esp_metadata_generated/

_generated_esp32p4.rs

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32p4"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32-P4"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32p4"
    };
    ("arch") => {
        "riscv"
    };
    ("cores") => {
        2
    };
    ("cores", str) => {
        stringify!(2)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp32-p4_technical_reference_manual_en.pdf"
    };
    ("gpio.version") => {
        3
    };
    ("gpio.version", str) => {
        stringify!(3)
    };
    ("gpio.has_input_sync") => {
        true
    };
    ("gpio.gpio_function") => {
        1
    };
    ("gpio.gpio_function", str) => {
        stringify!(1)
    };
    ("gpio.constant_0_input") => {
        62
    };
    ("gpio.constant_0_input", str) => {
        stringify!(62)
    };
    ("gpio.constant_1_input") => {
        63
    };
    ("gpio.constant_1_input", str) => {
        stringify!(63)
    };
    ("gpio.remap_iomux_pin_registers") => {
        false
    };
    ("gpio.func_in_sel_offset") => {
        1
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(1)
    };
    ("gpio.need_soft_isolate_during_pd") => {
        false
    };
    ("gpio.has_bank_1") => {
        true
    };
    ("gpio.input_signal_max") => {
        249
    };
    ("gpio.input_signal_max", str) => {
        stringify!(249)
    };
    ("gpio.output_signal_max") => {
        256
    };
    ("gpio.output_signal_max", str) => {
        stringify!(256)
    };
    ("dedicated_gpio.version") => {
        "riscv_v2"
    };
    ("dedicated_gpio.needs_initialization") => {
        false
    };
    ("dedicated_gpio.channel_count") => {
        8
    };
    ("dedicated_gpio.channel_count", str) => {
        stringify!(8)
    };
    ("lp_io.version") => {
        "esp32p4"
    };
    ("lp_io.has_gpio_matrix") => {
        true
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.version") => {
        2
    };
    ("uart.version", str) => {
        stringify!(2)
    };
    ("uart.peripheral_controls_mem_clk") => {
        false
    };
    ("uart.has_sclk_divider") => {
        false
    };
    ("uart.has_sclk_enable") => {
        false
    };
    ("uhci.combined_uart_selector_field") => {
        true
    };
    ("i2c_master.version") => {
        4
    };
    ("i2c_master.version", str) => {
        stringify!(4)
    };
    ("i2c_master.has_fsm_timeouts") => {
        true
    };
    ("i2c_master.has_hw_bus_clear") => {
        true
    };
    ("i2c_master.has_bus_timeout_enable") => {
        true
    };
    ("i2c_master.separate_filter_config_registers") => {
        false
    };
    ("i2c_master.can_estimate_nack_reason") => {
        true
    };
    ("i2c_master.has_conf_update") => {
        true
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        false
    };
    ("i2c_master.has_arbitration_en") => {
        true
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        false
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        false
    };
    ("i2c_master.has_pd_en") => {
        true
    };
    ("i2c_master.max_bus_timeout") => {
        31
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(31)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        32
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(32)
    };
    ("lp_i2c_master.version") => {
        "lp_i2c"
    };
    ("lp_i2c_master.fifo_size") => {
        16
    };
    ("lp_i2c_master.fifo_size", str) => {
        stringify!(16)
    };
    ("spi_master.version") => {
        3
    };
    ("spi_master.version", str) => {
        stringify!(3)
    };
    ("spi_master.fifo_size") => {
        64
    };
    ("spi_master.fifo_size", str) => {
        stringify!(64)
    };
    ("spi_master.bit_order_is_bool") => {
        false
    };
    ("spi_master.has_octal") => {
        false
    };
    ("spi_master.has_app_interrupts") => {
        false
    };
    ("spi_master.has_dma_segmented_transfer") => {
        false
    };
    ("spi_master.has_clk_pre_div") => {
        false
    };
    ("spi_master.dma_can_access_flash") => {
        false
    };
    ("i2s.version") => {
        3
    };
    ("i2s.version", str) => {
        stringify!(3)
    };
    ("i2s.mclk_divider_bit_width") => {
        9
    };
    ("i2s.mclk_divider_bit_width", str) => {
        stringify!(9)
    };
    ("i2s.max_ws_width") => {
        128
    };
    ("i2s.max_ws_width", str) => {
        stringify!(128)
    };
    ("i2s.clock_configured_by_pcr") => {
        false
    };
    ("i2s.clock_configured_by_hp_sys_clkrst") => {
        true
    };
    ("i2s.supports_pdm_rx_hp_filter") => {
        true
    };
    ("i2s.supports_pdm_tx") => {
        true
    };
    ("i2s.supports_pdm_rx") => {
        true
    };
    ("i2s.supports_pcm2pdm") => {
        true
    };
    ("i2s.supports_pdm2pcm") => {
        true
    };
    ("rmt.ram_start") => {
        1342842880
    };
    ("rmt.ram_start", str) => {
        stringify!(1342842880)
    };
    ("rmt.channel_ram_size") => {
        48
    };
    ("rmt.channel_ram_size", str) => {
        stringify!(48)
    };
    ("rmt.has_tx_immediate_stop") => {
        true
    };
    ("rmt.has_tx_loop_count") => {
        true
    };
    ("rmt.has_tx_loop_auto_stop") => {
        true
    };
    ("rmt.has_tx_carrier_data_only") => {
        true
    };
    ("rmt.has_tx_sync") => {
        true
    };
    ("rmt.has_rx_wrap") => {
        true
    };
    ("rmt.has_rx_demodulation") => {
        true
    };
    ("rmt.has_per_channel_clock") => {
        false
    };
    ("sdmmc.delay_phase_num") => {
        8
    };
    ("sdmmc.delay_phase_num", str) => {
        stringify!(8)
    };
    ("sdmmc.has_iomux") => {
        true
    };
    ("sdmmc.has_gpio_matrix") => {
        true
    };
    ("sdmmc.psram_dma") => {
        true
    };
    ("sdmmc.uhs") => {
        false
    };
    ("usb_otg.fifo_depth_words") => {
        200
    };
    ("usb_otg.fifo_depth_words", str) => {
        stringify!(200)
    };
    ("usb_otg_hs.fifo_depth_words") => {
        896
    };
    ("usb_otg_hs.fifo_depth_words", str) => {
        stringify!(896)
    };
    ("ethernet.mii_via_gpio_matrix") => {
        true
    };
    ("ethernet.rx_store_and_forward") => {
        false
    };
    ("ethernet.rx_checksum_offload") => {
        true
    };
    ("ethernet.tx_checksum_offload") => {
        false
    };
    ("ethernet.dma_burst_len") => {
        32
    };
    ("ethernet.dma_burst_len", str) => {
        stringify!(32)
    };
    ("ethernet.has_rgmii") => {
        false
    };
    ("adc.line_calibration") => {
        true
    };
    ("adc.curve_calibration") => {
        true
    };
    ("adc.basic_calibration") => {
        true
    };
    ("adc.calibration_v1_scheme_supported") => {
        true
    };
    ("adc.channel_compensation") => {
        true
    };
    ("adc.pcr_clock") => {
        false
    };
    ("adc.pcr_sar_clk_div") => {
        false
    };
    ("adc.sar_power_override") => {
        false
    };
    ("sdm.channel_count") => {
        8
    };
    ("sdm.channel_count", str) => {
        stringify!(8)
    };
    ("timergroup.timg_has_timer1") => {
        true
    };
    ("timergroup.timg_has_divcnt_rst") => {
        true
    };
    ("timergroup.wdt_has_conf_update") => {
        true
    };
    ("aes.has_split_text_registers") => {
        true
    };
    ("aes.endianness_configurable") => {
        false
    };
    ("ecc.zero_extend_writes") => {
        false
    };
    ("ecc.separate_jacobian_point_memory") => {
        true
    };
    ("ecc.has_memory_clock_gate") => {
        true
    };
    ("ecc.supports_enhanced_security") => {
        true
    };
    ("ecc.mem_block_size") => {
        48
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rng.is_lp_sys") => {
        false
    };
    ("rsa.version") => {
        3
    };
    ("rsa.version", str) => {
        stringify!(3)
    };
    ("rsa.size_increment") => {
        32
    };
    ("rsa.size_increment", str) => {
        stringify!(32)
    };
    ("rsa.memory_size_bytes") => {
        512
    };
    ("rsa.memory_size_bytes", str) => {
        stringify!(512)
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("sleep.rejectable_mask") => {
        14845
    };
    ("sleep.ext1_version") => {
        3
    };
    ("sleep.ext1_version", str) => {
        stringify!(3)
    };
    ("sleep.pin_wakeup_version") => {
        3
    };
    ("sleep.pin_wakeup_version", str) => {
        stringify!(3)
    };
    ("sleep.deep_sleep_needs_gpio_isolation") => {
        false
    };
    ("dma.mem2mem_requires_peripheral") => {
        false
    };
    ("dma.ext_mem_configurable_block_size") => {
        false
    };
    ("dma.separate_in_out_interrupts") => {
        true
    };
    ("dma.gdma_version") => {
        2
    };
    ("dma.gdma_version", str) => {
        stringify!(2)
    };
    ("interrupts.status_registers") => {
        5
    };
    ("interrupts.status_registers", str) => {
        stringify!(5)
    };
    ("interrupts.disabled_interrupt") => {
        0
    };
    ("mmu.page_size") => {
        65536
    };
    ("mmu.page_size", str) => {
        stringify!(65536)
    };
    ("mmu.entry_num") => {
        1024
    };
    ("mmu.entry_num", str) => {
        stringify!(1024)
    };
    ("psram.octal_spi") => {
        true
    };
    ("psram.hex_spi") => {
        true
    };
    ("psram.extmem_origin") => {
        1207959552
    };
    ("psram.extmem_origin", str) => {
        stringify!(1207959552)
    };
    ("rom.has_crc_le") => {
        true
    };
    ("rom.has_crc_be") => {
        true
    };
    ("rom.has_md5_bsd") => {
        true
    };
    ("rom.has_md5_mbedtls") => {
        false
    };
    ("soc.cpu_has_branch_predictor") => {
        true
    };
    ("soc.cpu_has_csr_pc") => {
        false
    };
    ("soc.cpu_has_zcmp_workaround") => {
        true
    };
    ("soc.multi_core_enabled") => {
        true
    };
    ("soc.internal_memory_cached") => {
        true
    };
    ("soc.has_swd_watchdog") => {
        true
    };
    ("soc.cpu_mcause_mask") => {
        63
    };
    ("soc.cpu_mcause_mask", str) => {
        stringify!(63)
    };
    ("soc.cpu_pmp_granularity") => {
        128
    };
    ("soc.cpu_pmp_granularity", str) => {
        stringify!(128)
    };
    ("clock_tree.iomux_function_clock.source") => {
        [crate ::soc::clocks::IomuxFunctionClockSource::XtalClk, crate
        ::soc::clocks::IomuxFunctionClockSource::PllF80m]
    };
    ("clock_tree.iomux_function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.cpu_root_clk") => {
        [crate ::soc::clocks::CpuRootClkConfig::Xtal, crate
        ::soc::clocks::CpuRootClkConfig::Cpll, crate
        ::soc::clocks::CpuRootClkConfig::RcFast]
    };
    ("clock_tree.cpu_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.mem_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.sys_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.apb_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.lp_fast_clk") => {
        [crate ::soc::clocks::LpFastClkConfig::RcFast, crate
        ::soc::clocks::LpFastClkConfig::XtalD2]
    };
    ("clock_tree.lp_slow_clk") => {
        [crate ::soc::clocks::LpSlowClkConfig::RcSlow, #[cfg(use_xtal32k)] crate
        ::soc::clocks::LpSlowClkConfig::Xtal32k, crate
        ::soc::clocks::LpSlowClkConfig::OscSlow]
    };
    ("clock_tree.crypto_clk") => {
        [crate ::soc::clocks::CryptoClkConfig::Xtal, crate
        ::soc::clocks::CryptoClkConfig::RcFast, crate
        ::soc::clocks::CryptoClkConfig::PllF240m, crate
        ::soc::clocks::CryptoClkConfig::PllF160m]
    };
    ("clock_tree.timg_calibration_clock") => {
        [crate ::soc::clocks::TimgCalibrationClockConfig::MpllClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::SpllClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::CpllClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcFastDivClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcSlowClk, #[cfg(use_xtal32k)] crate
        ::soc::clocks::TimgCalibrationClockConfig::Xtal32kClk]
    };
    ("clock_tree.psram.function_clock") => {
        [crate ::soc::clocks::PsramFunctionClockConfig::Xtal, crate
        ::soc::clocks::PsramFunctionClockConfig::Mpll, crate
        ::soc::clocks::PsramFunctionClockConfig::Spll, crate
        ::soc::clocks::PsramFunctionClockConfig::Cpll]
    };
    ("clock_tree.uart.function_clock.sclk") => {
        [crate ::soc::clocks::UartFunctionClockSclk::Xtal, crate
        ::soc::clocks::UartFunctionClockSclk::PllF80m, crate
        ::soc::clocks::UartFunctionClockSclk::RcFast]
    };
    ("clock_tree.uart.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 4095)
    };
    ("clock_tree.timg.function_clock") => {
        [crate ::soc::clocks::TimgFunctionClockConfig::XtalClk, crate
        ::soc::clocks::TimgFunctionClockConfig::RcFastClk, crate
        ::soc::clocks::TimgFunctionClockConfig::PllF80m]
    };
    ("clock_tree.timg.wdt_clock") => {
        [crate ::soc::clocks::TimgWdtClockConfig::XtalClk, crate
        ::soc::clocks::TimgWdtClockConfig::PllF80m, crate
        ::soc::clocks::TimgWdtClockConfig::RcFastClk]
    };
    ("clock_tree.i2c.function_clock.sclk") => {
        [crate ::soc::clocks::I2cFunctionClockSclk::Xtal, crate
        ::soc::clocks::I2cFunctionClockSclk::RcFast]
    };
    ("clock_tree.i2c.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.rmt.sclk") => {
        [crate ::soc::clocks::RmtSclkConfig::PllF80m, crate
        ::soc::clocks::RmtSclkConfig::RcFastClk, crate
        ::soc::clocks::RmtSclkConfig::XtalClk]
    };
    ("clock_tree.spi.function_clock") => {
        [crate ::soc::clocks::SpiFunctionClockConfig::Xtal, crate
        ::soc::clocks::SpiFunctionClockConfig::RcFast, crate
        ::soc::clocks::SpiFunctionClockConfig::Spll]
    };
    ("clock_tree.i2s.tx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate
        ::soc::clocks::I2sClkSclk::PllF160m]
    };
    ("clock_tree.i2s.tx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.tx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.tx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.rx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate
        ::soc::clocks::I2sClkSclk::PllF160m]
    };
    ("clock_tree.i2s.rx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.rx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.rx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.mclk_out") => {
        [crate ::soc::clocks::I2sMclkOutConfig::Tx, crate
        ::soc::clocks::I2sMclkOutConfig::Rx]
    };
    ("clock_tree.mipi_dsi.dpi_clk.sclk") => {
        [crate ::soc::clocks::MipiDsiDpiClkSclk::Xtal, crate
        ::soc::clocks::MipiDsiDpiClkSclk::PllF240m, crate
        ::soc::clocks::MipiDsiDpiClkSclk::PllF160m]
    };
    ("clock_tree.mipi_dsi.dpi_clk.div_num") => {
        (0, 255)
    };
    ("clock_tree.mipi_dsi.phy_pll_refclk.sclk") => {
        [crate ::soc::clocks::MipiDsiPhyPllRefclkSclk::Xtal, crate
        ::soc::clocks::MipiDsiPhyPllRefclkSclk::Cpll, crate
        ::soc::clocks::MipiDsiPhyPllRefclkSclk::Spll, crate
        ::soc::clocks::MipiDsiPhyPllRefclkSclk::Mpll]
    };
    ("clock_tree.mipi_dsi.phy_pll_refclk.div_num") => {
        (0, 255)
    };
    ("clock_tree.mipi_dsi.phy_cfg_clk") => {
        [crate ::soc::clocks::MipiDsiPhyCfgClkConfig::PllF20m, crate
        ::soc::clocks::MipiDsiPhyCfgClkConfig::RcFast, crate
        ::soc::clocks::MipiDsiPhyCfgClkConfig::PllF25m]
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dedicated_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dedicated_gpio { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_dedicated_gpio!((0));
        _for_each_inner_dedicated_gpio!((1)); _for_each_inner_dedicated_gpio!((2));
        _for_each_inner_dedicated_gpio!((3)); _for_each_inner_dedicated_gpio!((4));
        _for_each_inner_dedicated_gpio!((5)); _for_each_inner_dedicated_gpio!((6));
        _for_each_inner_dedicated_gpio!((7)); _for_each_inner_dedicated_gpio!((0, 0,
        CPU_GPIO_0)); _for_each_inner_dedicated_gpio!((0, 1, CPU_GPIO_1));
        _for_each_inner_dedicated_gpio!((0, 2, CPU_GPIO_2));
        _for_each_inner_dedicated_gpio!((0, 3, CPU_GPIO_3));
        _for_each_inner_dedicated_gpio!((0, 4, CPU_GPIO_4));
        _for_each_inner_dedicated_gpio!((0, 5, CPU_GPIO_5));
        _for_each_inner_dedicated_gpio!((0, 6, CPU_GPIO_6));
        _for_each_inner_dedicated_gpio!((0, 7, CPU_GPIO_7));
        _for_each_inner_dedicated_gpio!((1, 0, CPU_GPIO_8));
        _for_each_inner_dedicated_gpio!((1, 1, CPU_GPIO_9));
        _for_each_inner_dedicated_gpio!((1, 2, CPU_GPIO_10));
        _for_each_inner_dedicated_gpio!((1, 3, CPU_GPIO_11));
        _for_each_inner_dedicated_gpio!((1, 4, CPU_GPIO_12));
        _for_each_inner_dedicated_gpio!((1, 5, CPU_GPIO_13));
        _for_each_inner_dedicated_gpio!((1, 6, CPU_GPIO_14));
        _for_each_inner_dedicated_gpio!((1, 7, CPU_GPIO_15));
        _for_each_inner_dedicated_gpio!((channels(0), (1), (2), (3), (4), (5), (6),
        (7))); _for_each_inner_dedicated_gpio!((signals(0, 0, CPU_GPIO_0), (0, 1,
        CPU_GPIO_1), (0, 2, CPU_GPIO_2), (0, 3, CPU_GPIO_3), (0, 4, CPU_GPIO_4), (0, 5,
        CPU_GPIO_5), (0, 6, CPU_GPIO_6), (0, 7, CPU_GPIO_7), (1, 0, CPU_GPIO_8), (1, 1,
        CPU_GPIO_9), (1, 2, CPU_GPIO_10), (1, 3, CPU_GPIO_11), (1, 4, CPU_GPIO_12), (1,
        5, CPU_GPIO_13), (1, 6, CPU_GPIO_14), (1, 7, CPU_GPIO_15)));
    };
}
/// Defines the `LpInputSignal` and `LpOutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_io_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpInputSignal {
            LP_I2C_SCL   = 0,
            LP_I2C_SDA   = 1,
            LP_UART_RXD  = 2,
            LP_UART_CTSN = 3,
            LP_UART_DSRN = 4,
            LP_SPI_CK    = 5,
            LP_SPI_CS    = 6,
            LP_SPI_D     = 7,
            LP_SPI_Q     = 8,
            LP_I2S_I_BCK = 9,
            LP_I2S_I_SD  = 10,
            LP_I2S_I_WS  = 11,
            LP_I2S_O_BCK = 12,
            LP_I2S_O_WS  = 13,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpOutputSignal {
            LP_I2C_SCL   = 0,
            LP_I2C_SDA   = 1,
            LP_UART_TXD  = 2,
            LP_UART_RTSN = 3,
            LP_UART_DTRN = 4,
            LP_SPI_CK    = 5,
            LP_SPI_CS    = 6,
            LP_SPI_D     = 7,
            LP_SPI_Q     = 8,
            LP_I2S_I_BCK = 9,
            LP_I2S_O_SD  = 10,
            LP_I2S_I_WS  = 11,
            LP_I2S_O_BCK = 12,
            LP_I2S_O_WS  = 13,
        }
    };
}
/// This macro can be used to generate code for each channel of the RMT peripheral.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has three options for its "Individual matcher" case:
///
/// - `all`: `($num:literal)`
/// - `tx`: `($num:literal, $idx:literal)`
/// - `rx`: `($num:literal, $idx:literal)`
///
/// Macro fragments:
///
/// - `$num`: number of the channel, e.g. `0`
/// - `$idx`: index of the channel among channels of the same capability, e.g. `0`
///
/// Example data:
///
/// - `all`: `(0)`
/// - `tx`: `(1, 1)`
/// - `rx`: `(2, 0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rmt_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rmt_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_rmt_channel!((0)); _for_each_inner_rmt_channel!((1));
        _for_each_inner_rmt_channel!((2)); _for_each_inner_rmt_channel!((3));
        _for_each_inner_rmt_channel!((4)); _for_each_inner_rmt_channel!((5));
        _for_each_inner_rmt_channel!((6)); _for_each_inner_rmt_channel!((7));
        _for_each_inner_rmt_channel!((0, 0)); _for_each_inner_rmt_channel!((1, 1));
        _for_each_inner_rmt_channel!((2, 2)); _for_each_inner_rmt_channel!((3, 3));
        _for_each_inner_rmt_channel!((4, 0)); _for_each_inner_rmt_channel!((5, 1));
        _for_each_inner_rmt_channel!((6, 2)); _for_each_inner_rmt_channel!((7, 3));
        _for_each_inner_rmt_channel!((all(0), (1), (2), (3), (4), (5), (6), (7)));
        _for_each_inner_rmt_channel!((tx(0, 0), (1, 1), (2, 2), (3, 3)));
        _for_each_inner_rmt_channel!((rx(4, 0), (5, 1), (6, 2), (7, 3)));
    };
}
/// This macro can be used to generate code for each slot of the SDMMC/SDIO host driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($slot:ident, $idx:literal, $iomux:literal, [$($clk:ident)?]
/// [$($cmd_in:ident)?] [$($cmd_out:ident)?] [$($data_in:ident),*] [$($data_out:ident),*]
/// [$($cd:ident)?] [$($wp:ident)?] [$($card_int:ident)?] [$($data_strobe:ident)?]
/// [$($rst:ident)?])`
///
/// Macro fragments:
///
/// - `$slot`: the name of the slot (`slot0`, `slot1`).
/// - `$idx`: the zero-based slot index.
/// - `$iomux`: `true` if the slot's clock/command/data signals are IO_MUX-routed.
/// - `$clk`, `$cmd_in`, `$cmd_out`, `$data_in`, `$data_out`: GPIO-matrix bus signal names (absent
///   for IO_MUX-routed slots).
/// - `$cd`, `$wp`, `$card_int`, `$data_strobe`, `$rst`: auxiliary signal names, each present only
///   when the slot routes that signal through the GPIO matrix.
///
/// Each optional signal is wrapped in brackets so the branch shape stays uniform: a set
/// signal appears as `[SIGNAL]`, an absent one as `[]`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdmmc {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdmmc { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_sdmmc!((slot0, 0, true, [], [], [], [], [],
        [SDHOST_CARD_DETECT_N_1], [SDHOST_CARD_WRITE_PRT_1], [SDHOST_CARD_INT_N_1],
        [SDHOST_DATA_STROBE_1], [SD_RST_N_1])); _for_each_inner_sdmmc!((slot1, 1, false,
        [SDHOST_CCLK_OUT_2], [SDHOST_CCMD_IN_2], [SDHOST_CCMD_OUT_2],
        [SDHOST_CDATA_IN_20, SDHOST_CDATA_IN_21, SDHOST_CDATA_IN_22, SDHOST_CDATA_IN_23,
        SDHOST_CDATA_IN_24, SDHOST_CDATA_IN_25, SDHOST_CDATA_IN_26, SDHOST_CDATA_IN_27],
        [SDHOST_CDATA_OUT_20, SDHOST_CDATA_OUT_21, SDHOST_CDATA_OUT_22,
        SDHOST_CDATA_OUT_23, SDHOST_CDATA_OUT_24, SDHOST_CDATA_OUT_25,
        SDHOST_CDATA_OUT_26, SDHOST_CDATA_OUT_27], [SDHOST_CARD_DETECT_N_2],
        [SDHOST_CARD_WRITE_PRT_2], [SDHOST_CARD_INT_N_2], [SDHOST_DATA_STROBE_2],
        [SD_RST_N_2])); _for_each_inner_sdmmc!((all(slot0, 0, true, [], [], [], [], [],
        [SDHOST_CARD_DETECT_N_1], [SDHOST_CARD_WRITE_PRT_1], [SDHOST_CARD_INT_N_1],
        [SDHOST_DATA_STROBE_1], [SD_RST_N_1]), (slot1, 1, false, [SDHOST_CCLK_OUT_2],
        [SDHOST_CCMD_IN_2], [SDHOST_CCMD_OUT_2], [SDHOST_CDATA_IN_20, SDHOST_CDATA_IN_21,
        SDHOST_CDATA_IN_22, SDHOST_CDATA_IN_23, SDHOST_CDATA_IN_24, SDHOST_CDATA_IN_25,
        SDHOST_CDATA_IN_26, SDHOST_CDATA_IN_27], [SDHOST_CDATA_OUT_20,
        SDHOST_CDATA_OUT_21, SDHOST_CDATA_OUT_22, SDHOST_CDATA_OUT_23,
        SDHOST_CDATA_OUT_24, SDHOST_CDATA_OUT_25, SDHOST_CDATA_OUT_26,
        SDHOST_CDATA_OUT_27], [SDHOST_CARD_DETECT_N_2], [SDHOST_CARD_WRITE_PRT_2],
        [SDHOST_CARD_INT_N_2], [SDHOST_DATA_STROBE_2], [SD_RST_N_2])));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdm_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdm_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_sdm_channel!((0, SDM_CH0, SdmCh0, GPIO_SD0));
        _for_each_inner_sdm_channel!((1, SDM_CH1, SdmCh1, GPIO_SD1));
        _for_each_inner_sdm_channel!((2, SDM_CH2, SdmCh2, GPIO_SD2));
        _for_each_inner_sdm_channel!((3, SDM_CH3, SdmCh3, GPIO_SD3));
        _for_each_inner_sdm_channel!((4, SDM_CH4, SdmCh4, GPIO_SD4));
        _for_each_inner_sdm_channel!((5, SDM_CH5, SdmCh5, GPIO_SD5));
        _for_each_inner_sdm_channel!((6, SDM_CH6, SdmCh6, GPIO_SD6));
        _for_each_inner_sdm_channel!((7, SDM_CH7, SdmCh7, GPIO_SD7));
        _for_each_inner_sdm_channel!((channels(0, SDM_CH0, SdmCh0, GPIO_SD0), (1,
        SDM_CH1, SdmCh1, GPIO_SD1), (2, SDM_CH2, SdmCh2, GPIO_SD2), (3, SDM_CH3, SdmCh3,
        GPIO_SD3), (4, SDM_CH4, SdmCh4, GPIO_SD4), (5, SDM_CH5, SdmCh5, GPIO_SD5), (6,
        SDM_CH6, SdmCh6, GPIO_SD6), (7, SDM_CH7, SdmCh7, GPIO_SD7)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_aes_key_length {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_aes_key_length { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_aes_key_length!((128));
        _for_each_inner_aes_key_length!((256)); _for_each_inner_aes_key_length!((128, 0,
        4)); _for_each_inner_aes_key_length!((256, 2, 6));
        _for_each_inner_aes_key_length!((bits(128), (256)));
        _for_each_inner_aes_key_length!((modes(128, 0, 4), (256, 2, 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_working_mode {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_working_mode { $(($pattern) => $code;)* ($other
        : tt) => {} } _for_each_inner_ecc_working_mode!((0, AffinePointMultiplication));
        _for_each_inner_ecc_working_mode!((2, AffinePointVerification));
        _for_each_inner_ecc_working_mode!((3, AffinePointVerificationAndMultiplication));
        _for_each_inner_ecc_working_mode!((4, JacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((5, AffinePointAddition));
        _for_each_inner_ecc_working_mode!((6, JacobianPointVerification));
        _for_each_inner_ecc_working_mode!((7,
        AffinePointVerificationAndJacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((8, ModularAddition));
        _for_each_inner_ecc_working_mode!((9, ModularSubtraction));
        _for_each_inner_ecc_working_mode!((10, ModularMultiplication));
        _for_each_inner_ecc_working_mode!((11, ModularDivision));
        _for_each_inner_ecc_working_mode!((all(0, AffinePointMultiplication), (2,
        AffinePointVerification), (3, AffinePointVerificationAndMultiplication), (4,
        JacobianPointMultiplication), (5, AffinePointAddition), (6,
        JacobianPointVerification), (7,
        AffinePointVerificationAndJacobianPointMultiplication), (8, ModularAddition), (9,
        ModularSubtraction), (10, ModularMultiplication), (11, ModularDivision)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_curve {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_curve { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_ecc_curve!((0, P192, 192));
        _for_each_inner_ecc_curve!((1, P256, 256)); _for_each_inner_ecc_curve!((2, P384,
        384)); _for_each_inner_ecc_curve!((all(0, P192, 192), (1, P256, 256), (2, P384,
        384)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_exponentiation {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_exponentiation { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_exponentiation!((32));
        _for_each_inner_rsa_exponentiation!((64));
        _for_each_inner_rsa_exponentiation!((96));
        _for_each_inner_rsa_exponentiation!((128));
        _for_each_inner_rsa_exponentiation!((160));
        _for_each_inner_rsa_exponentiation!((192));
        _for_each_inner_rsa_exponentiation!((224));
        _for_each_inner_rsa_exponentiation!((256));
        _for_each_inner_rsa_exponentiation!((288));
        _for_each_inner_rsa_exponentiation!((320));
        _for_each_inner_rsa_exponentiation!((352));
        _for_each_inner_rsa_exponentiation!((384));
        _for_each_inner_rsa_exponentiation!((416));
        _for_each_inner_rsa_exponentiation!((448));
        _for_each_inner_rsa_exponentiation!((480));
        _for_each_inner_rsa_exponentiation!((512));
        _for_each_inner_rsa_exponentiation!((544));
        _for_each_inner_rsa_exponentiation!((576));
        _for_each_inner_rsa_exponentiation!((608));
        _for_each_inner_rsa_exponentiation!((640));
        _for_each_inner_rsa_exponentiation!((672));
        _for_each_inner_rsa_exponentiation!((704));
        _for_each_inner_rsa_exponentiation!((736));
        _for_each_inner_rsa_exponentiation!((768));
        _for_each_inner_rsa_exponentiation!((800));
        _for_each_inner_rsa_exponentiation!((832));
        _for_each_inner_rsa_exponentiation!((864));
        _for_each_inner_rsa_exponentiation!((896));
        _for_each_inner_rsa_exponentiation!((928));
        _for_each_inner_rsa_exponentiation!((960));
        _for_each_inner_rsa_exponentiation!((992));
        _for_each_inner_rsa_exponentiation!((1024));
        _for_each_inner_rsa_exponentiation!((1056));
        _for_each_inner_rsa_exponentiation!((1088));
        _for_each_inner_rsa_exponentiation!((1120));
        _for_each_inner_rsa_exponentiation!((1152));
        _for_each_inner_rsa_exponentiation!((1184));
        _for_each_inner_rsa_exponentiation!((1216));
        _for_each_inner_rsa_exponentiation!((1248));
        _for_each_inner_rsa_exponentiation!((1280));
        _for_each_inner_rsa_exponentiation!((1312));
        _for_each_inner_rsa_exponentiation!((1344));
        _for_each_inner_rsa_exponentiation!((1376));
        _for_each_inner_rsa_exponentiation!((1408));
        _for_each_inner_rsa_exponentiation!((1440));
        _for_each_inner_rsa_exponentiation!((1472));
        _for_each_inner_rsa_exponentiation!((1504));
        _for_each_inner_rsa_exponentiation!((1536));
        _for_each_inner_rsa_exponentiation!((1568));
        _for_each_inner_rsa_exponentiation!((1600));
        _for_each_inner_rsa_exponentiation!((1632));
        _for_each_inner_rsa_exponentiation!((1664));
        _for_each_inner_rsa_exponentiation!((1696));
        _for_each_inner_rsa_exponentiation!((1728));
        _for_each_inner_rsa_exponentiation!((1760));
        _for_each_inner_rsa_exponentiation!((1792));
        _for_each_inner_rsa_exponentiation!((1824));
        _for_each_inner_rsa_exponentiation!((1856));
        _for_each_inner_rsa_exponentiation!((1888));
        _for_each_inner_rsa_exponentiation!((1920));
        _for_each_inner_rsa_exponentiation!((1952));
        _for_each_inner_rsa_exponentiation!((1984));
        _for_each_inner_rsa_exponentiation!((2016));
        _for_each_inner_rsa_exponentiation!((2048));
        _for_each_inner_rsa_exponentiation!((2080));
        _for_each_inner_rsa_exponentiation!((2112));
        _for_each_inner_rsa_exponentiation!((2144));
        _for_each_inner_rsa_exponentiation!((2176));
        _for_each_inner_rsa_exponentiation!((2208));
        _for_each_inner_rsa_exponentiation!((2240));
        _for_each_inner_rsa_exponentiation!((2272));
        _for_each_inner_rsa_exponentiation!((2304));
        _for_each_inner_rsa_exponentiation!((2336));
        _for_each_inner_rsa_exponentiation!((2368));
        _for_each_inner_rsa_exponentiation!((2400));
        _for_each_inner_rsa_exponentiation!((2432));
        _for_each_inner_rsa_exponentiation!((2464));
        _for_each_inner_rsa_exponentiation!((2496));
        _for_each_inner_rsa_exponentiation!((2528));
        _for_each_inner_rsa_exponentiation!((2560));
        _for_each_inner_rsa_exponentiation!((2592));
        _for_each_inner_rsa_exponentiation!((2624));
        _for_each_inner_rsa_exponentiation!((2656));
        _for_each_inner_rsa_exponentiation!((2688));
        _for_each_inner_rsa_exponentiation!((2720));
        _for_each_inner_rsa_exponentiation!((2752));
        _for_each_inner_rsa_exponentiation!((2784));
        _for_each_inner_rsa_exponentiation!((2816));
        _for_each_inner_rsa_exponentiation!((2848));
        _for_each_inner_rsa_exponentiation!((2880));
        _for_each_inner_rsa_exponentiation!((2912));
        _for_each_inner_rsa_exponentiation!((2944));
        _for_each_inner_rsa_exponentiation!((2976));
        _for_each_inner_rsa_exponentiation!((3008));
        _for_each_inner_rsa_exponentiation!((3040));
        _for_each_inner_rsa_exponentiation!((3072));
        _for_each_inner_rsa_exponentiation!((3104));
        _for_each_inner_rsa_exponentiation!((3136));
        _for_each_inner_rsa_exponentiation!((3168));
        _for_each_inner_rsa_exponentiation!((3200));
        _for_each_inner_rsa_exponentiation!((3232));
        _for_each_inner_rsa_exponentiation!((3264));
        _for_each_inner_rsa_exponentiation!((3296));
        _for_each_inner_rsa_exponentiation!((3328));
        _for_each_inner_rsa_exponentiation!((3360));
        _for_each_inner_rsa_exponentiation!((3392));
        _for_each_inner_rsa_exponentiation!((3424));
        _for_each_inner_rsa_exponentiation!((3456));
        _for_each_inner_rsa_exponentiation!((3488));
        _for_each_inner_rsa_exponentiation!((3520));
        _for_each_inner_rsa_exponentiation!((3552));
        _for_each_inner_rsa_exponentiation!((3584));
        _for_each_inner_rsa_exponentiation!((3616));
        _for_each_inner_rsa_exponentiation!((3648));
        _for_each_inner_rsa_exponentiation!((3680));
        _for_each_inner_rsa_exponentiation!((3712));
        _for_each_inner_rsa_exponentiation!((3744));
        _for_each_inner_rsa_exponentiation!((3776));
        _for_each_inner_rsa_exponentiation!((3808));
        _for_each_inner_rsa_exponentiation!((3840));
        _for_each_inner_rsa_exponentiation!((3872));
        _for_each_inner_rsa_exponentiation!((3904));
        _for_each_inner_rsa_exponentiation!((3936));
        _for_each_inner_rsa_exponentiation!((3968));
        _for_each_inner_rsa_exponentiation!((4000));
        _for_each_inner_rsa_exponentiation!((4032));
        _for_each_inner_rsa_exponentiation!((4064));
        _for_each_inner_rsa_exponentiation!((4096));
        _for_each_inner_rsa_exponentiation!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536),
        (1568), (1600), (1632), (1664), (1696), (1728), (1760), (1792), (1824), (1856),
        (1888), (1920), (1952), (1984), (2016), (2048), (2080), (2112), (2144), (2176),
        (2208), (2240), (2272), (2304), (2336), (2368), (2400), (2432), (2464), (2496),
        (2528), (2560), (2592), (2624), (2656), (2688), (2720), (2752), (2784), (2816),
        (2848), (2880), (2912), (2944), (2976), (3008), (3040), (3072), (3104), (3136),
        (3168), (3200), (3232), (3264), (3296), (3328), (3360), (3392), (3424), (3456),
        (3488), (3520), (3552), (3584), (3616), (3648), (3680), (3712), (3744), (3776),
        (3808), (3840), (3872), (3904), (3936), (3968), (4000), (4032), (4064), (4096)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_multiplication {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_multiplication { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_multiplication!((32));
        _for_each_inner_rsa_multiplication!((64));
        _for_each_inner_rsa_multiplication!((96));
        _for_each_inner_rsa_multiplication!((128));
        _for_each_inner_rsa_multiplication!((160));
        _for_each_inner_rsa_multiplication!((192));
        _for_each_inner_rsa_multiplication!((224));
        _for_each_inner_rsa_multiplication!((256));
        _for_each_inner_rsa_multiplication!((288));
        _for_each_inner_rsa_multiplication!((320));
        _for_each_inner_rsa_multiplication!((352));
        _for_each_inner_rsa_multiplication!((384));
        _for_each_inner_rsa_multiplication!((416));
        _for_each_inner_rsa_multiplication!((448));
        _for_each_inner_rsa_multiplication!((480));
        _for_each_inner_rsa_multiplication!((512));
        _for_each_inner_rsa_multiplication!((544));
        _for_each_inner_rsa_multiplication!((576));
        _for_each_inner_rsa_multiplication!((608));
        _for_each_inner_rsa_multiplication!((640));
        _for_each_inner_rsa_multiplication!((672));
        _for_each_inner_rsa_multiplication!((704));
        _for_each_inner_rsa_multiplication!((736));
        _for_each_inner_rsa_multiplication!((768));
        _for_each_inner_rsa_multiplication!((800));
        _for_each_inner_rsa_multiplication!((832));
        _for_each_inner_rsa_multiplication!((864));
        _for_each_inner_rsa_multiplication!((896));
        _for_each_inner_rsa_multiplication!((928));
        _for_each_inner_rsa_multiplication!((960));
        _for_each_inner_rsa_multiplication!((992));
        _for_each_inner_rsa_multiplication!((1024));
        _for_each_inner_rsa_multiplication!((1056));
        _for_each_inner_rsa_multiplication!((1088));
        _for_each_inner_rsa_multiplication!((1120));
        _for_each_inner_rsa_multiplication!((1152));
        _for_each_inner_rsa_multiplication!((1184));
        _for_each_inner_rsa_multiplication!((1216));
        _for_each_inner_rsa_multiplication!((1248));
        _for_each_inner_rsa_multiplication!((1280));
        _for_each_inner_rsa_multiplication!((1312));
        _for_each_inner_rsa_multiplication!((1344));
        _for_each_inner_rsa_multiplication!((1376));
        _for_each_inner_rsa_multiplication!((1408));
        _for_each_inner_rsa_multiplication!((1440));
        _for_each_inner_rsa_multiplication!((1472));
        _for_each_inner_rsa_multiplication!((1504));
        _for_each_inner_rsa_multiplication!((1536));
        _for_each_inner_rsa_multiplication!((1568));
        _for_each_inner_rsa_multiplication!((1600));
        _for_each_inner_rsa_multiplication!((1632));
        _for_each_inner_rsa_multiplication!((1664));
        _for_each_inner_rsa_multiplication!((1696));
        _for_each_inner_rsa_multiplication!((1728));
        _for_each_inner_rsa_multiplication!((1760));
        _for_each_inner_rsa_multiplication!((1792));
        _for_each_inner_rsa_multiplication!((1824));
        _for_each_inner_rsa_multiplication!((1856));
        _for_each_inner_rsa_multiplication!((1888));
        _for_each_inner_rsa_multiplication!((1920));
        _for_each_inner_rsa_multiplication!((1952));
        _for_each_inner_rsa_multiplication!((1984));
        _for_each_inner_rsa_multiplication!((2016));
        _for_each_inner_rsa_multiplication!((2048));
        _for_each_inner_rsa_multiplication!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536),
        (1568), (1600), (1632), (1664), (1696), (1728), (1760), (1792), (1824), (1856),
        (1888), (1920), (1952), (1984), (2016), (2048)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha224, "SHA-224"(sizes : 64, 28, 8)
        (insecure_against : "length extension"), 1));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 2));
        _for_each_inner_sha_algorithm!((Sha384, "SHA-384"(sizes : 128, 48, 16)
        (insecure_against :), 3)); _for_each_inner_sha_algorithm!((Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 4));
        _for_each_inner_sha_algorithm!((Sha512_224, "SHA-512/224"(sizes : 128, 28, 16)
        (insecure_against :), 5)); _for_each_inner_sha_algorithm!((Sha512_256,
        "SHA-512/256"(sizes : 128, 32, 16) (insecure_against :), 6));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha224,
        "SHA-224"(sizes : 64, 28, 8) (insecure_against : "length extension"), 1),
        (Sha256, "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"),
        2), (Sha384, "SHA-384"(sizes : 128, 48, 16) (insecure_against :), 3), (Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 4),
        (Sha512_224, "SHA-512/224"(sizes : 128, 28, 16) (insecure_against :), 5),
        (Sha512_256, "SHA-512/256"(sizes : 128, 32, 16) (insecure_against :), 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_wakeup_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_wakeup_source { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_wakeup_source!((Sdio, 0));
        _for_each_inner_wakeup_source!((Gpio, 2)); _for_each_inner_wakeup_source!((Usb,
        3)); _for_each_inner_wakeup_source!((Uart4, 4));
        _for_each_inner_wakeup_source!((Uart3, 5));
        _for_each_inner_wakeup_source!((Uart2, 6));
        _for_each_inner_wakeup_source!((Uart1, 7));
        _for_each_inner_wakeup_source!((Uart0, 8));
        _for_each_inner_wakeup_source!((Touch, 11));
        _for_each_inner_wakeup_source!((Ext1, 12));
        _for_each_inner_wakeup_source!((Timer, 13));
        _for_each_inner_wakeup_source!((all(Sdio, 0), (Gpio, 2), (Usb, 3), (Uart4, 4),
        (Uart3, 5), (Uart2, 6), (Uart1, 7), (Uart0, 8), (Touch, 11), (Ext1, 12), (Timer,
        13)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_engine!(("AHB_GDMA"));
        _for_each_inner_dma_engine!(("AXI_GDMA")); _for_each_inner_dma_engine!(("VDMA"));
        _for_each_inner_dma_engine!((all("AHB_GDMA"), ("AXI_GDMA"), ("VDMA")));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH1));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH2));
        _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH0));
        _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH1));
        _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH2));
        _for_each_inner_dma_channel!(("VDMA", VDMA_CH0));
        _for_each_inner_dma_channel!(("VDMA", VDMA_CH1));
        _for_each_inner_dma_channel!(("VDMA", VDMA_CH2));
        _for_each_inner_dma_channel!(("VDMA", VDMA_CH3));
        _for_each_inner_dma_channel!(("AHB_GDMA", any_channel = AhbGdmaChannel));
        _for_each_inner_dma_channel!(("AXI_GDMA", any_channel = AxiGdmaChannel));
        _for_each_inner_dma_channel!(("VDMA", any_channel = VdmaChannel));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0, 0, interrupt_in =
        AHB_PDMA_IN_CH0, interrupt_out = AHB_PDMA_OUT_CH0, compatible = [UHCI0, I2S0,
        I2S1, I2S2])); _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH1, 1, interrupt_in
        = AHB_PDMA_IN_CH1, interrupt_out = AHB_PDMA_OUT_CH1, compatible = [UHCI0, I2S0,
        I2S1, I2S2])); _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH2, 2, interrupt_in
        = AHB_PDMA_IN_CH2, interrupt_out = AHB_PDMA_OUT_CH2, compatible = [UHCI0, I2S0,
        I2S1, I2S2])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH0, 0,
        interrupt_in = AXI_PDMA_IN_CH0, interrupt_out = AXI_PDMA_OUT_CH0, compatible =
        [SPI2, SPI3, AES, SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH1,
        1, interrupt_in = AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, compatible =
        [SPI2, SPI3, AES, SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH2,
        2, interrupt_in = AXI_PDMA_IN_CH2, interrupt_out = AXI_PDMA_OUT_CH2, compatible =
        [SPI2, SPI3, AES, SHA])); _for_each_inner_dma_channel!(("VDMA", VDMA_CH0, 0,
        compatible = [])); _for_each_inner_dma_channel!(("VDMA", VDMA_CH1, 1, compatible
        = [])); _for_each_inner_dma_channel!(("VDMA", VDMA_CH2, 2, compatible = []));
        _for_each_inner_dma_channel!(("VDMA", VDMA_CH3, 3, compatible = []));
        _for_each_inner_dma_channel!((names("AHB_GDMA", DMA_CH0), ("AHB_GDMA", DMA_CH1),
        ("AHB_GDMA", DMA_CH2), ("AXI_GDMA", DMA_AXI_CH0), ("AXI_GDMA", DMA_AXI_CH1),
        ("AXI_GDMA", DMA_AXI_CH2), ("VDMA", VDMA_CH0), ("VDMA", VDMA_CH1), ("VDMA",
        VDMA_CH2), ("VDMA", VDMA_CH3)));
        _for_each_inner_dma_channel!((separate_any_type("AHB_GDMA", any_channel =
        AhbGdmaChannel), ("AXI_GDMA", any_channel = AxiGdmaChannel), ("VDMA", any_channel
        = VdmaChannel))); _for_each_inner_dma_channel!((shared));
        _for_each_inner_dma_channel!((split("AHB_GDMA", DMA_CH0, 0, interrupt_in =
        AHB_PDMA_IN_CH0, interrupt_out = AHB_PDMA_OUT_CH0, compatible = [UHCI0, I2S0,
        I2S1, I2S2]), ("AHB_GDMA", DMA_CH1, 1, interrupt_in = AHB_PDMA_IN_CH1,
        interrupt_out = AHB_PDMA_OUT_CH1, compatible = [UHCI0, I2S0, I2S1, I2S2]),
        ("AHB_GDMA", DMA_CH2, 2, interrupt_in = AHB_PDMA_IN_CH2, interrupt_out =
        AHB_PDMA_OUT_CH2, compatible = [UHCI0, I2S0, I2S1, I2S2]), ("AXI_GDMA",
        DMA_AXI_CH0, 0, interrupt_in = AXI_PDMA_IN_CH0, interrupt_out = AXI_PDMA_OUT_CH0,
        compatible = [SPI2, SPI3, AES, SHA]), ("AXI_GDMA", DMA_AXI_CH1, 1, interrupt_in =
        AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, compatible = [SPI2, SPI3, AES,
        SHA]), ("AXI_GDMA", DMA_AXI_CH2, 2, interrupt_in = AXI_PDMA_IN_CH2, interrupt_out
        = AXI_PDMA_OUT_CH2, compatible = [SPI2, SPI3, AES, SHA])));
        _for_each_inner_dma_channel!((no_own_interrupt("VDMA", VDMA_CH0, 0, compatible =
        []), ("VDMA", VDMA_CH1, 1, compatible = []), ("VDMA", VDMA_CH2, 2, compatible =
        []), ("VDMA", VDMA_CH3, 3, compatible = [])));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel_peri_pair {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel_peri_pair { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        DMA_CH0, UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0,
        I2S0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, I2S2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, I2S2));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, AES));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, AES));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, AES));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel =
        AhbGdmaChannel, I2S0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        any_channel = AhbGdmaChannel, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        I2S2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel =
        AxiGdmaChannel, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA",
        any_channel = AxiGdmaChannel, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel = AxiGdmaChannel,
        AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel =
        AxiGdmaChannel, SHA));
        _for_each_inner_dma_channel_peri_pair!((channels("AHB_GDMA", DMA_CH0, UHCI0),
        ("AHB_GDMA", DMA_CH0, I2S0), ("AHB_GDMA", DMA_CH0, I2S1), ("AHB_GDMA", DMA_CH0,
        I2S2), ("AHB_GDMA", DMA_CH1, UHCI0), ("AHB_GDMA", DMA_CH1, I2S0), ("AHB_GDMA",
        DMA_CH1, I2S1), ("AHB_GDMA", DMA_CH1, I2S2), ("AHB_GDMA", DMA_CH2, UHCI0),
        ("AHB_GDMA", DMA_CH2, I2S0), ("AHB_GDMA", DMA_CH2, I2S1), ("AHB_GDMA", DMA_CH2,
        I2S2), ("AXI_GDMA", DMA_AXI_CH0, SPI2), ("AXI_GDMA", DMA_AXI_CH0, SPI3),
        ("AXI_GDMA", DMA_AXI_CH0, AES), ("AXI_GDMA", DMA_AXI_CH0, SHA), ("AXI_GDMA",
        DMA_AXI_CH1, SPI2), ("AXI_GDMA", DMA_AXI_CH1, SPI3), ("AXI_GDMA", DMA_AXI_CH1,
        AES), ("AXI_GDMA", DMA_AXI_CH1, SHA), ("AXI_GDMA", DMA_AXI_CH2, SPI2),
        ("AXI_GDMA", DMA_AXI_CH2, SPI3), ("AXI_GDMA", DMA_AXI_CH2, AES), ("AXI_GDMA",
        DMA_AXI_CH2, SHA)));
        _for_each_inner_dma_channel_peri_pair!((any_channels("AHB_GDMA", any_channel =
        AhbGdmaChannel, UHCI0), ("AHB_GDMA", any_channel = AhbGdmaChannel, I2S0),
        ("AHB_GDMA", any_channel = AhbGdmaChannel, I2S1), ("AHB_GDMA", any_channel =
        AhbGdmaChannel, I2S2), ("AXI_GDMA", any_channel = AxiGdmaChannel, SPI2),
        ("AXI_GDMA", any_channel = AxiGdmaChannel, SPI3), ("AXI_GDMA", any_channel =
        AxiGdmaChannel, AES), ("AXI_GDMA", any_channel = AxiGdmaChannel, SHA)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_mem2mem_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_mem2mem_channel { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH1, 11)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, DMA_CH2, 12));
        _for_each_inner_mem2mem_channel!(("AXI_GDMA", AxiGdma, AxiGdmaChannel,
        DMA_AXI_CH0, 6)); _for_each_inner_mem2mem_channel!(("AXI_GDMA", AxiGdma,
        AxiGdmaChannel, DMA_AXI_CH1, 7)); _for_each_inner_mem2mem_channel!(("AXI_GDMA",
        AxiGdma, AxiGdmaChannel, DMA_AXI_CH2, 8));
        _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel, 1, 11, 2,
        12)); _for_each_inner_mem2mem_channel!(("AXI_GDMA", AxiGdma, AxiGdmaChannel, 0,
        6, 1, 7, 2, 8)); _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel)); _for_each_inner_mem2mem_channel!(("AXI_GDMA", AxiGdma,
        AxiGdmaChannel)); _for_each_inner_mem2mem_channel!((channels("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH1, 11), ("AHB_GDMA", AhbGdma, AhbGdmaChannel, DMA_CH2, 12),
        ("AXI_GDMA", AxiGdma, AxiGdmaChannel, DMA_AXI_CH0, 6), ("AXI_GDMA", AxiGdma,
        AxiGdmaChannel, DMA_AXI_CH1, 7), ("AXI_GDMA", AxiGdma, AxiGdmaChannel,
        DMA_AXI_CH2, 8))); _for_each_inner_mem2mem_channel!((erased("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, 1, 11, 2, 12), ("AXI_GDMA", AxiGdma, AxiGdmaChannel, 0, 6, 1, 7,
        2, 8))); _for_each_inner_mem2mem_channel!((engines("AHB_GDMA", AhbGdma,
        AhbGdmaChannel), ("AXI_GDMA", AxiGdma, AxiGdmaChannel)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_aes_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_aes_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_aes_dma_engine!(("AXI_GDMA", AxiGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_i2s_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_i2s_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_i2s_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_mipi_dsi_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_mipi_dsi_dma_engine { $(($pattern) => $code;)* ($other :
        tt) => {} } _with_inner_mipi_dsi_dma_engine!(("VDMA", VdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_sha_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_sha_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_sha_dma_engine!(("AXI_GDMA", AxiGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_master_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_master_dma_engine!(("AXI_GDMA", AxiGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_slave_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_slave_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_slave_dma_engine!(("AXI_GDMA", AxiGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_uhci_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_uhci_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_uhci_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_interrupt!(([disabled 0] 0));
        _for_each_inner_interrupt!(([reserved 0] 1));
        _for_each_inner_interrupt!(([reserved 1] 2));
        _for_each_inner_interrupt!(([reserved 2] 3));
        _for_each_inner_interrupt!(([reserved 3] 4));
        _for_each_inner_interrupt!(([reserved 4] 5));
        _for_each_inner_interrupt!(([reserved 5] 6));
        _for_each_inner_interrupt!(([reserved 6] 7));
        _for_each_inner_interrupt!(([reserved 7] 8));
        _for_each_inner_interrupt!(([reserved 8] 9));
        _for_each_inner_interrupt!(([reserved 9] 10));
        _for_each_inner_interrupt!(([reserved 10] 11));
        _for_each_inner_interrupt!(([reserved 11] 12));
        _for_each_inner_interrupt!(([reserved 12] 13));
        _for_each_inner_interrupt!(([reserved 13] 14));
        _for_each_inner_interrupt!(([reserved 14] 15));
        _for_each_inner_interrupt!(([vector 0] 16)); _for_each_inner_interrupt!(([vector
        1] 17)); _for_each_inner_interrupt!(([vector 2] 18));
        _for_each_inner_interrupt!(([vector 3] 19)); _for_each_inner_interrupt!(([vector
        4] 20)); _for_each_inner_interrupt!(([vector 5] 21));
        _for_each_inner_interrupt!(([vector 6] 22)); _for_each_inner_interrupt!(([vector
        7] 23)); _for_each_inner_interrupt!(([direct_bindable 0] 24));
        _for_each_inner_interrupt!(([direct_bindable 1] 25));
        _for_each_inner_interrupt!(([direct_bindable 2] 26));
        _for_each_inner_interrupt!(([direct_bindable 3] 27));
        _for_each_inner_interrupt!(([direct_bindable 4] 28));
        _for_each_inner_interrupt!(([direct_bindable 5] 29));
        _for_each_inner_interrupt!(([direct_bindable 6] 30));
        _for_each_inner_interrupt!(([direct_bindable 7] 31));
        _for_each_inner_interrupt!(([direct_bindable 8] 32));
        _for_each_inner_interrupt!(([direct_bindable 9] 33));
        _for_each_inner_interrupt!(([direct_bindable 10] 34));
        _for_each_inner_interrupt!(([direct_bindable 11] 35));
        _for_each_inner_interrupt!(([direct_bindable 12] 36));
        _for_each_inner_interrupt!(([direct_bindable 13] 37));
        _for_each_inner_interrupt!(([direct_bindable 14] 38));
        _for_each_inner_interrupt!(([direct_bindable 15] 39));
        _for_each_inner_interrupt!(([direct_bindable 16] 40));
        _for_each_inner_interrupt!(([direct_bindable 17] 41));
        _for_each_inner_interrupt!(([direct_bindable 18] 42));
        _for_each_inner_interrupt!(([direct_bindable 19] 43));
        _for_each_inner_interrupt!(([direct_bindable 20] 44));
        _for_each_inner_interrupt!(([direct_bindable 21] 45));
        _for_each_inner_interrupt!(([direct_bindable 22] 46));
        _for_each_inner_interrupt!(([direct_bindable 23] 47));
        _for_each_inner_interrupt!((all([disabled 0] 0), ([reserved 0] 1), ([reserved 1]
        2), ([reserved 2] 3), ([reserved 3] 4), ([reserved 4] 5), ([reserved 5] 6),
        ([reserved 6] 7), ([reserved 7] 8), ([reserved 8] 9), ([reserved 9] 10),
        ([reserved 10] 11), ([reserved 11] 12), ([reserved 12] 13), ([reserved 13] 14),
        ([reserved 14] 15), ([vector 0] 16), ([vector 1] 17), ([vector 2] 18), ([vector
        3] 19), ([vector 4] 20), ([vector 5] 21), ([vector 6] 22), ([vector 7] 23),
        ([direct_bindable 0] 24), ([direct_bindable 1] 25), ([direct_bindable 2] 26),
        ([direct_bindable 3] 27), ([direct_bindable 4] 28), ([direct_bindable 5] 29),
        ([direct_bindable 6] 30), ([direct_bindable 7] 31), ([direct_bindable 8] 32),
        ([direct_bindable 9] 33), ([direct_bindable 10] 34), ([direct_bindable 11] 35),
        ([direct_bindable 12] 36), ([direct_bindable 13] 37), ([direct_bindable 14] 38),
        ([direct_bindable 15] 39), ([direct_bindable 16] 40), ([direct_bindable 17] 41),
        ([direct_bindable 18] 42), ([direct_bindable 19] 43), ([direct_bindable 20] 44),
        ([direct_bindable 21] 45), ([direct_bindable 22] 46), ([direct_bindable 23]
        47)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_classified_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_classified_interrupt { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_classified_interrupt!(([direct_bindable 0]
        24)); _for_each_inner_classified_interrupt!(([direct_bindable 1] 25));
        _for_each_inner_classified_interrupt!(([direct_bindable 2] 26));
        _for_each_inner_classified_interrupt!(([direct_bindable 3] 27));
        _for_each_inner_classified_interrupt!(([direct_bindable 4] 28));
        _for_each_inner_classified_interrupt!(([direct_bindable 5] 29));
        _for_each_inner_classified_interrupt!(([direct_bindable 6] 30));
        _for_each_inner_classified_interrupt!(([direct_bindable 7] 31));
        _for_each_inner_classified_interrupt!(([direct_bindable 8] 32));
        _for_each_inner_classified_interrupt!(([direct_bindable 9] 33));
        _for_each_inner_classified_interrupt!(([direct_bindable 10] 34));
        _for_each_inner_classified_interrupt!(([direct_bindable 11] 35));
        _for_each_inner_classified_interrupt!(([direct_bindable 12] 36));
        _for_each_inner_classified_interrupt!(([direct_bindable 13] 37));
        _for_each_inner_classified_interrupt!(([direct_bindable 14] 38));
        _for_each_inner_classified_interrupt!(([direct_bindable 15] 39));
        _for_each_inner_classified_interrupt!(([direct_bindable 16] 40));
        _for_each_inner_classified_interrupt!(([direct_bindable 17] 41));
        _for_each_inner_classified_interrupt!(([direct_bindable 18] 42));
        _for_each_inner_classified_interrupt!(([direct_bindable 19] 43));
        _for_each_inner_classified_interrupt!(([direct_bindable 20] 44));
        _for_each_inner_classified_interrupt!(([direct_bindable 21] 45));
        _for_each_inner_classified_interrupt!(([direct_bindable 22] 46));
        _for_each_inner_classified_interrupt!(([direct_bindable 23] 47));
        _for_each_inner_classified_interrupt!(([vector 0] 16));
        _for_each_inner_classified_interrupt!(([vector 1] 17));
        _for_each_inner_classified_interrupt!(([vector 2] 18));
        _for_each_inner_classified_interrupt!(([vector 3] 19));
        _for_each_inner_classified_interrupt!(([vector 4] 20));
        _for_each_inner_classified_interrupt!(([vector 5] 21));
        _for_each_inner_classified_interrupt!(([vector 6] 22));
        _for_each_inner_classified_interrupt!(([vector 7] 23));
        _for_each_inner_classified_interrupt!(([reserved 0] 1));
        _for_each_inner_classified_interrupt!(([reserved 1] 2));
        _for_each_inner_classified_interrupt!(([reserved 2] 3));
        _for_each_inner_classified_interrupt!(([reserved 3] 4));
        _for_each_inner_classified_interrupt!(([reserved 4] 5));
        _for_each_inner_classified_interrupt!(([reserved 5] 6));
        _for_each_inner_classified_interrupt!(([reserved 6] 7));
        _for_each_inner_classified_interrupt!(([reserved 7] 8));
        _for_each_inner_classified_interrupt!(([reserved 8] 9));
        _for_each_inner_classified_interrupt!(([reserved 9] 10));
        _for_each_inner_classified_interrupt!(([reserved 10] 11));
        _for_each_inner_classified_interrupt!(([reserved 11] 12));
        _for_each_inner_classified_interrupt!(([reserved 12] 13));
        _for_each_inner_classified_interrupt!(([reserved 13] 14));
        _for_each_inner_classified_interrupt!(([reserved 14] 15));
        _for_each_inner_classified_interrupt!((direct_bindable([direct_bindable 0] 24),
        ([direct_bindable 1] 25), ([direct_bindable 2] 26), ([direct_bindable 3] 27),
        ([direct_bindable 4] 28), ([direct_bindable 5] 29), ([direct_bindable 6] 30),
        ([direct_bindable 7] 31), ([direct_bindable 8] 32), ([direct_bindable 9] 33),
        ([direct_bindable 10] 34), ([direct_bindable 11] 35), ([direct_bindable 12] 36),
        ([direct_bindable 13] 37), ([direct_bindable 14] 38), ([direct_bindable 15] 39),
        ([direct_bindable 16] 40), ([direct_bindable 17] 41), ([direct_bindable 18] 42),
        ([direct_bindable 19] 43), ([direct_bindable 20] 44), ([direct_bindable 21] 45),
        ([direct_bindable 22] 46), ([direct_bindable 23] 47)));
        _for_each_inner_classified_interrupt!((vector([vector 0] 16), ([vector 1] 17),
        ([vector 2] 18), ([vector 3] 19), ([vector 4] 20), ([vector 5] 21), ([vector 6]
        22), ([vector 7] 23))); _for_each_inner_classified_interrupt!((reserved([reserved
        0] 1), ([reserved 1] 2), ([reserved 2] 3), ([reserved 3] 4), ([reserved 4] 5),
        ([reserved 5] 6), ([reserved 6] 7), ([reserved 7] 8), ([reserved 8] 9),
        ([reserved 9] 10), ([reserved 10] 11), ([reserved 11] 12), ([reserved 12] 13),
        ([reserved 13] 14), ([reserved 14] 15)));
        _for_each_inner_classified_interrupt!((context_switch));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt_priority {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt_priority { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_interrupt_priority!((0, 1, Priority1,
        Level1)); _for_each_inner_interrupt_priority!((1, 2, Priority2, Level2));
        _for_each_inner_interrupt_priority!((2, 3, Priority3, Level3));
        _for_each_inner_interrupt_priority!((3, 4, Priority4, Level4));
        _for_each_inner_interrupt_priority!((4, 5, Priority5, Level5));
        _for_each_inner_interrupt_priority!((5, 6, Priority6, Level6));
        _for_each_inner_interrupt_priority!((6, 7, Priority7, Level7));
        _for_each_inner_interrupt_priority!((7, 8, Priority8, Level8));
        _for_each_inner_interrupt_priority!((all(0, 1, Priority1, Level1), (1, 2,
        Priority2, Level2), (2, 3, Priority3, Level3), (3, 4, Priority4, Level4), (4, 5,
        Priority5, Level5), (5, 6, Priority6, Level6), (6, 7, Priority7, Level7), (7, 8,
        Priority8, Level8)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// // CPLL_CLK
///
/// fn enable_cpll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpllClkConfig>,
///     _new_config: CpllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // SPLL_CLK
///
/// fn enable_spll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // MPLL_CLK
///
/// fn enable_mpll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_mpll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<MpllClkConfig>,
///     _new_config: MpllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL32K_CLK
///
/// #[cfg(use_xtal32k)]
/// fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // OSC_SLOW_CLK
///
/// fn enable_osc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC32K_CLK
///
/// fn enable_rc32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F20M
///
/// fn enable_pll_f20m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F80M
///
/// fn enable_pll_f80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F120M
///
/// fn enable_pll_f120m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F160M
///
/// fn enable_pll_f160m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F240M
///
/// fn enable_pll_f240m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // SPLL_D3_CLOCK
///
/// fn enable_spll_d3_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // IOMUX_FUNCTION_CLOCK
///
/// fn configure_iomux_function_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<IomuxFunctionClockConfig>,
///     _new_config: IomuxFunctionClockConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_F25M
///
/// fn enable_pll_f25m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F50M
///
/// fn enable_pll_f50m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL_D2_CLK
///
/// fn enable_xtal_d2_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // CPU_ROOT_CLK
///
/// fn enable_cpu_root_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_root_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuRootClkConfig>,
///     _new_config: CpuRootClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn enable_cpu_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // MEM_CLK
///
/// fn enable_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_mem_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<MemClkConfig>,
///     _new_config: MemClkConfig,
/// ) {
///     todo!()
/// }
///
/// // SYS_CLK
///
/// fn enable_sys_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_sys_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SysClkConfig>,
///     _new_config: SysClkConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LP_FAST_CLK
///
/// fn enable_lp_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_lp_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LpFastClkConfig>,
///     _new_config: LpFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LP_SLOW_CLK
///
/// fn enable_lp_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_lp_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LpSlowClkConfig>,
///     _new_config: LpSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CRYPTO_CLK
///
/// fn enable_crypto_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_crypto_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CryptoClkConfig>,
///     _new_config: CryptoClkConfig,
/// ) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl SdmInstance {
///     // SDM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl TimgInstance {
///     // TIMG_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgFunctionClockConfig>,
///         _new_config: TimgFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // TIMG_WDT_CLOCK
///
///     fn enable_wdt_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_wdt_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgWdtClockConfig>,
///         _new_config: TimgWdtClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl SpiInstance {
///     // SPI_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<SpiFunctionClockConfig>,
///         _new_config: SpiFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2cInstance {
///     // I2C_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2cFunctionClockConfig>,
///         _new_config: I2cFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2sInstance {
///     // I2S_TX_CLK
///
///     fn enable_tx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_tx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_RX_CLK
///
///     fn enable_rx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_rx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_MCLK_OUT
///
///     fn enable_mclk_out_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_mclk_out_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sMclkOutConfig>,
///         _new_config: I2sMclkOutConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl MipiDsiInstance {
///     // MIPI_DSI_DPI_CLK
///
///     fn enable_dpi_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_dpi_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<MipiDsiDpiClkConfig>,
///         _new_config: MipiDsiDpiClkConfig,
///     ) {
///         todo!()
///     }
///
///     // MIPI_DSI_PHY_PLL_REFCLK
///
///     fn enable_phy_pll_refclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_phy_pll_refclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<MipiDsiPhyPllRefclkConfig>,
///         _new_config: MipiDsiPhyPllRefclkConfig,
///     ) {
///         todo!()
///     }
///
///     // MIPI_DSI_PHY_CFG_CLK
///
///     fn enable_phy_cfg_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_phy_cfg_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<MipiDsiPhyCfgClkConfig>,
///         _new_config: MipiDsiPhyCfgClkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl RmtInstance {
///     // RMT_SCLK
///
///     fn enable_sclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_sclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<RmtSclkConfig>,
///         _new_config: RmtSclkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl PsramInstance {
///     // PSRAM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<PsramFunctionClockConfig>,
///         _new_config: PsramFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SdmInstance {
            GpioSd = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgInstance {
            Timg0 = 0,
            Timg1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
            Uart2 = 2,
            Uart3 = 3,
            Uart4 = 4,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiInstance {
            Spi2 = 0,
            Spi3 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cInstance {
            I2c0 = 0,
            I2c1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sInstance {
            I2s0 = 0,
            I2s1 = 1,
            I2s2 = 2,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MipiDsiInstance {
            MipiDsi = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtInstance {
            Rmt = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum PsramInstance {
            Psram = 0,
        }
        /// Selects the output frequency of `CPLL_CLK`. Depends on `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpllClkConfig {
            /// 360 MHz
            _360,
            /// 400 MHz
            _400,
        }
        impl CpllClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    CpllClkConfig::_360 => 360000000,
                    CpllClkConfig::_400 => 400000000,
                }
            }
        }
        /// Selects the output frequency of `MPLL_CLK`. Depends on `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MpllClkConfig {
            /// 320 MHz
            _320,
            /// 400 MHz
            _400,
            /// 500 MHz
            _500,
        }
        impl MpllClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    MpllClkConfig::_320 => 320000000,
                    MpllClkConfig::_400 => 400000000,
                    MpllClkConfig::_500 => 500000000,
                }
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum IomuxFunctionClockSource {
            /// Selects `XTAL_CLK`.
            XtalClk,
            #[default]
            /// Selects `PLL_F80M`.
            PllF80m,
        }
        /// Configures the `IOMUX_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = source / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct IomuxFunctionClockConfig {
            source: IomuxFunctionClockSource,
            div_num: u32,
        }
        impl IomuxFunctionClockConfig {
            /// Creates a new configuration for the IOMUX_FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(source: IomuxFunctionClockSource, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`IOMUX_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { source, div_num }
            }
            pub fn source(self) -> IomuxFunctionClockSource {
                self.source
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// The list of clock signals that the `CPU_ROOT_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuRootClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `CPLL_CLK`.
            Cpll,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `CPU_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = CPU_ROOT_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct CpuClkConfig {
            divisor: u32,
        }
        impl CpuClkConfig {
            /// Creates a new configuration for the CPU_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`CPU_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `MEM_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = CPU_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct MemClkConfig {
            divisor: u32,
        }
        impl MemClkConfig {
            /// Creates a new configuration for the MEM_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`MEM_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `SYS_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = MEM_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct SysClkConfig {
            divisor: u32,
        }
        impl SysClkConfig {
            /// Creates a new configuration for the SYS_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`SYS_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `APB_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = SYS_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct ApbClkConfig {
            divisor: u32,
        }
        impl ApbClkConfig {
            /// Creates a new configuration for the APB_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`APB_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `LP_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LpFastClkConfig {
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `XTAL_D2_CLK`.
            XtalD2,
        }
        /// The list of clock signals that the `LP_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LpSlowClkConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `OSC_SLOW_CLK`.
            OscSlow,
        }
        /// The list of clock signals that the `CRYPTO_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CryptoClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `PLL_F240M`.
            PllF240m,
            /// Selects `PLL_F160M`.
            PllF160m,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `MPLL_CLK`.
            MpllClk,
            /// Selects `SPLL_CLK`.
            SpllClk,
            /// Selects `CPLL_CLK`.
            CpllClk,
            /// Selects `RC_FAST_CLK`.
            RcFastDivClk,
            /// Selects `LP_SLOW_CLK`.
            RcSlowClk,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32kClk,
        }
        /// The list of clock signals that the `TIMG0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `PLL_F80M`.
            PllF80m,
        }
        /// The list of clock signals that the `TIMG0_WDT_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgWdtClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `PLL_F80M`.
            PllF80m,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `PLL_F80M`.
            PllF80m,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
            div_num: u32,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: UartFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`UART0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 4095).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 4095,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 4095 (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            pub fn fractional(self) -> u32 {
                self.fractional as u32
            }
            pub fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// The list of clock signals that the `SPI2_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiFunctionClockConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[default]
            /// Selects `SPLL_D3_CLOCK`.
            Spll,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `I2C0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2cFunctionClockConfig {
            sclk: I2cFunctionClockSclk,
            div_num: u32,
        }
        impl I2cFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: I2cFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`I2C0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> I2cFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sClkSclk {
            /// Selects `XTAL_CLK`.
            Xtal,
            #[default]
            /// Selects `PLL_F160M`.
            PllF160m,
        }
        /// Configures the `I2S0_TX_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2sClkConfig {
            sclk: I2sClkSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl I2sClkConfig {
            /// Creates a new configuration for the TX_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (1 ..= 255).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 511).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 511).
            pub const fn new(sclk: I2sClkSclk, div_num: u32, div_a: u32, div_b: u32) -> Self {
                ::core::assert!(
                    div_num >= 1 && div_num <= 255,
                    "`I2S0_TX_CLK` div_num must be between 1 and 255 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 511,
                    "`I2S0_TX_CLK` div_a must be between 1 and 511 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 511,
                    "`I2S0_TX_CLK` div_b must be between 0 and 511 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> I2sClkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        /// The list of clock signals that the `I2S0_MCLK_OUT` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sMclkOutConfig {
            /// Selects `TX_CLK`.
            Tx,
            #[default]
            /// Selects `RX_CLK`.
            Rx,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MipiDsiDpiClkSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `PLL_F240M`.
            PllF240m,
            /// Selects `PLL_F160M`.
            PllF160m,
        }
        /// Configures the `MIPI_DSI_DPI_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct MipiDsiDpiClkConfig {
            sclk: MipiDsiDpiClkSclk,
            div_num: u32,
        }
        impl MipiDsiDpiClkConfig {
            /// Creates a new configuration for the DPI_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: MipiDsiDpiClkSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`MIPI_DSI_DPI_CLK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> MipiDsiDpiClkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MipiDsiPhyPllRefclkSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `CPLL_CLK`.
            Cpll,
            /// Selects `SPLL_CLK`.
            Spll,
            /// Selects `MPLL_CLK`.
            Mpll,
        }
        /// Configures the `MIPI_DSI_PHY_PLL_REFCLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct MipiDsiPhyPllRefclkConfig {
            sclk: MipiDsiPhyPllRefclkSclk,
            div_num: u32,
        }
        impl MipiDsiPhyPllRefclkConfig {
            /// Creates a new configuration for the PHY_PLL_REFCLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: MipiDsiPhyPllRefclkSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`MIPI_DSI_PHY_PLL_REFCLK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> MipiDsiPhyPllRefclkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// The list of clock signals that the `MIPI_DSI_PHY_CFG_CLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MipiDsiPhyCfgClkConfig {
            #[default]
            /// Selects `PLL_F20M`.
            PllF20m,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `PLL_F25M`.
            PllF25m,
        }
        /// The list of clock signals that the `RMT_SCLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtSclkConfig {
            #[default]
            /// Selects `PLL_F80M`.
            PllF80m,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `XTAL_CLK`.
            XtalClk,
        }
        /// The list of clock signals that the `PSRAM_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum PsramFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `MPLL_CLK`.
            Mpll,
            /// Selects `SPLL_CLK`.
            Spll,
            /// Selects `CPLL_CLK`.
            Cpll,
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            cpll_clk: Option<CpllClkConfig>,
            mpll_clk: Option<MpllClkConfig>,
            iomux_function_clock: Option<IomuxFunctionClockConfig>,
            cpu_root_clk: Option<CpuRootClkConfig>,
            cpu_clk: Option<CpuClkConfig>,
            mem_clk: Option<MemClkConfig>,
            sys_clk: Option<SysClkConfig>,
            apb_clk: Option<ApbClkConfig>,
            lp_fast_clk: Option<LpFastClkConfig>,
            lp_slow_clk: Option<LpSlowClkConfig>,
            crypto_clk: Option<CryptoClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            timg_function_clock: [Option<TimgFunctionClockConfig>; 2],
            timg_wdt_clock: [Option<TimgWdtClockConfig>; 2],
            uart_function_clock: [Option<UartFunctionClockConfig>; 5],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 5],
            spi_function_clock: [Option<SpiFunctionClockConfig>; 2],
            i2c_function_clock: [Option<I2cFunctionClockConfig>; 2],
            i2s_tx_clk: [Option<I2sClkConfig>; 3],
            i2s_rx_clk: [Option<I2sClkConfig>; 3],
            i2s_mclk_out: [Option<I2sMclkOutConfig>; 3],
            mipi_dsi_dpi_clk: [Option<MipiDsiDpiClkConfig>; 1],
            mipi_dsi_phy_pll_refclk: [Option<MipiDsiPhyPllRefclkConfig>; 1],
            mipi_dsi_phy_cfg_clk: [Option<MipiDsiPhyCfgClkConfig>; 1],
            rmt_sclk: [Option<RmtSclkConfig>; 1],
            psram_function_clock: [Option<PsramFunctionClockConfig>; 1],
            cpll_clk_refcount: u32,
            spll_clk_refcount: u32,
            mpll_clk_refcount: u32,
            rc_fast_clk_refcount: u32,
            #[cfg(use_xtal32k)]
            xtal32k_clk_refcount: u32,
            rc32k_clk_refcount: u32,
            pll_f80m_refcount: u32,
            pll_f120m_refcount: u32,
            pll_f160m_refcount: u32,
            pll_f240m_refcount: u32,
            spll_d3_clock_refcount: u32,
            pll_f50m_refcount: u32,
            apb_clk_refcount: u32,
            lp_fast_clk_refcount: u32,
            crypto_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            sdm_function_clock_refcount: [u32; 1],
            timg_function_clock_refcount: [u32; 2],
            timg_wdt_clock_refcount: [u32; 2],
            uart_function_clock_refcount: [u32; 5],
            uart_baud_rate_generator_refcount: [u32; 5],
            spi_function_clock_refcount: [u32; 2],
            i2c_function_clock_refcount: [u32; 2],
            i2s_tx_clk_refcount: [u32; 3],
            i2s_rx_clk_refcount: [u32; 3],
            i2s_mclk_out_refcount: [u32; 3],
            mipi_dsi_dpi_clk_refcount: [u32; 1],
            mipi_dsi_phy_pll_refclk_refcount: [u32; 1],
            mipi_dsi_phy_cfg_clk_refcount: [u32; 1],
            rmt_sclk_refcount: [u32; 1],
            psram_function_clock_refcount: [u32; 1],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the CPLL_CLK clock tree node
            pub fn cpll_clk(&self) -> Option<CpllClkConfig> {
                self.cpll_clk
            }
            /// Returns the current configuration of the MPLL_CLK clock tree node
            pub fn mpll_clk(&self) -> Option<MpllClkConfig> {
                self.mpll_clk
            }
            /// Returns the current configuration of the IOMUX_FUNCTION_CLOCK clock tree node
            pub fn iomux_function_clock(&self) -> Option<IomuxFunctionClockConfig> {
                self.iomux_function_clock
            }
            /// Returns the current configuration of the CPU_ROOT_CLK clock tree node
            pub fn cpu_root_clk(&self) -> Option<CpuRootClkConfig> {
                self.cpu_root_clk
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the MEM_CLK clock tree node
            pub fn mem_clk(&self) -> Option<MemClkConfig> {
                self.mem_clk
            }
            /// Returns the current configuration of the SYS_CLK clock tree node
            pub fn sys_clk(&self) -> Option<SysClkConfig> {
                self.sys_clk
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the LP_FAST_CLK clock tree node
            pub fn lp_fast_clk(&self) -> Option<LpFastClkConfig> {
                self.lp_fast_clk
            }
            /// Returns the current configuration of the LP_SLOW_CLK clock tree node
            pub fn lp_slow_clk(&self) -> Option<LpSlowClkConfig> {
                self.lp_slow_clk
            }
            /// Returns the current configuration of the CRYPTO_CLK clock tree node
            pub fn crypto_clk(&self) -> Option<CryptoClkConfig> {
                self.crypto_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the TIMG0_FUNCTION_CLOCK clock tree node
            pub fn timg0_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG0_WDT_CLOCK clock tree node
            pub fn timg0_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG1_FUNCTION_CLOCK clock tree node
            pub fn timg1_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the TIMG1_WDT_CLOCK clock tree node
            pub fn timg1_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART2_FUNCTION_CLOCK clock tree node
            pub fn uart2_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart2 as usize]
            }
            /// Returns the current configuration of the UART2_BAUD_RATE_GENERATOR clock tree node
            pub fn uart2_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart2 as usize]
            }
            /// Returns the current configuration of the UART3_FUNCTION_CLOCK clock tree node
            pub fn uart3_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart3 as usize]
            }
            /// Returns the current configuration of the UART3_BAUD_RATE_GENERATOR clock tree node
            pub fn uart3_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart3 as usize]
            }
            /// Returns the current configuration of the UART4_FUNCTION_CLOCK clock tree node
            pub fn uart4_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart4 as usize]
            }
            /// Returns the current configuration of the UART4_BAUD_RATE_GENERATOR clock tree node
            pub fn uart4_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart4 as usize]
            }
            /// Returns the current configuration of the SPI2_FUNCTION_CLOCK clock tree node
            pub fn spi2_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi2 as usize]
            }
            /// Returns the current configuration of the SPI3_FUNCTION_CLOCK clock tree node
            pub fn spi3_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi3 as usize]
            }
            /// Returns the current configuration of the I2C0_FUNCTION_CLOCK clock tree node
            pub fn i2c0_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c0 as usize]
            }
            /// Returns the current configuration of the I2C1_FUNCTION_CLOCK clock tree node
            pub fn i2c1_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c1 as usize]
            }
            /// Returns the current configuration of the I2S0_TX_CLK clock tree node
            pub fn i2s0_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_RX_CLK clock tree node
            pub fn i2s0_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_MCLK_OUT clock tree node
            pub fn i2s0_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S1_TX_CLK clock tree node
            pub fn i2s1_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the I2S1_RX_CLK clock tree node
            pub fn i2s1_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the I2S1_MCLK_OUT clock tree node
            pub fn i2s1_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the I2S2_TX_CLK clock tree node
            pub fn i2s2_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s2 as usize]
            }
            /// Returns the current configuration of the I2S2_RX_CLK clock tree node
            pub fn i2s2_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s2 as usize]
            }
            /// Returns the current configuration of the I2S2_MCLK_OUT clock tree node
            pub fn i2s2_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s2 as usize]
            }
            /// Returns the current configuration of the MIPI_DSI_DPI_CLK clock tree node
            pub fn mipi_dsi_dpi_clk(&self) -> Option<MipiDsiDpiClkConfig> {
                self.mipi_dsi_dpi_clk[MipiDsiInstance::MipiDsi as usize]
            }
            /// Returns the current configuration of the MIPI_DSI_PHY_PLL_REFCLK clock tree node
            pub fn mipi_dsi_phy_pll_refclk(&self) -> Option<MipiDsiPhyPllRefclkConfig> {
                self.mipi_dsi_phy_pll_refclk[MipiDsiInstance::MipiDsi as usize]
            }
            /// Returns the current configuration of the MIPI_DSI_PHY_CFG_CLK clock tree node
            pub fn mipi_dsi_phy_cfg_clk(&self) -> Option<MipiDsiPhyCfgClkConfig> {
                self.mipi_dsi_phy_cfg_clk[MipiDsiInstance::MipiDsi as usize]
            }
            /// Returns the current configuration of the RMT_SCLK clock tree node
            pub fn rmt_sclk(&self) -> Option<RmtSclkConfig> {
                self.rmt_sclk[RmtInstance::Rmt as usize]
            }
            /// Returns the current configuration of the PSRAM_FUNCTION_CLOCK clock tree node
            pub fn psram_function_clock(&self) -> Option<PsramFunctionClockConfig> {
                self.psram_function_clock[PsramInstance::Psram as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                cpll_clk: None,
                mpll_clk: None,
                iomux_function_clock: None,
                cpu_root_clk: None,
                cpu_clk: None,
                mem_clk: None,
                sys_clk: None,
                apb_clk: None,
                lp_fast_clk: None,
                lp_slow_clk: None,
                crypto_clk: None,
                timg_calibration_clock: None,
                timg_function_clock: [None; 2],
                timg_wdt_clock: [None; 2],
                uart_function_clock: [None; 5],
                uart_baud_rate_generator: [None; 5],
                spi_function_clock: [None; 2],
                i2c_function_clock: [None; 2],
                i2s_tx_clk: [None; 3],
                i2s_rx_clk: [None; 3],
                i2s_mclk_out: [None; 3],
                mipi_dsi_dpi_clk: [None; 1],
                mipi_dsi_phy_pll_refclk: [None; 1],
                mipi_dsi_phy_cfg_clk: [None; 1],
                rmt_sclk: [None; 1],
                psram_function_clock: [None; 1],
                cpll_clk_refcount: 0,
                spll_clk_refcount: 0,
                mpll_clk_refcount: 0,
                rc_fast_clk_refcount: 0,
                #[cfg(use_xtal32k)]
                xtal32k_clk_refcount: 0,
                rc32k_clk_refcount: 0,
                pll_f80m_refcount: 0,
                pll_f120m_refcount: 0,
                pll_f160m_refcount: 0,
                pll_f240m_refcount: 0,
                spll_d3_clock_refcount: 0,
                pll_f50m_refcount: 0,
                apb_clk_refcount: 0,
                lp_fast_clk_refcount: 0,
                crypto_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                sdm_function_clock_refcount: [0; 1],
                timg_function_clock_refcount: [0; 2],
                timg_wdt_clock_refcount: [0; 2],
                uart_function_clock_refcount: [0; 5],
                uart_baud_rate_generator_refcount: [0; 5],
                spi_function_clock_refcount: [0; 2],
                i2c_function_clock_refcount: [0; 2],
                i2s_tx_clk_refcount: [0; 3],
                i2s_rx_clk_refcount: [0; 3],
                i2s_mclk_out_refcount: [0; 3],
                mipi_dsi_dpi_clk_refcount: [0; 1],
                mipi_dsi_phy_pll_refclk_refcount: [0; 1],
                mipi_dsi_phy_cfg_clk_refcount: [0; 1],
                rmt_sclk_refcount: [0; 1],
                psram_function_clock_refcount: [0; 1],
            });
        static CPLL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static MPLL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static IOMUX_FUNCTION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_ROOT_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static MEM_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYS_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static APB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LP_FAST_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LP_SLOW_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CRYPTO_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_CALIBRATION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static TIMG_WDT_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static UART_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 5] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 5];
        static UART_BAUD_RATE_GENERATOR_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 5] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 5];
        static SPI_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static I2C_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static I2S_TX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static I2S_RX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static I2S_MCLK_OUT_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static MIPI_DSI_DPI_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static MIPI_DSI_PHY_PLL_REFCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static MIPI_DSI_PHY_CFG_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static RMT_SCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static PSRAM_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        /// The clock sources of the device.
        ///
        /// A clock source is a node of the clock tree that other nodes derive their output
        /// from. Ask a node which source it runs on with its `..._root_source` function.
        #[derive(Debug, enumset::EnumSetType)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ClockSource {
            /// `XTAL_CLK`.
            XtalClk,
            /// `RC_FAST_CLK`.
            RcFastClk,
            #[cfg(use_xtal32k)]
            /// `XTAL32K_CLK`.
            Xtal32kClk,
            /// `OSC_SLOW_CLK`.
            OscSlowClk,
            /// `RC_SLOW_CLK`.
            RcSlowClk,
            /// `RC32K_CLK`.
            Rc32kClk,
        }
        /// Returns the clock source that `XTAL_CLK` currently runs on.
        pub fn xtal_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::XtalClk)
        }
        /// Returns the clock source that `CPLL_CLK` currently runs on.
        pub fn cpll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `SPLL_CLK` currently runs on.
        pub fn spll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `MPLL_CLK` currently runs on.
        pub fn mpll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK` currently runs on.
        pub fn rc_fast_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcFastClk)
        }
        #[cfg(use_xtal32k)]
        /// Returns the clock source that `XTAL32K_CLK` currently runs on.
        pub fn xtal32k_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::Xtal32kClk)
        }
        /// Returns the clock source that `OSC_SLOW_CLK` currently runs on.
        pub fn osc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::OscSlowClk)
        }
        /// Returns the clock source that `RC_SLOW_CLK` currently runs on.
        pub fn rc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcSlowClk)
        }
        /// Returns the clock source that `RC32K_CLK` currently runs on.
        pub fn rc32k_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::Rc32kClk)
        }
        /// Returns the clock source that `PLL_F20M` currently runs on.
        pub fn pll_f20m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F80M` currently runs on.
        pub fn pll_f80m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F120M` currently runs on.
        pub fn pll_f120m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F160M` currently runs on.
        pub fn pll_f160m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F240M` currently runs on.
        pub fn pll_f240m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `SPLL_D3_CLOCK` currently runs on.
        pub fn spll_d3_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            spll_clk_root_source(clocks)
        }
        /// Returns the clock source that `IOMUX_FUNCTION_CLOCK` currently runs on.
        pub fn iomux_function_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.iomux_function_clock?;
            match config.source() {
                IomuxFunctionClockSource::XtalClk => xtal_clk_root_source(clocks),
                IomuxFunctionClockSource::PllF80m => pll_f80m_root_source(clocks),
            }
        }
        /// Returns the clock source that `PLL_F25M` currently runs on.
        pub fn pll_f25m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            mpll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F50M` currently runs on.
        pub fn pll_f50m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            mpll_clk_root_source(clocks)
        }
        /// Returns the clock source that `XTAL_D2_CLK` currently runs on.
        pub fn xtal_d2_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `CPU_ROOT_CLK` currently runs on.
        pub fn cpu_root_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.cpu_root_clk?;
            match config {
                CpuRootClkConfig::Xtal => xtal_clk_root_source(clocks),
                CpuRootClkConfig::Cpll => cpll_clk_root_source(clocks),
                CpuRootClkConfig::RcFast => rc_fast_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CPU_CLK` currently runs on.
        pub fn cpu_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_root_clk_root_source(clocks)
        }
        /// Returns the clock source that `MEM_CLK` currently runs on.
        pub fn mem_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `SYS_CLK` currently runs on.
        pub fn sys_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            mem_clk_root_source(clocks)
        }
        /// Returns the clock source that `APB_CLK` currently runs on.
        pub fn apb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            sys_clk_root_source(clocks)
        }
        /// Returns the clock source that `LP_FAST_CLK` currently runs on.
        pub fn lp_fast_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.lp_fast_clk?;
            match config {
                LpFastClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                LpFastClkConfig::XtalD2 => xtal_d2_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `LP_SLOW_CLK` currently runs on.
        pub fn lp_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.lp_slow_clk?;
            match config {
                LpSlowClkConfig::RcSlow => rc_slow_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
                LpSlowClkConfig::OscSlow => osc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CRYPTO_CLK` currently runs on.
        pub fn crypto_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.crypto_clk?;
            match config {
                CryptoClkConfig::Xtal => xtal_clk_root_source(clocks),
                CryptoClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                CryptoClkConfig::PllF240m => pll_f240m_root_source(clocks),
                CryptoClkConfig::PllF160m => pll_f160m_root_source(clocks),
            }
        }
        /// Returns the clock source that `TIMG_CALIBRATION_CLOCK` currently runs on.
        pub fn timg_calibration_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.timg_calibration_clock?;
            match config {
                TimgCalibrationClockConfig::MpllClk => mpll_clk_root_source(clocks),
                TimgCalibrationClockConfig::SpllClk => spll_clk_root_source(clocks),
                TimgCalibrationClockConfig::CpllClk => cpll_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcSlowClk => lp_slow_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_root_source(clocks),
            }
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        pub fn xtal_clk_frequency() -> u32 {
            40000000
        }
        pub fn configure_cpll_clk(clocks: &mut ClockTree, config: CpllClkConfig) {
            let old_config = clocks.cpll_clk.replace(config);
            refresh_cpll_clk_downstream(clocks);
            configure_cpll_clk_impl(clocks, old_config, config);
        }
        pub fn cpll_clk_config(clocks: &mut ClockTree) -> Option<CpllClkConfig> {
            clocks.cpll_clk
        }
        pub fn request_cpll_clk(clocks: &mut ClockTree) {
            trace!("Requesting CPLL_CLK");
            if increment_reference_count(&mut clocks.cpll_clk_refcount) {
                trace!("Enabling CPLL_CLK");
                request_xtal_clk(clocks);
                enable_cpll_clk_impl(clocks, true);
            }
        }
        pub fn release_cpll_clk(clocks: &mut ClockTree) {
            trace!("Releasing CPLL_CLK");
            if decrement_reference_count(&mut clocks.cpll_clk_refcount) {
                trace!("Disabling CPLL_CLK");
                enable_cpll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn cpll_clk_config_frequency(config: CpllClkConfig) -> u32 {
            config.value()
        }
        pub fn cpll_clk_frequency() -> u32 {
            CPLL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_spll_clk(clocks: &mut ClockTree) {
            trace!("Requesting SPLL_CLK");
            if increment_reference_count(&mut clocks.spll_clk_refcount) {
                trace!("Enabling SPLL_CLK");
                request_xtal_clk(clocks);
                enable_spll_clk_impl(clocks, true);
            }
        }
        pub fn release_spll_clk(clocks: &mut ClockTree) {
            trace!("Releasing SPLL_CLK");
            if decrement_reference_count(&mut clocks.spll_clk_refcount) {
                trace!("Disabling SPLL_CLK");
                enable_spll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn spll_clk_frequency() -> u32 {
            (480 * 1000000)
        }
        pub fn spll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_mpll_clk(clocks: &mut ClockTree, config: MpllClkConfig) {
            let old_config = clocks.mpll_clk.replace(config);
            refresh_mpll_clk_downstream(clocks);
            configure_mpll_clk_impl(clocks, old_config, config);
        }
        pub fn mpll_clk_config(clocks: &mut ClockTree) -> Option<MpllClkConfig> {
            clocks.mpll_clk
        }
        pub fn request_mpll_clk(clocks: &mut ClockTree) {
            trace!("Requesting MPLL_CLK");
            if increment_reference_count(&mut clocks.mpll_clk_refcount) {
                trace!("Enabling MPLL_CLK");
                request_xtal_clk(clocks);
                enable_mpll_clk_impl(clocks, true);
            }
        }
        pub fn release_mpll_clk(clocks: &mut ClockTree) {
            trace!("Releasing MPLL_CLK");
            if decrement_reference_count(&mut clocks.mpll_clk_refcount) {
                trace!("Disabling MPLL_CLK");
                enable_mpll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn mpll_clk_config_frequency(config: MpllClkConfig) -> u32 {
            config.value()
        }
        pub fn mpll_clk_frequency() -> u32 {
            MPLL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn mpll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        static RC_FAST_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_fast_clk_nominal_frequency());
        pub const fn rc_fast_clk_nominal_frequency() -> u32 {
            20000000
        }
        pub fn rc_fast_clk_frequency() -> u32 {
            RC_FAST_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_fast_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(10000000..=30000000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_FAST_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_FAST_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_fast_clk_nominal_frequency()
            );
            RC_FAST_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_fast_clk_downstream(clocks);
        }
        #[cfg(use_xtal32k)]
        pub fn request_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL32K_CLK");
            if increment_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Enabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, true);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn release_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL32K_CLK");
            if decrement_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Disabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, false);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn xtal32k_clk_frequency() -> u32 {
            32768
        }
        pub fn request_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling OSC_SLOW_CLK");
            enable_osc_slow_clk_impl(clocks, true);
        }
        pub fn release_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling OSC_SLOW_CLK");
            enable_osc_slow_clk_impl(clocks, false);
        }
        pub fn osc_slow_clk_frequency() -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling RC_SLOW_CLK");
            enable_rc_slow_clk_impl(clocks, true);
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling RC_SLOW_CLK");
            enable_rc_slow_clk_impl(clocks, false);
        }
        static RC_SLOW_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_slow_clk_nominal_frequency());
        pub const fn rc_slow_clk_nominal_frequency() -> u32 {
            136000
        }
        pub fn rc_slow_clk_frequency() -> u32 {
            RC_SLOW_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_slow_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(68000..=204000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_SLOW_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_SLOW_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_slow_clk_nominal_frequency()
            );
            RC_SLOW_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_slow_clk_downstream(clocks);
        }
        pub fn request_rc32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC32K_CLK");
            if increment_reference_count(&mut clocks.rc32k_clk_refcount) {
                trace!("Enabling RC32K_CLK");
                enable_rc32k_clk_impl(clocks, true);
            }
        }
        pub fn release_rc32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC32K_CLK");
            if decrement_reference_count(&mut clocks.rc32k_clk_refcount) {
                trace!("Disabling RC32K_CLK");
                enable_rc32k_clk_impl(clocks, false);
            }
        }
        pub fn rc32k_clk_frequency() -> u32 {
            32768
        }
        pub fn request_pll_f20m(clocks: &mut ClockTree) {
            trace!("Enabling PLL_F20M");
            request_spll_clk(clocks);
            enable_pll_f20m_impl(clocks, true);
        }
        pub fn release_pll_f20m(clocks: &mut ClockTree) {
            trace!("Disabling PLL_F20M");
            enable_pll_f20m_impl(clocks, false);
            release_spll_clk(clocks);
        }
        pub fn pll_f20m_frequency() -> u32 {
            (spll_clk_frequency() / 24)
        }
        pub fn pll_f20m_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn request_pll_f80m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F80M");
            if increment_reference_count(&mut clocks.pll_f80m_refcount) {
                trace!("Enabling PLL_F80M");
                request_spll_clk(clocks);
                enable_pll_f80m_impl(clocks, true);
            }
        }
        pub fn release_pll_f80m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F80M");
            if decrement_reference_count(&mut clocks.pll_f80m_refcount) {
                trace!("Disabling PLL_F80M");
                enable_pll_f80m_impl(clocks, false);
                release_spll_clk(clocks);
            }
        }
        pub fn pll_f80m_frequency() -> u32 {
            (spll_clk_frequency() / 6)
        }
        pub fn pll_f80m_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn request_pll_f120m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F120M");
            if increment_reference_count(&mut clocks.pll_f120m_refcount) {
                trace!("Enabling PLL_F120M");
                request_spll_clk(clocks);
                enable_pll_f120m_impl(clocks, true);
            }
        }
        pub fn release_pll_f120m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F120M");
            if decrement_reference_count(&mut clocks.pll_f120m_refcount) {
                trace!("Disabling PLL_F120M");
                enable_pll_f120m_impl(clocks, false);
                release_spll_clk(clocks);
            }
        }
        pub fn pll_f120m_frequency() -> u32 {
            (spll_clk_frequency() / 4)
        }
        pub fn pll_f120m_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn request_pll_f160m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F160M");
            if increment_reference_count(&mut clocks.pll_f160m_refcount) {
                trace!("Enabling PLL_F160M");
                request_spll_clk(clocks);
                enable_pll_f160m_impl(clocks, true);
            }
        }
        pub fn release_pll_f160m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F160M");
            if decrement_reference_count(&mut clocks.pll_f160m_refcount) {
                trace!("Disabling PLL_F160M");
                enable_pll_f160m_impl(clocks, false);
                release_spll_clk(clocks);
            }
        }
        pub fn pll_f160m_frequency() -> u32 {
            (spll_clk_frequency() / 3)
        }
        pub fn pll_f160m_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn request_pll_f240m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F240M");
            if increment_reference_count(&mut clocks.pll_f240m_refcount) {
                trace!("Enabling PLL_F240M");
                request_spll_clk(clocks);
                enable_pll_f240m_impl(clocks, true);
            }
        }
        pub fn release_pll_f240m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F240M");
            if decrement_reference_count(&mut clocks.pll_f240m_refcount) {
                trace!("Disabling PLL_F240M");
                enable_pll_f240m_impl(clocks, false);
                release_spll_clk(clocks);
            }
        }
        pub fn pll_f240m_frequency() -> u32 {
            (spll_clk_frequency() / 2)
        }
        pub fn pll_f240m_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn request_spll_d3_clock(clocks: &mut ClockTree) {
            trace!("Requesting SPLL_D3_CLOCK");
            if increment_reference_count(&mut clocks.spll_d3_clock_refcount) {
                trace!("Enabling SPLL_D3_CLOCK");
                request_spll_clk(clocks);
                enable_spll_d3_clock_impl(clocks, true);
            }
        }
        pub fn release_spll_d3_clock(clocks: &mut ClockTree) {
            trace!("Releasing SPLL_D3_CLOCK");
            if decrement_reference_count(&mut clocks.spll_d3_clock_refcount) {
                trace!("Disabling SPLL_D3_CLOCK");
                enable_spll_d3_clock_impl(clocks, false);
                release_spll_clk(clocks);
            }
        }
        pub fn spll_d3_clock_frequency() -> u32 {
            (spll_clk_frequency() / 3)
        }
        pub fn spll_d3_clock_source_frequency() -> u32 {
            spll_clk_frequency()
        }
        pub fn configure_iomux_function_clock(
            clocks: &mut ClockTree,
            config: IomuxFunctionClockConfig,
        ) {
            let old_config = clocks.iomux_function_clock.replace(config);
            refresh_iomux_function_clock_downstream(clocks);
            match config.source {
                IomuxFunctionClockSource::XtalClk => request_xtal_clk(clocks),
                IomuxFunctionClockSource::PllF80m => request_pll_f80m(clocks),
            }
            configure_iomux_function_clock_impl(clocks, old_config, config);
            if let Some(old_config) = old_config {
                match old_config.source {
                    IomuxFunctionClockSource::XtalClk => release_xtal_clk(clocks),
                    IomuxFunctionClockSource::PllF80m => release_pll_f80m(clocks),
                }
            }
        }
        pub fn iomux_function_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<IomuxFunctionClockConfig> {
            clocks.iomux_function_clock
        }
        fn request_iomux_function_clock(_clocks: &mut ClockTree) {}
        fn release_iomux_function_clock(_clocks: &mut ClockTree) {}
        pub fn iomux_function_clock_config_frequency(config: IomuxFunctionClockConfig) -> u32 {
            (match config.source {
                IomuxFunctionClockSource::XtalClk => xtal_clk_frequency(),
                IomuxFunctionClockSource::PllF80m => pll_f80m_frequency(),
            } / (config.div_num() + 1))
        }
        pub fn iomux_function_clock_frequency() -> u32 {
            IOMUX_FUNCTION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn iomux_function_clock_source_frequency(source: IomuxFunctionClockSource) -> u32 {
            match source {
                IomuxFunctionClockSource::XtalClk => xtal_clk_frequency(),
                IomuxFunctionClockSource::PllF80m => pll_f80m_frequency(),
            }
        }
        pub fn request_pll_f25m(clocks: &mut ClockTree) {
            trace!("Enabling PLL_F25M");
            request_mpll_clk(clocks);
            enable_pll_f25m_impl(clocks, true);
        }
        pub fn release_pll_f25m(clocks: &mut ClockTree) {
            trace!("Disabling PLL_F25M");
            enable_pll_f25m_impl(clocks, false);
            release_mpll_clk(clocks);
        }
        pub fn pll_f25m_frequency() -> u32 {
            (mpll_clk_frequency() / 20)
        }
        pub fn pll_f25m_source_frequency() -> u32 {
            mpll_clk_frequency()
        }
        pub fn request_pll_f50m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F50M");
            if increment_reference_count(&mut clocks.pll_f50m_refcount) {
                trace!("Enabling PLL_F50M");
                request_mpll_clk(clocks);
                enable_pll_f50m_impl(clocks, true);
            }
        }
        pub fn release_pll_f50m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F50M");
            if decrement_reference_count(&mut clocks.pll_f50m_refcount) {
                trace!("Disabling PLL_F50M");
                enable_pll_f50m_impl(clocks, false);
                release_mpll_clk(clocks);
            }
        }
        pub fn pll_f50m_frequency() -> u32 {
            (mpll_clk_frequency() / 10)
        }
        pub fn pll_f50m_source_frequency() -> u32 {
            mpll_clk_frequency()
        }
        pub fn request_xtal_d2_clk(clocks: &mut ClockTree) {
            trace!("Enabling XTAL_D2_CLK");
            request_xtal_clk(clocks);
            enable_xtal_d2_clk_impl(clocks, true);
        }
        pub fn release_xtal_d2_clk(clocks: &mut ClockTree) {
            trace!("Disabling XTAL_D2_CLK");
            enable_xtal_d2_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_d2_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 2)
        }
        pub fn xtal_d2_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_cpu_root_clk(clocks: &mut ClockTree, new_selector: CpuRootClkConfig) {
            let old_selector = clocks.cpu_root_clk.replace(new_selector);
            refresh_cpu_root_clk_downstream(clocks);
            match new_selector {
                CpuRootClkConfig::Xtal => request_xtal_clk(clocks),
                CpuRootClkConfig::Cpll => request_cpll_clk(clocks),
                CpuRootClkConfig::RcFast => request_rc_fast_clk(clocks),
            }
            configure_cpu_root_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuRootClkConfig::Xtal => release_xtal_clk(clocks),
                    CpuRootClkConfig::Cpll => release_cpll_clk(clocks),
                    CpuRootClkConfig::RcFast => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn cpu_root_clk_config(clocks: &mut ClockTree) -> Option<CpuRootClkConfig> {
            clocks.cpu_root_clk
        }
        pub fn request_cpu_root_clk(clocks: &mut ClockTree) {
            trace!("Enabling CPU_ROOT_CLK");
            match unwrap!(clocks.cpu_root_clk) {
                CpuRootClkConfig::Xtal => request_xtal_clk(clocks),
                CpuRootClkConfig::Cpll => request_cpll_clk(clocks),
                CpuRootClkConfig::RcFast => request_rc_fast_clk(clocks),
            }
            enable_cpu_root_clk_impl(clocks, true);
        }
        pub fn release_cpu_root_clk(clocks: &mut ClockTree) {
            trace!("Disabling CPU_ROOT_CLK");
            enable_cpu_root_clk_impl(clocks, false);
            match unwrap!(clocks.cpu_root_clk) {
                CpuRootClkConfig::Xtal => release_xtal_clk(clocks),
                CpuRootClkConfig::Cpll => release_cpll_clk(clocks),
                CpuRootClkConfig::RcFast => release_rc_fast_clk(clocks),
            }
        }
        pub fn cpu_root_clk_config_frequency(config: CpuRootClkConfig) -> u32 {
            match config {
                CpuRootClkConfig::Xtal => xtal_clk_frequency(),
                CpuRootClkConfig::Cpll => cpll_clk_frequency(),
                CpuRootClkConfig::RcFast => rc_fast_clk_frequency(),
            }
        }
        pub fn cpu_root_clk_frequency() -> u32 {
            CPU_ROOT_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_root_clk_source_frequency(source: CpuRootClkConfig) -> u32 {
            cpu_root_clk_config_frequency(source)
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, config: CpuClkConfig) {
            let old_config = clocks.cpu_clk.replace(config);
            refresh_cpu_clk_downstream(clocks);
            configure_cpu_clk_impl(clocks, old_config, config);
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        pub fn request_cpu_clk(clocks: &mut ClockTree) {
            trace!("Enabling CPU_CLK");
            request_cpu_root_clk(clocks);
            enable_cpu_clk_impl(clocks, true);
        }
        pub fn release_cpu_clk(clocks: &mut ClockTree) {
            trace!("Disabling CPU_CLK");
            enable_cpu_clk_impl(clocks, false);
            release_cpu_root_clk(clocks);
        }
        pub fn cpu_clk_config_frequency(config: CpuClkConfig) -> u32 {
            (cpu_root_clk_frequency() / (config.divisor() + 1))
        }
        pub fn cpu_clk_frequency() -> u32 {
            CPU_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_clk_source_frequency() -> u32 {
            cpu_root_clk_frequency()
        }
        pub fn configure_mem_clk(clocks: &mut ClockTree, config: MemClkConfig) {
            let old_config = clocks.mem_clk.replace(config);
            refresh_mem_clk_downstream(clocks);
            configure_mem_clk_impl(clocks, old_config, config);
        }
        pub fn mem_clk_config(clocks: &mut ClockTree) -> Option<MemClkConfig> {
            clocks.mem_clk
        }
        pub fn request_mem_clk(clocks: &mut ClockTree) {
            trace!("Enabling MEM_CLK");
            request_cpu_clk(clocks);
            enable_mem_clk_impl(clocks, true);
        }
        pub fn release_mem_clk(clocks: &mut ClockTree) {
            trace!("Disabling MEM_CLK");
            enable_mem_clk_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn mem_clk_config_frequency(config: MemClkConfig) -> u32 {
            (cpu_clk_frequency() / (config.divisor() + 1))
        }
        pub fn mem_clk_frequency() -> u32 {
            MEM_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn mem_clk_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn configure_sys_clk(clocks: &mut ClockTree, config: SysClkConfig) {
            let old_config = clocks.sys_clk.replace(config);
            refresh_sys_clk_downstream(clocks);
            configure_sys_clk_impl(clocks, old_config, config);
        }
        pub fn sys_clk_config(clocks: &mut ClockTree) -> Option<SysClkConfig> {
            clocks.sys_clk
        }
        pub fn request_sys_clk(clocks: &mut ClockTree) {
            trace!("Enabling SYS_CLK");
            request_mem_clk(clocks);
            enable_sys_clk_impl(clocks, true);
        }
        pub fn release_sys_clk(clocks: &mut ClockTree) {
            trace!("Disabling SYS_CLK");
            enable_sys_clk_impl(clocks, false);
            release_mem_clk(clocks);
        }
        pub fn sys_clk_config_frequency(config: SysClkConfig) -> u32 {
            (mem_clk_frequency() / (config.divisor() + 1))
        }
        pub fn sys_clk_frequency() -> u32 {
            SYS_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn sys_clk_source_frequency() -> u32 {
            mem_clk_frequency()
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, config: ApbClkConfig) {
            let old_config = clocks.apb_clk.replace(config);
            refresh_apb_clk_downstream(clocks);
            configure_apb_clk_impl(clocks, old_config, config);
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Requesting APB_CLK");
            if increment_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Enabling APB_CLK");
                request_sys_clk(clocks);
                enable_apb_clk_impl(clocks, true);
            }
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Releasing APB_CLK");
            if decrement_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Disabling APB_CLK");
                enable_apb_clk_impl(clocks, false);
                release_sys_clk(clocks);
            }
        }
        pub fn apb_clk_config_frequency(config: ApbClkConfig) -> u32 {
            (sys_clk_frequency() / (config.divisor() + 1))
        }
        pub fn apb_clk_frequency() -> u32 {
            APB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apb_clk_source_frequency() -> u32 {
            sys_clk_frequency()
        }
        pub fn configure_lp_fast_clk(clocks: &mut ClockTree, new_selector: LpFastClkConfig) {
            let old_selector = clocks.lp_fast_clk.replace(new_selector);
            refresh_lp_fast_clk_downstream(clocks);
            let active = clocks.lp_fast_clk_refcount > 0;
            if active {
                match new_selector {
                    LpFastClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => request_xtal_d2_clk(clocks),
                }
            }
            configure_lp_fast_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    LpFastClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => release_xtal_d2_clk(clocks),
                }
            }
        }
        pub fn lp_fast_clk_config(clocks: &mut ClockTree) -> Option<LpFastClkConfig> {
            clocks.lp_fast_clk
        }
        pub fn request_lp_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting LP_FAST_CLK");
            if increment_reference_count(&mut clocks.lp_fast_clk_refcount) {
                trace!("Enabling LP_FAST_CLK");
                match unwrap!(clocks.lp_fast_clk) {
                    LpFastClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => request_xtal_d2_clk(clocks),
                }
                enable_lp_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_lp_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing LP_FAST_CLK");
            if decrement_reference_count(&mut clocks.lp_fast_clk_refcount) {
                trace!("Disabling LP_FAST_CLK");
                enable_lp_fast_clk_impl(clocks, false);
                match unwrap!(clocks.lp_fast_clk) {
                    LpFastClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => release_xtal_d2_clk(clocks),
                }
            }
        }
        pub fn lp_fast_clk_config_frequency(config: LpFastClkConfig) -> u32 {
            match config {
                LpFastClkConfig::RcFast => rc_fast_clk_frequency(),
                LpFastClkConfig::XtalD2 => xtal_d2_clk_frequency(),
            }
        }
        pub fn lp_fast_clk_frequency() -> u32 {
            LP_FAST_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn lp_fast_clk_source_frequency(source: LpFastClkConfig) -> u32 {
            lp_fast_clk_config_frequency(source)
        }
        pub fn configure_lp_slow_clk(clocks: &mut ClockTree, new_selector: LpSlowClkConfig) {
            let old_selector = clocks.lp_slow_clk.replace(new_selector);
            refresh_lp_slow_clk_downstream(clocks);
            match new_selector {
                LpSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                LpSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
            }
            configure_lp_slow_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    LpSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LpSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LpSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
                }
            }
        }
        pub fn lp_slow_clk_config(clocks: &mut ClockTree) -> Option<LpSlowClkConfig> {
            clocks.lp_slow_clk
        }
        pub fn request_lp_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling LP_SLOW_CLK");
            match unwrap!(clocks.lp_slow_clk) {
                LpSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                LpSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
            }
            enable_lp_slow_clk_impl(clocks, true);
        }
        pub fn release_lp_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling LP_SLOW_CLK");
            enable_lp_slow_clk_impl(clocks, false);
            match unwrap!(clocks.lp_slow_clk) {
                LpSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                LpSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
            }
        }
        pub fn lp_slow_clk_config_frequency(config: LpSlowClkConfig) -> u32 {
            match config {
                LpSlowClkConfig::RcSlow => rc_slow_clk_frequency(),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => xtal32k_clk_frequency(),
                LpSlowClkConfig::OscSlow => osc_slow_clk_frequency(),
            }
        }
        pub fn lp_slow_clk_frequency() -> u32 {
            LP_SLOW_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn lp_slow_clk_source_frequency(source: LpSlowClkConfig) -> u32 {
            lp_slow_clk_config_frequency(source)
        }
        pub fn configure_crypto_clk(clocks: &mut ClockTree, new_selector: CryptoClkConfig) {
            let old_selector = clocks.crypto_clk.replace(new_selector);
            refresh_crypto_clk_downstream(clocks);
            let active = clocks.crypto_clk_refcount > 0;
            if active {
                match new_selector {
                    CryptoClkConfig::Xtal => request_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => request_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF240m => request_pll_f240m(clocks),
                    CryptoClkConfig::PllF160m => request_pll_f160m(clocks),
                }
            }
            configure_crypto_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    CryptoClkConfig::Xtal => release_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => release_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF240m => release_pll_f240m(clocks),
                    CryptoClkConfig::PllF160m => release_pll_f160m(clocks),
                }
            }
        }
        pub fn crypto_clk_config(clocks: &mut ClockTree) -> Option<CryptoClkConfig> {
            clocks.crypto_clk
        }
        pub fn request_crypto_clk(clocks: &mut ClockTree) {
            trace!("Requesting CRYPTO_CLK");
            if increment_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Enabling CRYPTO_CLK");
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Xtal => request_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => request_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF240m => request_pll_f240m(clocks),
                    CryptoClkConfig::PllF160m => request_pll_f160m(clocks),
                }
                enable_crypto_clk_impl(clocks, true);
            }
        }
        pub fn release_crypto_clk(clocks: &mut ClockTree) {
            trace!("Releasing CRYPTO_CLK");
            if decrement_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Disabling CRYPTO_CLK");
                enable_crypto_clk_impl(clocks, false);
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Xtal => release_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => release_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF240m => release_pll_f240m(clocks),
                    CryptoClkConfig::PllF160m => release_pll_f160m(clocks),
                }
            }
        }
        pub fn crypto_clk_config_frequency(config: CryptoClkConfig) -> u32 {
            match config {
                CryptoClkConfig::Xtal => xtal_clk_frequency(),
                CryptoClkConfig::RcFast => rc_fast_clk_frequency(),
                CryptoClkConfig::PllF240m => pll_f240m_frequency(),
                CryptoClkConfig::PllF160m => pll_f160m_frequency(),
            }
        }
        pub fn crypto_clk_frequency() -> u32 {
            CRYPTO_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn crypto_clk_source_frequency(source: CryptoClkConfig) -> u32 {
            crypto_clk_config_frequency(source)
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            refresh_timg_calibration_clock_downstream(clocks);
            let active = clocks.timg_calibration_clock_refcount > 0;
            if active {
                match new_selector {
                    TimgCalibrationClockConfig::MpllClk => request_mpll_clk(clocks),
                    TimgCalibrationClockConfig::SpllClk => request_spll_clk(clocks),
                    TimgCalibrationClockConfig::CpllClk => request_cpll_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => request_lp_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
            }
            configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    TimgCalibrationClockConfig::MpllClk => release_mpll_clk(clocks),
                    TimgCalibrationClockConfig::SpllClk => release_spll_clk(clocks),
                    TimgCalibrationClockConfig::CpllClk => release_cpll_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => release_lp_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::acquire();
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::MpllClk => request_mpll_clk(clocks),
                    TimgCalibrationClockConfig::SpllClk => request_spll_clk(clocks),
                    TimgCalibrationClockConfig::CpllClk => request_cpll_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => request_lp_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::release();
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::MpllClk => release_mpll_clk(clocks),
                    TimgCalibrationClockConfig::SpllClk => release_spll_clk(clocks),
                    TimgCalibrationClockConfig::CpllClk => release_cpll_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => release_lp_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config_frequency(config: TimgCalibrationClockConfig) -> u32 {
            match config {
                TimgCalibrationClockConfig::MpllClk => mpll_clk_frequency(),
                TimgCalibrationClockConfig::SpllClk => spll_clk_frequency(),
                TimgCalibrationClockConfig::CpllClk => cpll_clk_frequency(),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_clk_frequency(),
                TimgCalibrationClockConfig::RcSlowClk => lp_slow_clk_frequency(),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_frequency(),
            }
        }
        pub fn timg_calibration_clock_frequency() -> u32 {
            TIMG_CALIBRATION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn timg_calibration_clock_source_frequency(source: TimgCalibrationClockConfig) -> u32 {
            timg_calibration_clock_config_frequency(source)
        }
        impl SdmInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    request_iomux_function_clock(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    release_iomux_function_clock(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                iomux_function_clock_frequency()
            }
            pub fn function_clock_source_frequency() -> u32 {
                iomux_function_clock_frequency()
            }
        }
        impl TimgInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgFunctionClockConfig,
            ) {
                let old_selector = clocks.timg_function_clock[self as usize].replace(new_selector);
                refresh_timg_function_clock_downstream(clocks, self);
                let active = clocks.timg_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<TimgFunctionClockConfig> {
                clocks.timg_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: TimgFunctionClockConfig) -> u32 {
                match config {
                    TimgFunctionClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgFunctionClockConfig::RcFastClk => rc_fast_clk_frequency(),
                    TimgFunctionClockConfig::PllF80m => pll_f80m_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: TimgFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
            pub fn configure_wdt_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgWdtClockConfig,
            ) {
                let old_selector = clocks.timg_wdt_clock[self as usize].replace(new_selector);
                refresh_timg_wdt_clock_downstream(clocks, self);
                let active = clocks.timg_wdt_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgWdtClockConfig::PllF80m => request_pll_f80m(clocks),
                        TimgWdtClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_wdt_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgWdtClockConfig::PllF80m => release_pll_f80m(clocks),
                        TimgWdtClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn wdt_clock_config(self, clocks: &mut ClockTree) -> Option<TimgWdtClockConfig> {
                clocks.timg_wdt_clock[self as usize]
            }
            pub fn request_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::WDT_CLOCK", self);
                if increment_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::WDT_CLOCK", self);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgWdtClockConfig::PllF80m => request_pll_f80m(clocks),
                        TimgWdtClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                    }
                    self.enable_wdt_clock_impl(clocks, true);
                }
            }
            pub fn release_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::WDT_CLOCK", self);
                if decrement_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::WDT_CLOCK", self);
                    self.enable_wdt_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgWdtClockConfig::PllF80m => release_pll_f80m(clocks),
                        TimgWdtClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn wdt_clock_config_frequency(config: TimgWdtClockConfig) -> u32 {
                match config {
                    TimgWdtClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgWdtClockConfig::PllF80m => pll_f80m_frequency(),
                    TimgWdtClockConfig::RcFastClk => rc_fast_clk_frequency(),
                }
            }
            pub fn wdt_clock_frequency(self) -> u32 {
                TIMG_WDT_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn wdt_clock_source_frequency(source: TimgWdtClockConfig) -> u32 {
                Self::wdt_clock_config_frequency(source)
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                refresh_uart_function_clock_downstream(clocks, self);
                let active = clocks.uart_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => request_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => release_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => request_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => release_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: UartFunctionClockConfig) -> u32 {
                (match config.sclk {
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    UartFunctionClockSclk::PllF80m => pll_f80m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                UART_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: UartFunctionClockSclk) -> u32 {
                match sclk {
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    UartFunctionClockSclk::PllF80m => pll_f80m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                refresh_uart_baud_rate_generator_downstream(clocks, self);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            pub fn baud_rate_generator_config_frequency(
                self,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency() * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self) -> u32 {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        impl SpiInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: SpiFunctionClockConfig,
            ) {
                let old_selector = clocks.spi_function_clock[self as usize].replace(new_selector);
                refresh_spi_function_clock_downstream(clocks, self);
                let active = clocks.spi_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                        SpiFunctionClockConfig::Spll => request_spll_d3_clock(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                        SpiFunctionClockConfig::Spll => release_spll_d3_clock(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<SpiFunctionClockConfig> {
                clocks.spi_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                        SpiFunctionClockConfig::Spll => request_spll_d3_clock(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                        SpiFunctionClockConfig::Spll => release_spll_d3_clock(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: SpiFunctionClockConfig) -> u32 {
                match config {
                    SpiFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    SpiFunctionClockConfig::RcFast => rc_fast_clk_frequency(),
                    SpiFunctionClockConfig::Spll => spll_d3_clock_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: SpiFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl I2cInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: I2cFunctionClockConfig,
            ) {
                let old_config = clocks.i2c_function_clock[self as usize].replace(config);
                refresh_i2c_function_clock_downstream(clocks, self);
                let active = clocks.i2c_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<I2cFunctionClockConfig> {
                clocks.i2c_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: I2cFunctionClockConfig) -> u32 {
                (match config.sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: I2cFunctionClockSclk) -> u32 {
                match sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
        }
        impl I2sInstance {
            pub fn configure_tx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_tx_clk[self as usize].replace(config);
                refresh_i2s_tx_clk_downstream(clocks, self);
                let active = clocks.i2s_tx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                }
                self.configure_tx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_tx_clk[self as usize]
            }
            pub fn request_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::TX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                    self.enable_tx_clk_impl(clocks, true);
                }
            }
            pub fn release_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::TX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_tx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn tx_clk_frequency(self) -> u32 {
                I2S_TX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn tx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                }
            }
            pub fn configure_rx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_rx_clk[self as usize].replace(config);
                refresh_i2s_rx_clk_downstream(clocks, self);
                let active = clocks.i2s_rx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                }
                self.configure_rx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_rx_clk[self as usize]
            }
            pub fn request_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::RX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                    self.enable_rx_clk_impl(clocks, true);
                }
            }
            pub fn release_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::RX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_rx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn rx_clk_frequency(self) -> u32 {
                I2S_RX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn rx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                }
            }
            pub fn configure_mclk_out(
                self,
                clocks: &mut ClockTree,
                new_selector: I2sMclkOutConfig,
            ) {
                let old_selector = clocks.i2s_mclk_out[self as usize].replace(new_selector);
                refresh_i2s_mclk_out_downstream(clocks, self);
                let active = clocks.i2s_mclk_out_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                }
                self.configure_mclk_out_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config(self, clocks: &mut ClockTree) -> Option<I2sMclkOutConfig> {
                clocks.i2s_mclk_out[self as usize]
            }
            pub fn request_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MCLK_OUT", self);
                if increment_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Enabling {:?}::MCLK_OUT", self);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                    self.enable_mclk_out_impl(clocks, true);
                }
            }
            pub fn release_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MCLK_OUT", self);
                if decrement_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Disabling {:?}::MCLK_OUT", self);
                    self.enable_mclk_out_impl(clocks, false);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config_frequency(self, config: I2sMclkOutConfig) -> u32 {
                match config {
                    I2sMclkOutConfig::Tx => self.tx_clk_frequency(),
                    I2sMclkOutConfig::Rx => self.rx_clk_frequency(),
                }
            }
            pub fn mclk_out_frequency(self) -> u32 {
                I2S_MCLK_OUT_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        impl MipiDsiInstance {
            pub fn configure_dpi_clk(self, clocks: &mut ClockTree, config: MipiDsiDpiClkConfig) {
                let old_config = clocks.mipi_dsi_dpi_clk[self as usize].replace(config);
                refresh_mipi_dsi_dpi_clk_downstream(clocks, self);
                let active = clocks.mipi_dsi_dpi_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        MipiDsiDpiClkSclk::Xtal => request_xtal_clk(clocks),
                        MipiDsiDpiClkSclk::PllF240m => request_pll_f240m(clocks),
                        MipiDsiDpiClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                }
                self.configure_dpi_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        MipiDsiDpiClkSclk::Xtal => release_xtal_clk(clocks),
                        MipiDsiDpiClkSclk::PllF240m => release_pll_f240m(clocks),
                        MipiDsiDpiClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn dpi_clk_config(self, clocks: &mut ClockTree) -> Option<MipiDsiDpiClkConfig> {
                clocks.mipi_dsi_dpi_clk[self as usize]
            }
            pub fn request_dpi_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::DPI_CLK", self);
                if increment_reference_count(&mut clocks.mipi_dsi_dpi_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::DPI_CLK", self);
                    match unwrap!(clocks.mipi_dsi_dpi_clk[self as usize]).sclk {
                        MipiDsiDpiClkSclk::Xtal => request_xtal_clk(clocks),
                        MipiDsiDpiClkSclk::PllF240m => request_pll_f240m(clocks),
                        MipiDsiDpiClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                    self.enable_dpi_clk_impl(clocks, true);
                }
            }
            pub fn release_dpi_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::DPI_CLK", self);
                if decrement_reference_count(&mut clocks.mipi_dsi_dpi_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::DPI_CLK", self);
                    self.enable_dpi_clk_impl(clocks, false);
                    match unwrap!(clocks.mipi_dsi_dpi_clk[self as usize]).sclk {
                        MipiDsiDpiClkSclk::Xtal => release_xtal_clk(clocks),
                        MipiDsiDpiClkSclk::PllF240m => release_pll_f240m(clocks),
                        MipiDsiDpiClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn dpi_clk_config_frequency(config: MipiDsiDpiClkConfig) -> u32 {
                (match config.sclk {
                    MipiDsiDpiClkSclk::Xtal => xtal_clk_frequency(),
                    MipiDsiDpiClkSclk::PllF240m => pll_f240m_frequency(),
                    MipiDsiDpiClkSclk::PllF160m => pll_f160m_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn dpi_clk_frequency(self) -> u32 {
                MIPI_DSI_DPI_CLK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn dpi_clk_source_frequency(sclk: MipiDsiDpiClkSclk) -> u32 {
                match sclk {
                    MipiDsiDpiClkSclk::Xtal => xtal_clk_frequency(),
                    MipiDsiDpiClkSclk::PllF240m => pll_f240m_frequency(),
                    MipiDsiDpiClkSclk::PllF160m => pll_f160m_frequency(),
                }
            }
            pub fn configure_phy_pll_refclk(
                self,
                clocks: &mut ClockTree,
                config: MipiDsiPhyPllRefclkConfig,
            ) {
                let old_config = clocks.mipi_dsi_phy_pll_refclk[self as usize].replace(config);
                refresh_mipi_dsi_phy_pll_refclk_downstream(clocks, self);
                let active = clocks.mipi_dsi_phy_pll_refclk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        MipiDsiPhyPllRefclkSclk::Xtal => request_xtal_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Cpll => request_cpll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Spll => request_spll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Mpll => request_mpll_clk(clocks),
                    }
                }
                self.configure_phy_pll_refclk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        MipiDsiPhyPllRefclkSclk::Xtal => release_xtal_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Cpll => release_cpll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Spll => release_spll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Mpll => release_mpll_clk(clocks),
                    }
                }
            }
            pub fn phy_pll_refclk_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<MipiDsiPhyPllRefclkConfig> {
                clocks.mipi_dsi_phy_pll_refclk[self as usize]
            }
            pub fn request_phy_pll_refclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::PHY_PLL_REFCLK", self);
                if increment_reference_count(
                    &mut clocks.mipi_dsi_phy_pll_refclk_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::PHY_PLL_REFCLK", self);
                    match unwrap!(clocks.mipi_dsi_phy_pll_refclk[self as usize]).sclk {
                        MipiDsiPhyPllRefclkSclk::Xtal => request_xtal_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Cpll => request_cpll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Spll => request_spll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Mpll => request_mpll_clk(clocks),
                    }
                    self.enable_phy_pll_refclk_impl(clocks, true);
                }
            }
            pub fn release_phy_pll_refclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::PHY_PLL_REFCLK", self);
                if decrement_reference_count(
                    &mut clocks.mipi_dsi_phy_pll_refclk_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::PHY_PLL_REFCLK", self);
                    self.enable_phy_pll_refclk_impl(clocks, false);
                    match unwrap!(clocks.mipi_dsi_phy_pll_refclk[self as usize]).sclk {
                        MipiDsiPhyPllRefclkSclk::Xtal => release_xtal_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Cpll => release_cpll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Spll => release_spll_clk(clocks),
                        MipiDsiPhyPllRefclkSclk::Mpll => release_mpll_clk(clocks),
                    }
                }
            }
            pub fn phy_pll_refclk_config_frequency(config: MipiDsiPhyPllRefclkConfig) -> u32 {
                (match config.sclk {
                    MipiDsiPhyPllRefclkSclk::Xtal => xtal_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Cpll => cpll_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Spll => spll_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Mpll => mpll_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn phy_pll_refclk_frequency(self) -> u32 {
                MIPI_DSI_PHY_PLL_REFCLK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn phy_pll_refclk_source_frequency(sclk: MipiDsiPhyPllRefclkSclk) -> u32 {
                match sclk {
                    MipiDsiPhyPllRefclkSclk::Xtal => xtal_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Cpll => cpll_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Spll => spll_clk_frequency(),
                    MipiDsiPhyPllRefclkSclk::Mpll => mpll_clk_frequency(),
                }
            }
            pub fn configure_phy_cfg_clk(
                self,
                clocks: &mut ClockTree,
                new_selector: MipiDsiPhyCfgClkConfig,
            ) {
                let old_selector = clocks.mipi_dsi_phy_cfg_clk[self as usize].replace(new_selector);
                refresh_mipi_dsi_phy_cfg_clk_downstream(clocks, self);
                let active = clocks.mipi_dsi_phy_cfg_clk_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        MipiDsiPhyCfgClkConfig::PllF20m => request_pll_f20m(clocks),
                        MipiDsiPhyCfgClkConfig::RcFast => request_rc_fast_clk(clocks),
                        MipiDsiPhyCfgClkConfig::PllF25m => request_pll_f25m(clocks),
                    }
                }
                self.configure_phy_cfg_clk_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        MipiDsiPhyCfgClkConfig::PllF20m => release_pll_f20m(clocks),
                        MipiDsiPhyCfgClkConfig::RcFast => release_rc_fast_clk(clocks),
                        MipiDsiPhyCfgClkConfig::PllF25m => release_pll_f25m(clocks),
                    }
                }
            }
            pub fn phy_cfg_clk_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<MipiDsiPhyCfgClkConfig> {
                clocks.mipi_dsi_phy_cfg_clk[self as usize]
            }
            pub fn request_phy_cfg_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::PHY_CFG_CLK", self);
                if increment_reference_count(
                    &mut clocks.mipi_dsi_phy_cfg_clk_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::PHY_CFG_CLK", self);
                    match unwrap!(clocks.mipi_dsi_phy_cfg_clk[self as usize]) {
                        MipiDsiPhyCfgClkConfig::PllF20m => request_pll_f20m(clocks),
                        MipiDsiPhyCfgClkConfig::RcFast => request_rc_fast_clk(clocks),
                        MipiDsiPhyCfgClkConfig::PllF25m => request_pll_f25m(clocks),
                    }
                    self.enable_phy_cfg_clk_impl(clocks, true);
                }
            }
            pub fn release_phy_cfg_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::PHY_CFG_CLK", self);
                if decrement_reference_count(
                    &mut clocks.mipi_dsi_phy_cfg_clk_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::PHY_CFG_CLK", self);
                    self.enable_phy_cfg_clk_impl(clocks, false);
                    match unwrap!(clocks.mipi_dsi_phy_cfg_clk[self as usize]) {
                        MipiDsiPhyCfgClkConfig::PllF20m => release_pll_f20m(clocks),
                        MipiDsiPhyCfgClkConfig::RcFast => release_rc_fast_clk(clocks),
                        MipiDsiPhyCfgClkConfig::PllF25m => release_pll_f25m(clocks),
                    }
                }
            }
            pub fn phy_cfg_clk_config_frequency(config: MipiDsiPhyCfgClkConfig) -> u32 {
                match config {
                    MipiDsiPhyCfgClkConfig::PllF20m => pll_f20m_frequency(),
                    MipiDsiPhyCfgClkConfig::RcFast => rc_fast_clk_frequency(),
                    MipiDsiPhyCfgClkConfig::PllF25m => pll_f25m_frequency(),
                }
            }
            pub fn phy_cfg_clk_frequency(self) -> u32 {
                MIPI_DSI_PHY_CFG_CLK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn phy_cfg_clk_source_frequency(source: MipiDsiPhyCfgClkConfig) -> u32 {
                Self::phy_cfg_clk_config_frequency(source)
            }
        }
        impl RmtInstance {
            pub fn configure_sclk(self, clocks: &mut ClockTree, new_selector: RmtSclkConfig) {
                let old_selector = clocks.rmt_sclk[self as usize].replace(new_selector);
                refresh_rmt_sclk_downstream(clocks, self);
                let active = clocks.rmt_sclk_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        RmtSclkConfig::PllF80m => request_pll_f80m(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                }
                self.configure_sclk_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        RmtSclkConfig::PllF80m => release_pll_f80m(clocks),
                        RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn sclk_config(self, clocks: &mut ClockTree) -> Option<RmtSclkConfig> {
                clocks.rmt_sclk[self as usize]
            }
            pub fn request_sclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::SCLK", self);
                if increment_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Enabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::PllF80m => request_pll_f80m(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.enable_sclk_impl(clocks, true);
                }
            }
            pub fn release_sclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::SCLK", self);
                if decrement_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Disabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_sclk_impl(clocks, false);
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::PllF80m => release_pll_f80m(clocks),
                        RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn sclk_config_frequency(config: RmtSclkConfig) -> u32 {
                match config {
                    RmtSclkConfig::PllF80m => pll_f80m_frequency(),
                    RmtSclkConfig::RcFastClk => rc_fast_clk_frequency(),
                    RmtSclkConfig::XtalClk => xtal_clk_frequency(),
                }
            }
            pub fn sclk_frequency(self) -> u32 {
                RMT_SCLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn sclk_source_frequency(source: RmtSclkConfig) -> u32 {
                Self::sclk_config_frequency(source)
            }
        }
        impl PsramInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: PsramFunctionClockConfig,
            ) {
                let old_selector = clocks.psram_function_clock[self as usize].replace(new_selector);
                refresh_psram_function_clock_downstream(clocks, self);
                let active = clocks.psram_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        PsramFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        PsramFunctionClockConfig::Mpll => request_mpll_clk(clocks),
                        PsramFunctionClockConfig::Spll => request_spll_clk(clocks),
                        PsramFunctionClockConfig::Cpll => request_cpll_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        PsramFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        PsramFunctionClockConfig::Mpll => release_mpll_clk(clocks),
                        PsramFunctionClockConfig::Spll => release_spll_clk(clocks),
                        PsramFunctionClockConfig::Cpll => release_cpll_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<PsramFunctionClockConfig> {
                clocks.psram_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.psram_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.psram_function_clock[self as usize]) {
                        PsramFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        PsramFunctionClockConfig::Mpll => request_mpll_clk(clocks),
                        PsramFunctionClockConfig::Spll => request_spll_clk(clocks),
                        PsramFunctionClockConfig::Cpll => request_cpll_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.psram_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.psram_function_clock[self as usize]) {
                        PsramFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        PsramFunctionClockConfig::Mpll => release_mpll_clk(clocks),
                        PsramFunctionClockConfig::Spll => release_spll_clk(clocks),
                        PsramFunctionClockConfig::Cpll => release_cpll_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: PsramFunctionClockConfig) -> u32 {
                match config {
                    PsramFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    PsramFunctionClockConfig::Mpll => mpll_clk_frequency(),
                    PsramFunctionClockConfig::Spll => spll_clk_frequency(),
                    PsramFunctionClockConfig::Cpll => cpll_clk_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                PSRAM_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: PsramFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `CPLL_CLK` configuration.
            pub cpll_clk: Option<CpllClkConfig>,
            /// `MPLL_CLK` configuration.
            pub mpll_clk: Option<MpllClkConfig>,
            /// `IOMUX_FUNCTION_CLOCK` configuration.
            pub iomux_function_clock: Option<IomuxFunctionClockConfig>,
            /// `CPU_ROOT_CLK` configuration.
            pub cpu_root_clk: Option<CpuRootClkConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `MEM_CLK` configuration.
            pub mem_clk: Option<MemClkConfig>,
            /// `SYS_CLK` configuration.
            pub sys_clk: Option<SysClkConfig>,
            /// `APB_CLK` configuration.
            pub apb_clk: Option<ApbClkConfig>,
            /// `LP_FAST_CLK` configuration.
            pub lp_fast_clk: Option<LpFastClkConfig>,
            /// `LP_SLOW_CLK` configuration.
            pub lp_slow_clk: Option<LpSlowClkConfig>,
            /// `CRYPTO_CLK` configuration.
            pub crypto_clk: Option<CryptoClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self, clocks: &mut ClockTree) {
                if let Some(config) = self.cpll_clk {
                    configure_cpll_clk(clocks, config);
                }
                if let Some(config) = self.mpll_clk {
                    configure_mpll_clk(clocks, config);
                }
                if let Some(config) = self.iomux_function_clock {
                    configure_iomux_function_clock(clocks, config);
                }
                if let Some(config) = self.cpu_root_clk {
                    configure_cpu_root_clk(clocks, config);
                }
                if let Some(config) = self.cpu_clk {
                    configure_cpu_clk(clocks, config);
                }
                if let Some(config) = self.mem_clk {
                    configure_mem_clk(clocks, config);
                }
                if let Some(config) = self.sys_clk {
                    configure_sys_clk(clocks, config);
                }
                if let Some(config) = self.apb_clk {
                    configure_apb_clk(clocks, config);
                }
                if let Some(config) = self.lp_fast_clk {
                    configure_lp_fast_clk(clocks, config);
                }
                if let Some(config) = self.lp_slow_clk {
                    configure_lp_slow_clk(clocks, config);
                }
                if let Some(config) = self.crypto_clk {
                    configure_crypto_clk(clocks, config);
                }
                if let Some(config) = self.timg_calibration_clock {
                    configure_timg_calibration_clock(clocks, config);
                }
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
        fn refresh_cpll_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpll_clk {
                CPLL_CLK_FREQ_CACHE.store(
                    cpll_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_root_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [MipiDsiInstance::MipiDsi] {
                refresh_mipi_dsi_phy_pll_refclk_downstream(clocks, child_instance);
            }
            for child_instance in [PsramInstance::Psram] {
                refresh_psram_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_mpll_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.mpll_clk {
                MPLL_CLK_FREQ_CACHE.store(
                    mpll_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [MipiDsiInstance::MipiDsi] {
                refresh_mipi_dsi_phy_pll_refclk_downstream(clocks, child_instance);
                refresh_mipi_dsi_phy_cfg_clk_downstream(clocks, child_instance);
            }
            for child_instance in [PsramInstance::Psram] {
                refresh_psram_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_downstream(clocks: &mut ClockTree) {
            refresh_cpu_root_clk_downstream(clocks);
            refresh_lp_fast_clk_downstream(clocks);
            refresh_crypto_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [TimgInstance::Timg0, TimgInstance::Timg1] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
                refresh_timg_wdt_clock_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
                UartInstance::Uart3,
                UartInstance::Uart4,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2, SpiInstance::Spi3] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [I2cInstance::I2c0, I2cInstance::I2c1] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [MipiDsiInstance::MipiDsi] {
                refresh_mipi_dsi_phy_cfg_clk_downstream(clocks, child_instance);
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_slow_clk_downstream(clocks: &mut ClockTree) {
            refresh_lp_slow_clk_downstream(clocks);
        }
        fn refresh_iomux_function_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.iomux_function_clock {
                IOMUX_FUNCTION_CLOCK_FREQ_CACHE.store(
                    iomux_function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_cpu_root_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_root_clk {
                CPU_ROOT_CLK_FREQ_CACHE.store(
                    cpu_root_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_clk {
                CPU_CLK_FREQ_CACHE.store(
                    cpu_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_mem_clk_downstream(clocks);
        }
        fn refresh_mem_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.mem_clk {
                MEM_CLK_FREQ_CACHE.store(
                    mem_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_sys_clk_downstream(clocks);
        }
        fn refresh_sys_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.sys_clk {
                SYS_CLK_FREQ_CACHE.store(
                    sys_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apb_clk_downstream(clocks);
        }
        fn refresh_apb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apb_clk {
                APB_CLK_FREQ_CACHE.store(
                    apb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lp_fast_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.lp_fast_clk {
                LP_FAST_CLK_FREQ_CACHE.store(
                    lp_fast_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lp_slow_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.lp_slow_clk {
                LP_SLOW_CLK_FREQ_CACHE.store(
                    lp_slow_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_crypto_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.crypto_clk {
                CRYPTO_CLK_FREQ_CACHE.store(
                    crypto_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_calibration_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.timg_calibration_clock {
                TIMG_CALIBRATION_CLOCK_FREQ_CACHE.store(
                    timg_calibration_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_function_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_function_clock[instance as usize] {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_wdt_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_wdt_clock[instance as usize] {
                TIMG_WDT_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::wdt_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_uart_function_clock_downstream(clocks: &mut ClockTree, instance: UartInstance) {
            if let Some(config) = clocks.uart_function_clock[instance as usize] {
                UART_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    UartInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_uart_baud_rate_generator_downstream(clocks, instance);
        }
        fn refresh_uart_baud_rate_generator_downstream(
            clocks: &mut ClockTree,
            instance: UartInstance,
        ) {
            if let Some(config) = clocks.uart_baud_rate_generator[instance as usize] {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[instance as usize].store(
                    instance.baud_rate_generator_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_spi_function_clock_downstream(clocks: &mut ClockTree, instance: SpiInstance) {
            if let Some(config) = clocks.spi_function_clock[instance as usize] {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    SpiInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2c_function_clock_downstream(clocks: &mut ClockTree, instance: I2cInstance) {
            if let Some(config) = clocks.i2c_function_clock[instance as usize] {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    I2cInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2s_tx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_tx_clk[instance as usize] {
                I2S_TX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::tx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_rx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_rx_clk[instance as usize] {
                I2S_RX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::rx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_mclk_out_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_mclk_out[instance as usize] {
                I2S_MCLK_OUT_FREQ_CACHE[instance as usize].store(
                    instance.mclk_out_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_mipi_dsi_dpi_clk_downstream(clocks: &mut ClockTree, instance: MipiDsiInstance) {
            if let Some(config) = clocks.mipi_dsi_dpi_clk[instance as usize] {
                MIPI_DSI_DPI_CLK_FREQ_CACHE[instance as usize].store(
                    MipiDsiInstance::dpi_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_mipi_dsi_phy_pll_refclk_downstream(
            clocks: &mut ClockTree,
            instance: MipiDsiInstance,
        ) {
            if let Some(config) = clocks.mipi_dsi_phy_pll_refclk[instance as usize] {
                MIPI_DSI_PHY_PLL_REFCLK_FREQ_CACHE[instance as usize].store(
                    MipiDsiInstance::phy_pll_refclk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_mipi_dsi_phy_cfg_clk_downstream(
            clocks: &mut ClockTree,
            instance: MipiDsiInstance,
        ) {
            if let Some(config) = clocks.mipi_dsi_phy_cfg_clk[instance as usize] {
                MIPI_DSI_PHY_CFG_CLK_FREQ_CACHE[instance as usize].store(
                    MipiDsiInstance::phy_cfg_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_rmt_sclk_downstream(clocks: &mut ClockTree, instance: RmtInstance) {
            if let Some(config) = clocks.rmt_sclk[instance as usize] {
                RMT_SCLK_FREQ_CACHE[instance as usize].store(
                    RmtInstance::sclk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_psram_function_clock_downstream(
            clocks: &mut ClockTree,
            instance: PsramInstance,
        ) {
            if let Some(config) = clocks.psram_function_clock[instance as usize] {
                PSRAM_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    PsramInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AES peripheral clock signal
            Aes,
            /// AHB_GDMA peripheral clock signal
            AhbGdma,
            /// APB_SAR_ADC peripheral clock signal
            ApbSarAdc,
            /// AXI_GDMA peripheral clock signal
            AxiGdma,
            /// DS peripheral clock signal
            Ds,
            /// ECC peripheral clock signal
            Ecc,
            /// ECDSA peripheral clock signal
            Ecdsa,
            /// EMAC peripheral clock signal
            Emac,
            /// GPIO_SD peripheral clock signal
            GpioSd,
            /// HMAC peripheral clock signal
            Hmac,
            /// I2C0 peripheral clock signal
            I2c0,
            /// I2C1 peripheral clock signal
            I2c1,
            /// I2S0 peripheral clock signal
            I2s0,
            /// I2S1 peripheral clock signal
            I2s1,
            /// I2S2 peripheral clock signal
            I2s2,
            /// IOMUX peripheral clock signal
            Iomux,
            /// LCD_CAM peripheral clock signal
            LcdCam,
            /// LEDC peripheral clock signal
            Ledc,
            /// MCPWM0 peripheral clock signal
            Mcpwm0,
            /// MCPWM1 peripheral clock signal
            Mcpwm1,
            /// MIPI_DSI peripheral clock signal
            MipiDsi,
            /// PARL_IO peripheral clock signal
            ParlIo,
            /// PCNT peripheral clock signal
            Pcnt,
            /// RMT peripheral clock signal
            Rmt,
            /// RSA peripheral clock signal
            Rsa,
            /// SDIO_HOST peripheral clock signal
            SdioHost,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SPI3 peripheral clock signal
            Spi3,
            /// SYSTIMER peripheral clock signal
            Systimer,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TIMG1 peripheral clock signal
            Timg1,
            /// TWAI0 peripheral clock signal
            Twai0,
            /// TWAI1 peripheral clock signal
            Twai1,
            /// TWAI2 peripheral clock signal
            Twai2,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART2 peripheral clock signal
            Uart2,
            /// UART3 peripheral clock signal
            Uart3,
            /// UART4 peripheral clock signal
            Uart4,
            /// UHCI0 peripheral clock signal
            Uhci0,
            /// USB_DEVICE peripheral clock signal
            UsbDevice,
            /// USB_FS peripheral clock signal
            UsbFs,
            /// USB_HS peripheral clock signal
            UsbHs,
            /// VDMA peripheral clock signal
            Vdma,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] = &[
                Self::Iomux,
                Self::Systimer,
                Self::Timg0,
                Self::Uart0,
                Self::UsbDevice,
            ];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::Aes,
                Self::AhbGdma,
                Self::ApbSarAdc,
                Self::AxiGdma,
                Self::Ds,
                Self::Ecc,
                Self::Ecdsa,
                Self::Emac,
                Self::GpioSd,
                Self::Hmac,
                Self::I2c0,
                Self::I2c1,
                Self::I2s0,
                Self::I2s1,
                Self::I2s2,
                Self::Iomux,
                Self::LcdCam,
                Self::Ledc,
                Self::Mcpwm0,
                Self::Mcpwm1,
                Self::MipiDsi,
                Self::ParlIo,
                Self::Pcnt,
                Self::Rmt,
                Self::Rsa,
                Self::SdioHost,
                Self::Sha,
                Self::Spi2,
                Self::Spi3,
                Self::Systimer,
                Self::Timg0,
                Self::Timg1,
                Self::Twai0,
                Self::Twai1,
                Self::Twai2,
                Self::Uart0,
                Self::Uart1,
                Self::Uart2,
                Self::Uart3,
                Self::Uart4,
                Self::Uhci0,
                Self::UsbDevice,
                Self::UsbFs,
                Self::UsbHs,
                Self::Vdma,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::AhbGdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.ahb_pdma_sys_clk_en().bit(enable));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.adc_apb_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .peri_clk_ctrl23()
                        .modify(|_, w| w.adc_clk_en().bit(enable));
                }
                Peripheral::AxiGdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.axi_pdma_sys_clk_en().bit(enable));
                }
                Peripheral::Ds => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::Ecc => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::Ecdsa => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::Emac => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.emac_sys_clk_en().bit(enable));
                }
                Peripheral::GpioSd => {
                    crate::peripherals::GPIO_SD::regs()
                        .clock_gate()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Hmac => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::I2c0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.i2c0_apb_clk_en().bit(enable));
                }
                Peripheral::I2c1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.i2c1_apb_clk_en().bit(enable));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.i2s0_apb_clk_en().bit(enable));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.i2s1_apb_clk_en().bit(enable));
                }
                Peripheral::I2s2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.i2s2_apb_clk_en().bit(enable));
                }
                Peripheral::Iomux => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .peri_clk_ctrl26()
                        .modify(|_, w| w.iomux_clk_en().bit(enable));
                }
                Peripheral::LcdCam => {
                    let _ = enable;
                }
                Peripheral::Ledc => {
                    let _ = enable;
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.mcpwm0_apb_clk_en().bit(enable));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.mcpwm1_apb_clk_en().bit(enable));
                }
                Peripheral::MipiDsi => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.dsi_sys_clk_en().bit(enable));
                }
                Peripheral::ParlIo => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.parlio_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.parlio_apb_clk_en().bit(enable));
                }
                Peripheral::Pcnt => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.pcnt_apb_clk_en().bit(enable));
                }
                Peripheral::Rmt => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.rmt_sys_clk_en().bit(enable));
                }
                Peripheral::Rsa => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.sdmmc_sys_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.crypto_sys_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.gpspi2_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.gpspi2_apb_clk_en().bit(enable));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.gpspi3_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.gpspi3_apb_clk_en().bit(enable));
                }
                Peripheral::Systimer => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.systimer_apb_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .peri_clk_ctrl21()
                        .modify(|_, w| w.systimer_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.timergrp0_apb_clk_en().bit(enable));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.timergrp1_apb_clk_en().bit(enable));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.twai0_apb_clk_en().bit(enable));
                }
                Peripheral::Twai1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.twai1_apb_clk_en().bit(enable));
                }
                Peripheral::Twai2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.twai2_apb_clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uart0_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uart0_apb_clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uart1_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uart1_apb_clk_en().bit(enable));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uart2_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uart2_apb_clk_en().bit(enable));
                }
                Peripheral::Uart3 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uart3_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uart3_apb_clk_en().bit(enable));
                }
                Peripheral::Uart4 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uart4_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uart4_apb_clk_en().bit(enable));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.uhci_sys_clk_en().bit(enable));
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.uhci_apb_clk_en().bit(enable));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl2()
                        .modify(|_, w| w.usb_device_apb_clk_en().bit(enable));
                }
                Peripheral::UsbFs => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.usb_otg11_sys_clk_en().bit(enable));
                }
                Peripheral::UsbHs => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.usb_otg20_sys_clk_en().bit(enable));
                }
                Peripheral::Vdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .soc_clk_ctrl1()
                        .modify(|_, w| w.gdma_sys_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_aes().bit(reset));
                }
                Peripheral::AhbGdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_ahb_pdma().bit(reset));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_adc().bit(reset));
                }
                Peripheral::AxiGdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_axi_pdma().bit(reset));
                }
                Peripheral::Ds => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_ds().bit(reset));
                }
                Peripheral::Ecc => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_ecc().bit(reset));
                }
                Peripheral::Ecdsa => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_ecdsa().bit(reset));
                }
                Peripheral::Emac => {
                    let _ = reset;
                }
                Peripheral::GpioSd => {
                    let _ = reset;
                }
                Peripheral::Hmac => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_hmac().bit(reset));
                }
                Peripheral::I2c0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_i2c0().bit(reset));
                }
                Peripheral::I2c1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_i2c1().bit(reset));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_i2s0_apb().bit(reset));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_i2s1_apb().bit(reset));
                }
                Peripheral::I2s2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_i2s2_apb().bit(reset));
                }
                Peripheral::Iomux => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_iomux().bit(reset));
                }
                Peripheral::LcdCam => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_lcdcam().bit(reset));
                }
                Peripheral::Ledc => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_ledc().bit(reset));
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_pwm0().bit(reset));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_pwm1().bit(reset));
                }
                Peripheral::MipiDsi => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en0()
                        .modify(|_, w| w.rst_en_dsi_brg().bit(reset));
                }
                Peripheral::ParlIo => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| {
                            w.rst_en_parlio()
                                .bit(reset)
                                .rst_en_parlio_rx()
                                .bit(reset)
                                .rst_en_parlio_tx()
                                .bit(reset)
                        });
                }
                Peripheral::Pcnt => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_pcnt().bit(reset));
                }
                Peripheral::Rmt => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_rmt().bit(reset));
                }
                Peripheral::Rsa => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_rsa().bit(reset));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::LP_AON_CLKRST::regs()
                        .lp_aonclkrst_hp_sdmmc_emac_rst_ctrl()
                        .modify(|_, w| w.lp_aonclkrst_rst_en_sdmmc().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_sha().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_spi2().bit(reset));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en2()
                        .modify(|_, w| w.rst_en_spi3().bit(reset));
                }
                Peripheral::Systimer => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_stimer().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_timergrp0().bit(reset));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_timergrp1().bit(reset));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_can0().bit(reset));
                }
                Peripheral::Twai1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_can1().bit(reset));
                }
                Peripheral::Twai2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_can2().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| {
                            w.rst_en_uart0_core()
                                .bit(reset)
                                .rst_en_uart0_apb()
                                .bit(reset)
                        });
                }
                Peripheral::Uart1 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| {
                            w.rst_en_uart1_core()
                                .bit(reset)
                                .rst_en_uart1_apb()
                                .bit(reset)
                        });
                }
                Peripheral::Uart2 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| {
                            w.rst_en_uart2_core()
                                .bit(reset)
                                .rst_en_uart2_apb()
                                .bit(reset)
                        });
                }
                Peripheral::Uart3 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| {
                            w.rst_en_uart3_core()
                                .bit(reset)
                                .rst_en_uart3_apb()
                                .bit(reset)
                        });
                }
                Peripheral::Uart4 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| {
                            w.rst_en_uart4_core()
                                .bit(reset)
                                .rst_en_uart4_apb()
                                .bit(reset)
                        });
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en1()
                        .modify(|_, w| w.rst_en_uhci().bit(reset));
                }
                Peripheral::UsbDevice => {
                    let _ = reset;
                }
                Peripheral::UsbFs => {
                    let _ = reset;
                }
                Peripheral::UsbHs => {
                    let _ = reset;
                }
                Peripheral::Vdma => {
                    crate::peripherals::HP_SYS_CLKRST::regs()
                        .hp_rst_en0()
                        .modify(|_, w| w.rst_en_gdma().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x4FF40000..0x4FFADFC0
    };
    (size as str, "DRAM") => {
        "450496"
    };
    ("DRAM2_UNINIT") => {
        0x4FFADFC0..0x4FFBEFC0
    };
    (size as str, "DRAM2_UNINIT") => {
        "69632"
    };
    ("IROM") => {
        0x40000000..0x44000000
    };
    (size as str, "IROM") => {
        "67108864"
    };
    ("DROM") => {
        0x40000000..0x44000000
    };
    (size as str, "DROM") => {
        "67108864"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2c0, I2C0_SCL, I2C0_SDA));
        _for_each_inner_i2c_master!((1, I2C1, I2c1, I2C1_SCL, I2C1_SDA));
        _for_each_inner_i2c_master!((all(0, I2C0, I2c0, I2C0_SCL, I2C0_SDA), (1, I2C1,
        I2c1, I2C1_SCL, I2C1_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2S driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $mclk:ident, $bclk:ident, $ws:ident, $bclk_rx:ident,
/// $ws_rx:ident, [$($dout:ident),*], [$($din:ident),*], $pdm_tx:literal, $pdm_rx:literal,
/// $pcm2pdm:literal, $pdm2pcm:literal)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the I2S instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$mclk`: the MCLK output signal (a placeholder on chips without a GPIO-matrix MCLK).
/// - `$bclk`, `$ws`: TX bit clock and word select output signals.
/// - `$bclk_rx`, `$ws_rx`: RX bit clock and word select output signals.
/// - `$dout`, `$din`: data-out and data-in signal names.
/// - `$pdm_tx`, `$pdm_rx`: whether the instance supports PDM TX/RX.
/// - `$pcm2pdm`, `$pdm2pcm`: whether the instance supports the hardware PCM<->PDM format conversion
///   filter on TX/RX.
///
/// Example data:
/// - `(I2S0, I2s0, I2S_MCLK, I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true,
///   true, true, true)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2s {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2s { $(($pattern) => $code;)* ($other : tt) => {} }
        _for_each_inner_i2s!((I2S0)); _for_each_inner_i2s!((I2S1));
        _for_each_inner_i2s!((I2S2)); _for_each_inner_i2s!((I2S0, I2s0, I2S0_MCLK,
        I2S0_O_BCK, I2S0_O_WS, I2S0_I_BCK, I2S0_I_WS, [I2S0_O_SD, I2S0_O_SD1],
        [I2S0_I_SD, I2S0_I_SD1, I2S0_I_SD2, I2S0_I_SD3], true, true, true, true));
        _for_each_inner_i2s!((I2S1, I2s1, I2S1_MCLK, I2S1_O_BCK, I2S1_O_WS, I2S1_I_BCK,
        I2S1_I_WS, [I2S1_O_SD], [I2S1_I_SD], true, true, false, false));
        _for_each_inner_i2s!((I2S2, I2s2, I2S2_MCLK, I2S2_O_BCK, I2S2_O_WS, I2S2_I_BCK,
        I2S2_I_WS, [I2S2_O_SD], [I2S2_I_SD], true, true, false, false));
        _for_each_inner_i2s!((names(I2S0), (I2S1), (I2S2)));
        _for_each_inner_i2s!((all(I2S0, I2s0, I2S0_MCLK, I2S0_O_BCK, I2S0_O_WS,
        I2S0_I_BCK, I2S0_I_WS, [I2S0_O_SD, I2S0_O_SD1], [I2S0_I_SD, I2S0_I_SD1,
        I2S0_I_SD2, I2S0_I_SD3], true, true, true, true), (I2S1, I2s1, I2S1_MCLK,
        I2S1_O_BCK, I2S1_O_WS, I2S1_I_BCK, I2S1_I_WS, [I2S1_O_SD], [I2S1_I_SD], true,
        true, false, false), (I2S2, I2s2, I2S2_MCLK, I2S2_O_BCK, I2S2_O_WS, I2S2_I_BCK,
        I2S2_I_WS, [I2S2_O_SD], [I2S2_I_SD], true, true, false, false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, UART0_RXD, UART0_TXD, UART0_CTS,
        UART0_RTS, wakeup_source = true)); _for_each_inner_uart!((1, UART1, Uart1,
        UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS, wakeup_source = true));
        _for_each_inner_uart!((2, UART2, Uart2, UART2_RXD, UART2_TXD, UART2_CTS,
        UART2_RTS, wakeup_source = true)); _for_each_inner_uart!((3, UART3, Uart3,
        UART3_RXD, UART3_TXD, UART3_CTS, UART3_RTS, wakeup_source = true));
        _for_each_inner_uart!((4, UART4, Uart4, UART4_RXD, UART4_TXD, UART4_CTS,
        UART4_RTS, wakeup_source = true)); _for_each_inner_uart!((all(0, UART0, Uart0,
        UART0_RXD, UART0_TXD, UART0_CTS, UART0_RTS, wakeup_source = true), (1, UART1,
        Uart1, UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS, wakeup_source = true), (2,
        UART2, Uart2, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, wakeup_source = true),
        (3, UART3, Uart3, UART3_RXD, UART3_TXD, UART3_CTS, UART3_RTS, wakeup_source =
        true), (4, UART4, Uart4, UART4_RXD, UART4_TXD, UART4_CTS, UART4_RTS,
        wakeup_source = true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2)); _for_each_inner_spi_master!((SPI3));
        _for_each_inner_spi_master!((SPI2, Spi2, SPI2_CK[SPI2_CS] [SPI2_D, SPI2_Q,
        SPI2_WP, SPI2_HOLD], true)); _for_each_inner_spi_master!((SPI3, Spi3,
        SPI3_CK[SPI3_CS, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q, SPI3_WP, SPI3_HOLD],
        true)); _for_each_inner_spi_master!((names(SPI2), (SPI3)));
        _for_each_inner_spi_master!((all(SPI2, Spi2, SPI2_CK[SPI2_CS] [SPI2_D, SPI2_Q,
        SPI2_WP, SPI2_HOLD], true), (SPI3, Spi3, SPI3_CK[SPI3_CS, SPI3_CS1, SPI3_CS2]
        [SPI3_D, SPI3_Q, SPI3_WP, SPI3_HOLD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2)); _for_each_inner_spi_slave!((SPI3));
        _for_each_inner_spi_slave!((SPI2, Spi2, SPI2_CK, SPI2_D, SPI2_Q, SPI2_CS));
        _for_each_inner_spi_slave!((SPI3, Spi3, SPI3_CK, SPI3_D, SPI3_Q, SPI3_CS));
        _for_each_inner_spi_slave!((names(SPI2), (SPI3)));
        _for_each_inner_spi_slave!((all(SPI2, Spi2, SPI2_CK, SPI2_D, SPI2_Q, SPI2_CS),
        (SPI3, Spi3, SPI3_CK, SPI3_D, SPI3_Q, SPI3_CS)));
    };
}
/// This macro can be used to generate code for each PCNT unit.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has four options for its "Individual matcher" case:
///
/// - `names`: `($instance:ident)`
/// - `all`: `($peri:ident, $variant:ident, $sys:ident, $regs:ident, $unit:literal,
///   $interrupt:ident, $sig_ch0:ident, $sig_ch1:ident, $ctrl_ch0:ident, $ctrl_ch1:ident)`
/// - `interrupt`: `($interrupt:ident)` (repeated: one ident per unique IRQ)
/// - `regs`: `($regs:ident)` (repeated: one ident per register block)
///
/// Macro fragments:
///
/// - `$peri`: unit singleton name (`PCNT0_UNIT0`, `PCNT1_UNIT0`, …)
/// - `$variant`: `AnyPcntUnit` enum variant (`Pcnt0Unit0`, `Pcnt1Unit0`, …)
/// - `$sys`: `esp_hal::system::Peripheral` variant for clocks
/// - `$regs`: register-block singleton (`PCNT`, `PCNT1`)
/// - `$unit`: hardware unit index within that register block
/// - `$interrupt`: shared peripheral interrupt
/// - `$sig_ch0`, `$sig_ch1`, `$ctrl_ch0`, `$ctrl_ch1`: GPIO matrix input signals
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_pcnt_unit {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_pcnt_unit { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_pcnt_unit!((PCNT0_UNIT0));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT0, Pcnt0Unit0, Pcnt, PCNT, 0, PCNT,
        PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1, Pcnt0Unit1, Pcnt, PCNT, 1, PCNT,
        PCNT1_SIG_CH0, PCNT1_SIG_CH1, PCNT1_CTRL_CH0, PCNT1_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT,
        PCNT2_SIG_CH0, PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3, Pcnt0Unit3, Pcnt, PCNT, 3, PCNT,
        PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0, PCNT3_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT)); _for_each_inner_pcnt_unit!((PCNT));
        _for_each_inner_pcnt_unit!((names(PCNT0_UNIT0), (PCNT0_UNIT1), (PCNT0_UNIT2),
        (PCNT0_UNIT3))); _for_each_inner_pcnt_unit!((all(PCNT0_UNIT0, Pcnt0Unit0, Pcnt,
        PCNT, 0, PCNT, PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1),
        (PCNT0_UNIT1, Pcnt0Unit1, Pcnt, PCNT, 1, PCNT, PCNT1_SIG_CH0, PCNT1_SIG_CH1,
        PCNT1_CTRL_CH0, PCNT1_CTRL_CH1), (PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT,
        PCNT2_SIG_CH0, PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1), (PCNT0_UNIT3,
        Pcnt0Unit3, Pcnt, PCNT, 3, PCNT, PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0,
        PCNT3_CTRL_CH1))); _for_each_inner_pcnt_unit!((interrupt(PCNT)));
        _for_each_inner_pcnt_unit!((regs(PCNT)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO1 peripheral singleton"]
        GPIO1 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO6 peripheral singleton"]
        GPIO6 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO8 peripheral singleton"]
        GPIO8 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO10 peripheral singleton"]
        GPIO10 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO12 peripheral singleton"]
        GPIO12 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO13 peripheral singleton"] GPIO13 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO14 peripheral singleton"]
        GPIO14 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO16 peripheral singleton"]
        GPIO16 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO18 peripheral singleton"]
        GPIO18 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO19 peripheral singleton"] GPIO19 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO20 peripheral singleton"]
        GPIO20 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO21 peripheral singleton"] GPIO21 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO22 peripheral singleton"]
        GPIO22 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO23 peripheral singleton"] GPIO23 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO24 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO24 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO25 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO25 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO26 peripheral singleton"] GPIO26 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO27 peripheral singleton"]
        GPIO27 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO28 peripheral singleton"] GPIO28 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO29 peripheral singleton"]
        GPIO29 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO30 peripheral singleton"] GPIO30 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO31 peripheral singleton"]
        GPIO31 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO32 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO32 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO33 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO33 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO38 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO38 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO39 peripheral singleton"]
        GPIO39 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO40 peripheral singleton"] GPIO40 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO41 peripheral singleton"]
        GPIO41 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO42 peripheral singleton"] GPIO42 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO43 peripheral singleton"]
        GPIO43 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO44 peripheral singleton"] GPIO44 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO45 peripheral singleton"]
        GPIO45 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO46 peripheral singleton"] GPIO46 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO47 peripheral singleton"]
        GPIO47 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO48 peripheral singleton"] GPIO48 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO49 peripheral singleton"]
        GPIO49 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO50 peripheral singleton"] GPIO50 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO51 peripheral singleton"]
        GPIO51 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO52 peripheral singleton"] GPIO52 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO53 peripheral singleton"]
        GPIO53 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO54 peripheral singleton"] GPIO54 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual(AHB_PDMA_IN_CH0 : { bind_dma_in_interrupt,
        enable_dma_in_interrupt, disable_dma_in_interrupt }, AHB_PDMA_OUT_CH0 : {
        bind_dma_out_interrupt, enable_dma_out_interrupt, disable_dma_out_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual(AHB_PDMA_IN_CH1 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AHB_PDMA_OUT_CH1 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable))); _for_each_inner_peripheral!((@
        peri_type #[doc = "DMA_CH2 peripheral singleton"] DMA_CH2 <=
        virtual(AHB_PDMA_IN_CH2 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, AHB_PDMA_OUT_CH2 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "DMA_AXI_CH0 peripheral singleton"] DMA_AXI_CH0 <= virtual(AXI_PDMA_IN_CH0 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AXI_PDMA_OUT_CH0 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable))); _for_each_inner_peripheral!((@
        peri_type #[doc = "DMA_AXI_CH1 peripheral singleton"] DMA_AXI_CH1 <=
        virtual(AXI_PDMA_IN_CH1 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, AXI_PDMA_OUT_CH1 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "DMA_AXI_CH2 peripheral singleton"] DMA_AXI_CH2 <= virtual(AXI_PDMA_IN_CH2 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AXI_PDMA_OUT_CH2 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable))); _for_each_inner_peripheral!((@
        peri_type #[doc = "VDMA_CH0 peripheral singleton"] VDMA_CH0 <= virtual()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "VDMA_CH1 peripheral singleton"] VDMA_CH1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "VDMA_CH2 peripheral singleton"]
        VDMA_CH2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "VDMA_CH3 peripheral singleton"] VDMA_CH3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT0 peripheral singleton"] PCNT0_UNIT0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH0 peripheral singleton"]
        SDM_CH0 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH1 peripheral singleton"] SDM_CH1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH2 peripheral singleton"]
        SDM_CH2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH4 peripheral singleton"]
        SDM_CH4 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH5 peripheral singleton"] SDM_CH5 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH6 peripheral singleton"]
        SDM_CH6 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH7 peripheral singleton"] SDM_CH7 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EFUSE peripheral singleton"]
        EFUSE <= EFUSE() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO_SD peripheral singleton"]
        GPIO_SD <= GPIO_SD() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SYSTEM peripheral singleton"] SYSTEM <= HP_SYS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "HP_SYS peripheral singleton"]
        HP_SYS <= HP_SYS() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "HP_SYS_CLKRST peripheral singleton"] HP_SYS_CLKRST <= HP_SYS_CLKRST()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RNG peripheral singleton"] RNG <= LP_TRNG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE1 peripheral singleton"] INTERRUPT_CORE1 <= INTERRUPT_CORE1()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_I2C_ANA_MST peripheral singleton"] LP_I2C_ANA_MST <= LP_I2C_ANA_MST()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "CACHE peripheral singleton"] CACHE <= CACHE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "CLIC peripheral singleton"]
        CLIC <= CLIC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "CLINT peripheral singleton"] CLINT <= CLINT() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "CLINT_OTHER_CORE peripheral singleton"] CLINT_OTHER_CORE <= CLINT_OTHER_CORE()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "IOMUX_MSPI_PIN peripheral singleton"] IOMUX_MSPI_PIN <= IOMUX_MSPI_PIN()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_I2C0 peripheral singleton"] LP_I2C0 <= LP_I2C0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_AON peripheral singleton"]
        LP_AON <= LP_SYS() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_AON_CLKRST peripheral singleton"] LP_AON_CLKRST <= LP_AON_CLKRST()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_SYS peripheral singleton"] LP_SYS <= LP_SYS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_GPIO peripheral singleton"]
        LP_GPIO <= LP_GPIO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "LP_IO_MUX peripheral singleton"] LP_IO_MUX <= LP_IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_PERI peripheral singleton"]
        LP_PERI <= LP_PERI() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "RTC_TIMER peripheral singleton"] RTC_TIMER <= LP_TIMER() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_WDT peripheral singleton"]
        LP_WDT <= LP_WDT() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LPWR peripheral singleton"] LPWR <= LP_SYS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PMU peripheral singleton"] PMU
        <= PMU() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "PAU peripheral singleton"] PAU <= PAU() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTIMER peripheral singleton"]
        SYSTIMER <= SYSTIMER() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG1 peripheral singleton"]
        TIMG1 <= TIMG1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART0 peripheral singleton"] UART0 <= UART0(UART0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART2 peripheral singleton"] UART2 <= UART2(UART2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART3 peripheral singleton"]
        UART3 <= UART3(UART3 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART4 peripheral singleton"] UART4 <= UART4(UART4 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UHCI0 peripheral singleton"]
        UHCI0 <= UHCI0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MEMSPI2 peripheral singleton"] MEMSPI2 <= MEMSPI2() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "MEMSPI3 peripheral singleton"]
        MEMSPI3 <= MEMSPI3() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI3 peripheral singleton"]
        SPI3 <= SPI3(SPI3 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C0 peripheral singleton"] I2C0 <= I2C0(I2C0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C1 peripheral singleton"]
        I2C1 <= I2C1(I2C1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2S1 peripheral singleton"]
        I2S1 <= I2S1(I2S1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "I2S2 peripheral singleton"] I2S2 <= I2S2(I2S2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TWAI0 peripheral singleton"]
        TWAI0 <= TWAI0(TWAI0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "TWAI1 peripheral singleton"] TWAI1 <= TWAI1(TWAI1 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TWAI2 peripheral singleton"] TWAI2 <= TWAI2(TWAI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA peripheral singleton"] DMA
        <= AHB_DMA() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "AXI_GDMA peripheral singleton"] AXI_GDMA <= AXI_DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ETH peripheral singleton"] ETH
        <= virtual(ETH_MAC : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "EMAC_DMA peripheral singleton"] EMAC_DMA <= GMAC_DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EMAC_MAC peripheral singleton"]
        EMAC_MAC <= GMAC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MIPI_DSI peripheral singleton"] MIPI_DSI <= virtual(DSI_BRIDGE : {
        bind_bridge_interrupt, enable_bridge_interrupt, disable_bridge_interrupt }, DSI :
        { bind_dsi_interrupt, enable_dsi_interrupt, disable_dsi_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "VDMA peripheral singleton"] VDMA <= DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MIPI_DSI_HOST peripheral singleton"] MIPI_DSI_HOST <= MIPI_DSI_HOST()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MIPI_DSI_BRIDGE peripheral singleton"] MIPI_DSI_BRIDGE <= MIPI_DSI_BRIDGE()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SDHOST peripheral singleton"] SDHOST <= SDHOST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LEDC peripheral singleton"]
        LEDC <= LEDC(LEDC : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "MCPWM0 peripheral singleton"] MCPWM0 <= MCPWM0(PWM0 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MCPWM1 peripheral singleton"] MCPWM1 <= MCPWM1(PWM1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PCNT peripheral singleton"]
        PCNT <= PCNT(PCNT : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "APB_SARADC peripheral singleton"] APB_SARADC <= ADC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_ADC peripheral singleton"]
        LP_ADC <= LP_ADC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RMT peripheral singleton"] RMT <= RMT(RMT : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "AES peripheral singleton"] AES
        <= AES(AES : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SHA peripheral singleton"] SHA <= SHA(SHA : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RSA peripheral singleton"] RSA
        <= RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ECC peripheral singleton"] ECC <= ECC(ECC : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "USB_FS peripheral singleton"]
        USB_FS <= USB_FS(USB_FS : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "USB_HS peripheral singleton"] USB_HS <= USB_HS(USB_HS : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "USB_WRAP peripheral singleton"] USB_WRAP <= USB_WRAP() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ADC1 peripheral singleton"]
        ADC1 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ADC2 peripheral singleton"] ADC2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FLASH peripheral singleton"]
        FLASH <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "PSRAM peripheral singleton"] PSRAM <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "CPU_CTRL peripheral singleton"]
        CPU_CTRL <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "IPC peripheral singleton"] IPC <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((GPIO0)); _for_each_inner_peripheral!((GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14)); _for_each_inner_peripheral!((GPIO15));
        _for_each_inner_peripheral!((GPIO16)); _for_each_inner_peripheral!((GPIO17));
        _for_each_inner_peripheral!((GPIO18)); _for_each_inner_peripheral!((GPIO19));
        _for_each_inner_peripheral!((GPIO20)); _for_each_inner_peripheral!((GPIO21));
        _for_each_inner_peripheral!((GPIO22)); _for_each_inner_peripheral!((GPIO23));
        _for_each_inner_peripheral!((GPIO24)); _for_each_inner_peripheral!((GPIO25));
        _for_each_inner_peripheral!((GPIO26)); _for_each_inner_peripheral!((GPIO27));
        _for_each_inner_peripheral!((GPIO28)); _for_each_inner_peripheral!((GPIO29));
        _for_each_inner_peripheral!((GPIO30)); _for_each_inner_peripheral!((GPIO31));
        _for_each_inner_peripheral!((GPIO32)); _for_each_inner_peripheral!((GPIO33));
        _for_each_inner_peripheral!((GPIO34)); _for_each_inner_peripheral!((GPIO35));
        _for_each_inner_peripheral!((GPIO36)); _for_each_inner_peripheral!((GPIO37));
        _for_each_inner_peripheral!((GPIO38)); _for_each_inner_peripheral!((GPIO39));
        _for_each_inner_peripheral!((GPIO40)); _for_each_inner_peripheral!((GPIO41));
        _for_each_inner_peripheral!((GPIO42)); _for_each_inner_peripheral!((GPIO43));
        _for_each_inner_peripheral!((GPIO44)); _for_each_inner_peripheral!((GPIO45));
        _for_each_inner_peripheral!((GPIO46)); _for_each_inner_peripheral!((GPIO47));
        _for_each_inner_peripheral!((GPIO48)); _for_each_inner_peripheral!((GPIO49));
        _for_each_inner_peripheral!((GPIO50)); _for_each_inner_peripheral!((GPIO51));
        _for_each_inner_peripheral!((GPIO52)); _for_each_inner_peripheral!((GPIO53));
        _for_each_inner_peripheral!((GPIO54));
        _for_each_inner_peripheral!((DMA_CH0(unstable)));
        _for_each_inner_peripheral!((DMA_CH1(unstable)));
        _for_each_inner_peripheral!((DMA_CH2(unstable)));
        _for_each_inner_peripheral!((DMA_AXI_CH0(unstable)));
        _for_each_inner_peripheral!((DMA_AXI_CH1(unstable)));
        _for_each_inner_peripheral!((DMA_AXI_CH2(unstable)));
        _for_each_inner_peripheral!((VDMA_CH0(unstable)));
        _for_each_inner_peripheral!((VDMA_CH1(unstable)));
        _for_each_inner_peripheral!((VDMA_CH2(unstable)));
        _for_each_inner_peripheral!((VDMA_CH3(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT0(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT1(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT2(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT3(unstable)));
        _for_each_inner_peripheral!((SDM_CH0(unstable)));
        _for_each_inner_peripheral!((SDM_CH1(unstable)));
        _for_each_inner_peripheral!((SDM_CH2(unstable)));
        _for_each_inner_peripheral!((SDM_CH3(unstable)));
        _for_each_inner_peripheral!((SDM_CH4(unstable)));
        _for_each_inner_peripheral!((SDM_CH5(unstable)));
        _for_each_inner_peripheral!((SDM_CH6(unstable)));
        _for_each_inner_peripheral!((SDM_CH7(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((GPIO_SD(unstable)));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((HP_SYS(unstable)));
        _for_each_inner_peripheral!((HP_SYS_CLKRST(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE1(unstable)));
        _for_each_inner_peripheral!((LP_I2C_ANA_MST(unstable)));
        _for_each_inner_peripheral!((CLIC(unstable)));
        _for_each_inner_peripheral!((CLINT(unstable)));
        _for_each_inner_peripheral!((CLINT_OTHER_CORE(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LP_I2C0(unstable)));
        _for_each_inner_peripheral!((LP_AON(unstable)));
        _for_each_inner_peripheral!((LP_AON_CLKRST(unstable)));
        _for_each_inner_peripheral!((LP_SYS(unstable)));
        _for_each_inner_peripheral!((LP_GPIO(unstable)));
        _for_each_inner_peripheral!((LP_IO_MUX(unstable)));
        _for_each_inner_peripheral!((LP_PERI(unstable)));
        _for_each_inner_peripheral!((RTC_TIMER(unstable)));
        _for_each_inner_peripheral!((LP_WDT(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((PMU(unstable)));
        _for_each_inner_peripheral!((PAU(unstable)));
        _for_each_inner_peripheral!((SYSTIMER(unstable)));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((TIMG1(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((UART2)); _for_each_inner_peripheral!((UART3));
        _for_each_inner_peripheral!((UART4));
        _for_each_inner_peripheral!((UHCI0(unstable)));
        _for_each_inner_peripheral!((SPI2)); _for_each_inner_peripheral!((SPI3));
        _for_each_inner_peripheral!((I2C0)); _for_each_inner_peripheral!((I2C1));
        _for_each_inner_peripheral!((I2S0(unstable)));
        _for_each_inner_peripheral!((I2S1(unstable)));
        _for_each_inner_peripheral!((I2S2(unstable)));
        _for_each_inner_peripheral!((TWAI0(unstable)));
        _for_each_inner_peripheral!((TWAI1(unstable)));
        _for_each_inner_peripheral!((TWAI2(unstable)));
        _for_each_inner_peripheral!((DMA(unstable)));
        _for_each_inner_peripheral!((AXI_GDMA(unstable)));
        _for_each_inner_peripheral!((ETH(unstable)));
        _for_each_inner_peripheral!((MIPI_DSI(unstable)));
        _for_each_inner_peripheral!((USB_DEVICE(unstable)));
        _for_each_inner_peripheral!((SDHOST(unstable)));
        _for_each_inner_peripheral!((LEDC(unstable)));
        _for_each_inner_peripheral!((MCPWM0(unstable)));
        _for_each_inner_peripheral!((MCPWM1(unstable)));
        _for_each_inner_peripheral!((PCNT(unstable)));
        _for_each_inner_peripheral!((APB_SARADC(unstable)));
        _for_each_inner_peripheral!((LP_ADC(unstable)));
        _for_each_inner_peripheral!((RMT(unstable)));
        _for_each_inner_peripheral!((AES(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((RSA(unstable)));
        _for_each_inner_peripheral!((ECC(unstable)));
        _for_each_inner_peripheral!((USB_FS(unstable)));
        _for_each_inner_peripheral!((USB_HS(unstable)));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((ADC2(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((PSRAM(unstable)));
        _for_each_inner_peripheral!((GPIO_DEDICATED(unstable)));
        _for_each_inner_peripheral!((CPU_CTRL(unstable)));
        _for_each_inner_peripheral!((IPC(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR0(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR1(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable)));
        _for_each_inner_peripheral!((SPI2, Spi2, 1, AxiGdmaChannel));
        _for_each_inner_peripheral!((UHCI0, Uhci0, 2, AhbGdmaChannel));
        _for_each_inner_peripheral!((SPI3, Spi3, 2, AxiGdmaChannel));
        _for_each_inner_peripheral!((I2S0, I2s0, 3, AhbGdmaChannel));
        _for_each_inner_peripheral!((I2S1, I2s1, 4, AhbGdmaChannel));
        _for_each_inner_peripheral!((AES, Aes, 4, AxiGdmaChannel));
        _for_each_inner_peripheral!((I2S2, I2s2, 5, AhbGdmaChannel));
        _for_each_inner_peripheral!((SHA, Sha, 5, AxiGdmaChannel));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "GPIO21 peripheral singleton"] GPIO21 <= virtual()), (@ peri_type #[doc =
        "GPIO22 peripheral singleton"] GPIO22 <= virtual()), (@ peri_type #[doc =
        "GPIO23 peripheral singleton"] GPIO23 <= virtual()), (@ peri_type #[doc =
        "GPIO24 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO24 <= virtual()), (@ peri_type #[doc =
        "GPIO25 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO25 <= virtual()), (@ peri_type #[doc =
        "GPIO26 peripheral singleton"] GPIO26 <= virtual()), (@ peri_type #[doc =
        "GPIO27 peripheral singleton"] GPIO27 <= virtual()), (@ peri_type #[doc =
        "GPIO28 peripheral singleton"] GPIO28 <= virtual()), (@ peri_type #[doc =
        "GPIO29 peripheral singleton"] GPIO29 <= virtual()), (@ peri_type #[doc =
        "GPIO30 peripheral singleton"] GPIO30 <= virtual()), (@ peri_type #[doc =
        "GPIO31 peripheral singleton"] GPIO31 <= virtual()), (@ peri_type #[doc =
        "GPIO32 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO32 <= virtual()), (@ peri_type #[doc =
        "GPIO33 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO33 <= virtual()), (@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()), (@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()), (@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()), (@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()), (@ peri_type #[doc =
        "GPIO38 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO38 <= virtual()), (@ peri_type #[doc =
        "GPIO39 peripheral singleton"] GPIO39 <= virtual()), (@ peri_type #[doc =
        "GPIO40 peripheral singleton"] GPIO40 <= virtual()), (@ peri_type #[doc =
        "GPIO41 peripheral singleton"] GPIO41 <= virtual()), (@ peri_type #[doc =
        "GPIO42 peripheral singleton"] GPIO42 <= virtual()), (@ peri_type #[doc =
        "GPIO43 peripheral singleton"] GPIO43 <= virtual()), (@ peri_type #[doc =
        "GPIO44 peripheral singleton"] GPIO44 <= virtual()), (@ peri_type #[doc =
        "GPIO45 peripheral singleton"] GPIO45 <= virtual()), (@ peri_type #[doc =
        "GPIO46 peripheral singleton"] GPIO46 <= virtual()), (@ peri_type #[doc =
        "GPIO47 peripheral singleton"] GPIO47 <= virtual()), (@ peri_type #[doc =
        "GPIO48 peripheral singleton"] GPIO48 <= virtual()), (@ peri_type #[doc =
        "GPIO49 peripheral singleton"] GPIO49 <= virtual()), (@ peri_type #[doc =
        "GPIO50 peripheral singleton"] GPIO50 <= virtual()), (@ peri_type #[doc =
        "GPIO51 peripheral singleton"] GPIO51 <= virtual()), (@ peri_type #[doc =
        "GPIO52 peripheral singleton"] GPIO52 <= virtual()), (@ peri_type #[doc =
        "GPIO53 peripheral singleton"] GPIO53 <= virtual()), (@ peri_type #[doc =
        "GPIO54 peripheral singleton"] GPIO54 <= virtual()), (@ peri_type #[doc =
        "DMA_CH0 peripheral singleton"] DMA_CH0 <= virtual(AHB_PDMA_IN_CH0 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AHB_PDMA_OUT_CH0 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual(AHB_PDMA_IN_CH1 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AHB_PDMA_OUT_CH1 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH2 peripheral singleton"] DMA_CH2 <= virtual(AHB_PDMA_IN_CH2 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AHB_PDMA_OUT_CH2 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_AXI_CH0 peripheral singleton"] DMA_AXI_CH0 <= virtual(AXI_PDMA_IN_CH0 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AXI_PDMA_OUT_CH0 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_AXI_CH1 peripheral singleton"] DMA_AXI_CH1 <= virtual(AXI_PDMA_IN_CH1 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AXI_PDMA_OUT_CH1 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_AXI_CH2 peripheral singleton"] DMA_AXI_CH2 <= virtual(AXI_PDMA_IN_CH2 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        AXI_PDMA_OUT_CH2 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "VDMA_CH0 peripheral singleton"] VDMA_CH0 <= virtual() (unstable)), (@ peri_type
        #[doc = "VDMA_CH1 peripheral singleton"] VDMA_CH1 <= virtual() (unstable)), (@
        peri_type #[doc = "VDMA_CH2 peripheral singleton"] VDMA_CH2 <= virtual()
        (unstable)), (@ peri_type #[doc = "VDMA_CH3 peripheral singleton"] VDMA_CH3 <=
        virtual() (unstable)), (@ peri_type #[doc = "PCNT0_UNIT0 peripheral singleton"]
        PCNT0_UNIT0 <= virtual() (unstable)), (@ peri_type #[doc =
        "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1 <= virtual() (unstable)), (@
        peri_type #[doc = "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2 <= virtual()
        (unstable)), (@ peri_type #[doc = "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3
        <= virtual() (unstable)), (@ peri_type #[doc = "SDM_CH0 peripheral singleton"]
        SDM_CH0 <= virtual() (unstable)), (@ peri_type #[doc =
        "SDM_CH1 peripheral singleton"] SDM_CH1 <= virtual() (unstable)), (@ peri_type
        #[doc = "SDM_CH2 peripheral singleton"] SDM_CH2 <= virtual() (unstable)), (@
        peri_type #[doc = "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual()
        (unstable)), (@ peri_type #[doc = "SDM_CH4 peripheral singleton"] SDM_CH4 <=
        virtual() (unstable)), (@ peri_type #[doc = "SDM_CH5 peripheral singleton"]
        SDM_CH5 <= virtual() (unstable)), (@ peri_type #[doc =
        "SDM_CH6 peripheral singleton"] SDM_CH6 <= virtual() (unstable)), (@ peri_type
        #[doc = "SDM_CH7 peripheral singleton"] SDM_CH7 <= virtual() (unstable)), (@
        peri_type #[doc = "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)), (@
        peri_type #[doc = "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)), (@
        peri_type #[doc = "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD()
        (unstable)), (@ peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <=
        HP_SYS() (unstable)), (@ peri_type #[doc = "HP_SYS peripheral singleton"] HP_SYS
        <= HP_SYS() (unstable)), (@ peri_type #[doc =
        "HP_SYS_CLKRST peripheral singleton"] HP_SYS_CLKRST <= HP_SYS_CLKRST()
        (unstable)), (@ peri_type #[doc = "RNG peripheral singleton"] RNG <= LP_TRNG()
        (unstable)), (@ peri_type #[doc = "INTERRUPT_CORE0 peripheral singleton"]
        INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (@ peri_type #[doc =
        "INTERRUPT_CORE1 peripheral singleton"] INTERRUPT_CORE1 <= INTERRUPT_CORE1()
        (unstable)), (@ peri_type #[doc = "LP_I2C_ANA_MST peripheral singleton"]
        LP_I2C_ANA_MST <= LP_I2C_ANA_MST() (unstable)), (@ peri_type #[doc =
        "CACHE peripheral singleton"] CACHE <= CACHE() (unstable)), (@ peri_type #[doc =
        "CLIC peripheral singleton"] CLIC <= CLIC() (unstable)), (@ peri_type #[doc =
        "CLINT peripheral singleton"] CLINT <= CLINT() (unstable)), (@ peri_type #[doc =
        "CLINT_OTHER_CORE peripheral singleton"] CLINT_OTHER_CORE <= CLINT_OTHER_CORE()
        (unstable)), (@ peri_type #[doc = "IO_MUX peripheral singleton"] IO_MUX <=
        IO_MUX() (unstable)), (@ peri_type #[doc = "IOMUX_MSPI_PIN peripheral singleton"]
        IOMUX_MSPI_PIN <= IOMUX_MSPI_PIN() (unstable)), (@ peri_type #[doc =
        "LP_I2C0 peripheral singleton"] LP_I2C0 <= LP_I2C0() (unstable)), (@ peri_type
        #[doc = "LP_AON peripheral singleton"] LP_AON <= LP_SYS() (unstable)), (@
        peri_type #[doc = "LP_AON_CLKRST peripheral singleton"] LP_AON_CLKRST <=
        LP_AON_CLKRST() (unstable)), (@ peri_type #[doc = "LP_SYS peripheral singleton"]
        LP_SYS <= LP_SYS() (unstable)), (@ peri_type #[doc =
        "LP_GPIO peripheral singleton"] LP_GPIO <= LP_GPIO() (unstable)), (@ peri_type
        #[doc = "LP_IO_MUX peripheral singleton"] LP_IO_MUX <= LP_IO_MUX() (unstable)),
        (@ peri_type #[doc = "LP_PERI peripheral singleton"] LP_PERI <= LP_PERI()
        (unstable)), (@ peri_type #[doc = "RTC_TIMER peripheral singleton"] RTC_TIMER <=
        LP_TIMER() (unstable)), (@ peri_type #[doc = "LP_WDT peripheral singleton"]
        LP_WDT <= LP_WDT() (unstable)), (@ peri_type #[doc = "LPWR peripheral singleton"]
        LPWR <= LP_SYS() (unstable)), (@ peri_type #[doc = "PMU peripheral singleton"]
        PMU <= PMU() (unstable)), (@ peri_type #[doc = "PAU peripheral singleton"] PAU <=
        PAU() (unstable)), (@ peri_type #[doc = "SYSTIMER peripheral singleton"] SYSTIMER
        <= SYSTIMER() (unstable)), (@ peri_type #[doc = "TIMG0 peripheral singleton"]
        TIMG0 <= TIMG0() (unstable)), (@ peri_type #[doc = "TIMG1 peripheral singleton"]
        TIMG1 <= TIMG1() (unstable)), (@ peri_type #[doc = "UART0 peripheral singleton"]
        UART0 <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART3 peripheral singleton"]
        UART3 <= UART3(UART3 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART4 peripheral singleton"]
        UART4 <= UART4(UART4 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UHCI0 peripheral singleton"]
        UHCI0 <= UHCI0() (unstable)), (@ peri_type #[doc = "SPI0 peripheral singleton"]
        SPI0 <= SPI0() (unstable)), (@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable)), (@ peri_type #[doc = "MEMSPI2 peripheral singleton"]
        MEMSPI2 <= MEMSPI2() (unstable)), (@ peri_type #[doc =
        "MEMSPI3 peripheral singleton"] MEMSPI3 <= MEMSPI3() (unstable)), (@ peri_type
        #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })), (@ peri_type #[doc =
        "SPI3 peripheral singleton"] SPI3 <= SPI3(SPI3 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })), (@ peri_type #[doc =
        "I2C0 peripheral singleton"] I2C0 <= I2C0(I2C0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })), (@ peri_type #[doc =
        "I2C1 peripheral singleton"] I2C1 <= I2C1(I2C1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })), (@ peri_type #[doc =
        "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "I2S1 peripheral singleton"] I2S1 <= I2S1(I2S1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "I2S2 peripheral singleton"] I2S2 <= I2S2(I2S2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "TWAI0 peripheral singleton"] TWAI0 <= TWAI0(TWAI0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "TWAI1 peripheral singleton"] TWAI1 <= TWAI1(TWAI1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "TWAI2 peripheral singleton"] TWAI2 <= TWAI2(TWAI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "DMA peripheral singleton"] DMA <= AHB_DMA() (unstable)), (@ peri_type #[doc =
        "AXI_GDMA peripheral singleton"] AXI_GDMA <= AXI_DMA() (unstable)), (@ peri_type
        #[doc = "ETH peripheral singleton"] ETH <= virtual(ETH_MAC : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "EMAC_DMA peripheral singleton"] EMAC_DMA <=
        GMAC_DMA() (unstable)), (@ peri_type #[doc = "EMAC_MAC peripheral singleton"]
        EMAC_MAC <= GMAC() (unstable)), (@ peri_type #[doc =
        "MIPI_DSI peripheral singleton"] MIPI_DSI <= virtual(DSI_BRIDGE : {
        bind_bridge_interrupt, enable_bridge_interrupt, disable_bridge_interrupt }, DSI :
        { bind_dsi_interrupt, enable_dsi_interrupt, disable_dsi_interrupt }) (unstable)),
        (@ peri_type #[doc = "VDMA peripheral singleton"] VDMA <= DMA() (unstable)), (@
        peri_type #[doc = "MIPI_DSI_HOST peripheral singleton"] MIPI_DSI_HOST <=
        MIPI_DSI_HOST() (unstable)), (@ peri_type #[doc =
        "MIPI_DSI_BRIDGE peripheral singleton"] MIPI_DSI_BRIDGE <= MIPI_DSI_BRIDGE()
        (unstable)), (@ peri_type #[doc = "USB_DEVICE peripheral singleton"] USB_DEVICE
        <= USB_DEVICE(USB_DEVICE : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "SDHOST peripheral singleton"] SDHOST <= SDHOST() (unstable)), (@ peri_type #[doc
        = "LEDC peripheral singleton"] LEDC <= LEDC(LEDC : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "MCPWM0 peripheral singleton"] MCPWM0 <= MCPWM0(PWM0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "MCPWM1 peripheral singleton"] MCPWM1 <= MCPWM1(PWM1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "PCNT peripheral singleton"] PCNT <= PCNT(PCNT : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "APB_SARADC peripheral singleton"] APB_SARADC <= ADC() (unstable)), (@
        peri_type #[doc = "LP_ADC peripheral singleton"] LP_ADC <= LP_ADC() (unstable)),
        (@ peri_type #[doc = "RMT peripheral singleton"] RMT <= RMT(RMT : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "AES peripheral singleton"] AES <= AES(AES : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "SHA peripheral singleton"] SHA <= SHA(SHA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "RSA peripheral singleton"] RSA <= RSA(RSA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "ECC peripheral singleton"] ECC <= ECC(ECC : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "USB_FS peripheral singleton"] USB_FS <=
        USB_FS(USB_FS : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "USB_HS peripheral singleton"] USB_HS <= USB_HS(USB_HS : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "USB_WRAP peripheral singleton"] USB_WRAP <= USB_WRAP() (unstable)), (@
        peri_type #[doc = "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)), (@
        peri_type #[doc = "ADC2 peripheral singleton"] ADC2 <= virtual() (unstable)), (@
        peri_type #[doc = "FLASH peripheral singleton"] FLASH <= virtual() (unstable)),
        (@ peri_type #[doc = "PSRAM peripheral singleton"] PSRAM <= virtual()
        (unstable)), (@ peri_type #[doc = "GPIO_DEDICATED peripheral singleton"]
        GPIO_DEDICATED <= virtual() (unstable)), (@ peri_type #[doc =
        "CPU_CTRL peripheral singleton"] CPU_CTRL <= virtual() (unstable)), (@ peri_type
        #[doc = "IPC peripheral singleton"] IPC <= virtual() (unstable)), (@ peri_type
        #[doc = "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual()
        (unstable)), (@ peri_type #[doc = "FROM_CPU_INTR1 peripheral singleton"]
        FROM_CPU_INTR1 <= virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <=
        virtual() (unstable)))); _for_each_inner_peripheral!((singletons(GPIO0), (GPIO1),
        (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6), (GPIO7), (GPIO8), (GPIO9), (GPIO10),
        (GPIO11), (GPIO12), (GPIO13), (GPIO14), (GPIO15), (GPIO16), (GPIO17), (GPIO18),
        (GPIO19), (GPIO20), (GPIO21), (GPIO22), (GPIO23), (GPIO24), (GPIO25), (GPIO26),
        (GPIO27), (GPIO28), (GPIO29), (GPIO30), (GPIO31), (GPIO32), (GPIO33), (GPIO34),
        (GPIO35), (GPIO36), (GPIO37), (GPIO38), (GPIO39), (GPIO40), (GPIO41), (GPIO42),
        (GPIO43), (GPIO44), (GPIO45), (GPIO46), (GPIO47), (GPIO48), (GPIO49), (GPIO50),
        (GPIO51), (GPIO52), (GPIO53), (GPIO54), (DMA_CH0(unstable)), (DMA_CH1(unstable)),
        (DMA_CH2(unstable)), (DMA_AXI_CH0(unstable)), (DMA_AXI_CH1(unstable)),
        (DMA_AXI_CH2(unstable)), (VDMA_CH0(unstable)), (VDMA_CH1(unstable)),
        (VDMA_CH2(unstable)), (VDMA_CH3(unstable)), (PCNT0_UNIT0(unstable)),
        (PCNT0_UNIT1(unstable)), (PCNT0_UNIT2(unstable)), (PCNT0_UNIT3(unstable)),
        (SDM_CH0(unstable)), (SDM_CH1(unstable)), (SDM_CH2(unstable)),
        (SDM_CH3(unstable)), (SDM_CH4(unstable)), (SDM_CH5(unstable)),
        (SDM_CH6(unstable)), (SDM_CH7(unstable)), (GPIO(unstable)), (GPIO_SD(unstable)),
        (SYSTEM(unstable)), (HP_SYS(unstable)), (HP_SYS_CLKRST(unstable)),
        (RNG(unstable)), (INTERRUPT_CORE0(unstable)), (INTERRUPT_CORE1(unstable)),
        (LP_I2C_ANA_MST(unstable)), (CLIC(unstable)), (CLINT(unstable)),
        (CLINT_OTHER_CORE(unstable)), (IO_MUX(unstable)), (LP_I2C0(unstable)),
        (LP_AON(unstable)), (LP_AON_CLKRST(unstable)), (LP_SYS(unstable)),
        (LP_GPIO(unstable)), (LP_IO_MUX(unstable)), (LP_PERI(unstable)),
        (RTC_TIMER(unstable)), (LP_WDT(unstable)), (LPWR(unstable)), (PMU(unstable)),
        (PAU(unstable)), (SYSTIMER(unstable)), (TIMG0(unstable)), (TIMG1(unstable)),
        (UART0), (UART1), (UART2), (UART3), (UART4), (UHCI0(unstable)), (SPI2), (SPI3),
        (I2C0), (I2C1), (I2S0(unstable)), (I2S1(unstable)), (I2S2(unstable)),
        (TWAI0(unstable)), (TWAI1(unstable)), (TWAI2(unstable)), (DMA(unstable)),
        (AXI_GDMA(unstable)), (ETH(unstable)), (MIPI_DSI(unstable)),
        (USB_DEVICE(unstable)), (SDHOST(unstable)), (LEDC(unstable)), (MCPWM0(unstable)),
        (MCPWM1(unstable)), (PCNT(unstable)), (APB_SARADC(unstable)), (LP_ADC(unstable)),
        (RMT(unstable)), (AES(unstable)), (SHA(unstable)), (RSA(unstable)),
        (ECC(unstable)), (USB_FS(unstable)), (USB_HS(unstable)), (ADC1(unstable)),
        (ADC2(unstable)), (FLASH(unstable)), (PSRAM(unstable)),
        (GPIO_DEDICATED(unstable)), (CPU_CTRL(unstable)), (IPC(unstable)),
        (FROM_CPU_INTR0(unstable)), (FROM_CPU_INTR1(unstable)),
        (FROM_CPU_INTR2(unstable)), (FROM_CPU_INTR3(unstable))));
        _for_each_inner_peripheral!((dma_eligible(SPI2, Spi2, 1, AxiGdmaChannel), (UHCI0,
        Uhci0, 2, AhbGdmaChannel), (SPI3, Spi3, 2, AxiGdmaChannel), (I2S0, I2s0, 3,
        AhbGdmaChannel), (I2S1, I2s1, 4, AhbGdmaChannel), (AES, Aes, 4, AxiGdmaChannel),
        (I2S2, I2s2, 5, AhbGdmaChannel), (SHA, Sha, 5, AxiGdmaChannel)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output])));
        _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2(_0 => MTCK) (_0 => MTCK) ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3(_0 => MTDI) (_0 => MTDI) ([Input] [Output])));
        _for_each_inner_gpio!((4, GPIO4(_0 => MTMS) (_0 => MTMS) ([Input] [Output])));
        _for_each_inner_gpio!((5, GPIO5(_0 => MTDO) (_0 => MTDO) ([Input] [Output])));
        _for_each_inner_gpio!((6, GPIO6(_3 => SPI2_HOLD) (_3 => SPI2_HOLD) ([Input]
        [Output]))); _for_each_inner_gpio!((7, GPIO7(_3 => SPI2_CS) (_3 => SPI2_CS)
        ([Input] [Output]))); _for_each_inner_gpio!((8, GPIO8(_3 => SPI2_D) (_2 =>
        UART0_RTS _3 => SPI2_D) ([Input] [Output]))); _for_each_inner_gpio!((9, GPIO9(_2
        => UART0_CTS _3 => SPI2_CK) (_3 => SPI2_CK) ([Input] [Output])));
        _for_each_inner_gpio!((10, GPIO10(_3 => SPI2_Q) (_2 => UART1_TXD _3 => SPI2_Q)
        ([Input] [Output]))); _for_each_inner_gpio!((11, GPIO11(_2 => UART1_RXD _3 =>
        SPI2_WP) (_3 => SPI2_WP) ([Input] [Output]))); _for_each_inner_gpio!((12,
        GPIO12() (_2 => UART1_RTS) ([Input] [Output]))); _for_each_inner_gpio!((13,
        GPIO13(_2 => UART1_CTS) () ([Input] [Output]))); _for_each_inner_gpio!((14,
        GPIO14() () ([Input] [Output]))); _for_each_inner_gpio!((15, GPIO15() () ([Input]
        [Output]))); _for_each_inner_gpio!((16, GPIO16() () ([Input] [Output])));
        _for_each_inner_gpio!((17, GPIO17() () ([Input] [Output])));
        _for_each_inner_gpio!((18, GPIO18() () ([Input] [Output])));
        _for_each_inner_gpio!((19, GPIO19() () ([Input] [Output])));
        _for_each_inner_gpio!((20, GPIO20() () ([Input] [Output])));
        _for_each_inner_gpio!((21, GPIO21() () ([Input] [Output])));
        _for_each_inner_gpio!((22, GPIO22(_4 => DBG_PSRAM_CK) (_4 => DBG_PSRAM_CK)
        ([Input] [Output]))); _for_each_inner_gpio!((23, GPIO23(_3 => REF_50M_CLK _4 =>
        DBG_PSRAM_CS) (_3 => REF_50M_CLK _4 => DBG_PSRAM_CS) ([Input] [Output])));
        _for_each_inner_gpio!((24, GPIO24() () ([Input] [Output])));
        _for_each_inner_gpio!((25, GPIO25() () ([Input] [Output])));
        _for_each_inner_gpio!((26, GPIO26() () ([Input] [Output])));
        _for_each_inner_gpio!((27, GPIO27() () ([Input] [Output])));
        _for_each_inner_gpio!((28, GPIO28(_2 => SPI2_CS _3 => EMAC_RXDV _4 =>
        DBG_PSRAM_D) (_2 => SPI2_CS _4 => DBG_PSRAM_D) ([Input] [Output])));
        _for_each_inner_gpio!((29, GPIO29(_2 => SPI2_D _3 => EMAC_RXD0 _4 => DBG_PSRAM_Q)
        (_2 => SPI2_D _4 => DBG_PSRAM_Q) ([Input] [Output]))); _for_each_inner_gpio!((30,
        GPIO30(_2 => SPI2_CK _3 => EMAC_RXD1 _4 => DBG_PSRAM_WP) (_2 => SPI2_CK _4 =>
        DBG_PSRAM_WP) ([Input] [Output]))); _for_each_inner_gpio!((31, GPIO31(_2 =>
        SPI2_Q _3 => EMAC_RXER _4 => DBG_PSRAM_HOLD) (_2 => SPI2_Q _4 => DBG_PSRAM_HOLD)
        ([Input] [Output]))); _for_each_inner_gpio!((32, GPIO32(_2 => SPI2_HOLD _3 =>
        EMAC_RMII_CLK _4 => DBG_PSRAM_DQ4) (_2 => SPI2_HOLD _3 => EMAC_RMII_CLK _4 =>
        DBG_PSRAM_DQ4) ([Input] [Output]))); _for_each_inner_gpio!((33, GPIO33(_2 =>
        SPI2_WP _4 => DBG_PSRAM_DQ5) (_2 => SPI2_WP _3 => EMAC_TXEN _4 => DBG_PSRAM_DQ5)
        ([Input] [Output]))); _for_each_inner_gpio!((34, GPIO34(_2 => SPI2_IO4 _4 =>
        DBG_PSRAM_DQ6) (_2 => SPI2_IO4 _3 => EMAC_TXD0 _4 => DBG_PSRAM_DQ6) ([Input]
        [Output]))); _for_each_inner_gpio!((35, GPIO35(_2 => SPI2_IO5 _4 =>
        DBG_PSRAM_DQ7) (_2 => SPI2_IO5 _3 => EMAC_TXD1 _4 => DBG_PSRAM_DQ7) ([Input]
        [Output]))); _for_each_inner_gpio!((36, GPIO36(_2 => SPI2_IO6 _4 =>
        DBG_PSRAM_DQS_0) (_2 => SPI2_IO6 _3 => EMAC_TXER _4 => DBG_PSRAM_DQS_0) ([Input]
        [Output]))); _for_each_inner_gpio!((37, GPIO37(_2 => SPI2_IO7) (_0 => UART0_TXD
        _2 => SPI2_IO7) ([Input] [Output]))); _for_each_inner_gpio!((38, GPIO38(_0 =>
        UART0_RXD _2 => SPI2_DQS) (_2 => SPI2_DQS) ([Input] [Output])));
        _for_each_inner_gpio!((39, GPIO39(_0 => SD1_DATA0 _2 => BIST _3 => REF_50M_CLK _4
        => DBG_PSRAM_DQ8) (_0 => SD1_DATA0 _2 => BIST _3 => REF_50M_CLK _4 =>
        DBG_PSRAM_DQ8) ([Input] [Output]))); _for_each_inner_gpio!((40, GPIO40(_0 =>
        SD1_DATA1 _2 => BIST _4 => DBG_PSRAM_DQ9) (_0 => SD1_DATA1 _2 => BIST _3 =>
        EMAC_TXEN _4 => DBG_PSRAM_DQ9) ([Input] [Output]))); _for_each_inner_gpio!((41,
        GPIO41(_0 => SD1_DATA2 _2 => BIST _4 => DBG_PSRAM_DQ10) (_0 => SD1_DATA2 _2 =>
        BIST _3 => EMAC_TXD0 _4 => DBG_PSRAM_DQ10) ([Input] [Output])));
        _for_each_inner_gpio!((42, GPIO42(_0 => SD1_DATA3 _2 => BIST _4 =>
        DBG_PSRAM_DQ11) (_0 => SD1_DATA3 _2 => BIST _3 => EMAC_TXD1 _4 => DBG_PSRAM_DQ11)
        ([Input] [Output]))); _for_each_inner_gpio!((43, GPIO43(_0 => SD1_CLK _2 => BIST
        _4 => DBG_PSRAM_DQ12) (_0 => SD1_CLK _2 => BIST _3 => EMAC_TXER _4 =>
        DBG_PSRAM_DQ12) ([Input] [Output]))); _for_each_inner_gpio!((44, GPIO44(_0 =>
        SD1_CMD _2 => BIST _3 => EMAC_RMII_CLK _4 => DBG_PSRAM_DQ13) (_0 => SD1_CMD _2 =>
        BIST _3 => EMAC_RMII_CLK _4 => DBG_PSRAM_DQ13) ([Input] [Output])));
        _for_each_inner_gpio!((45, GPIO45(_0 => SD1_DATA4 _2 => BIST _3 => EMAC_RXDV _4
        => DBG_PSRAM_DQ14) (_0 => SD1_DATA4 _2 => BIST _4 => DBG_PSRAM_DQ14) ([Input]
        [Output]))); _for_each_inner_gpio!((46, GPIO46(_0 => SD1_DATA5 _2 => BIST _3 =>
        EMAC_RXD0 _4 => DBG_PSRAM_DQ15) (_0 => SD1_DATA5 _2 => BIST _4 => DBG_PSRAM_DQ15)
        ([Input] [Output]))); _for_each_inner_gpio!((47, GPIO47(_0 => SD1_DATA6 _2 =>
        BIST _3 => EMAC_RXD1 _4 => DBG_PSRAM_DQS_1) (_0 => SD1_DATA6 _2 => BIST _4 =>
        DBG_PSRAM_DQS_1) ([Input] [Output]))); _for_each_inner_gpio!((48, GPIO48(_0 =>
        SD1_DATA7 _2 => BIST _3 => EMAC_RXER) (_0 => SD1_DATA7 _2 => BIST) ([Input]
        [Output]))); _for_each_inner_gpio!((49, GPIO49(_4 => DBG_FLASH_CS) (_3 =>
        EMAC_TXEN _4 => DBG_FLASH_CS) ([Input] [Output]))); _for_each_inner_gpio!((50,
        GPIO50(_3 => EMAC_RMII_CLK _4 => DBG_FLASH_Q) (_3 => EMAC_RMII_CLK _4 =>
        DBG_FLASH_Q) ([Input] [Output]))); _for_each_inner_gpio!((51, GPIO51(_3 =>
        EMAC_RXDV _4 => DBG_FLASH_WP) (_4 => DBG_FLASH_WP) ([Input] [Output])));
        _for_each_inner_gpio!((52, GPIO52(_3 => EMAC_RXD0 _4 => DBG_FLASH_HOLD) (_4 =>
        DBG_FLASH_HOLD) ([Input] [Output]))); _for_each_inner_gpio!((53, GPIO53(_3 =>
        EMAC_RXD1 _4 => DBG_FLASH_CK) (_4 => DBG_FLASH_CK) ([Input] [Output])));
        _for_each_inner_gpio!((54, GPIO54(_3 => EMAC_RXER _4 => DBG_FLASH_D) (_4 =>
        DBG_FLASH_D) ([Input] [Output]))); _for_each_inner_gpio!((all(0, GPIO0() ()
        ([Input] [Output])), (1, GPIO1() () ([Input] [Output])), (2, GPIO2(_0 => MTCK)
        (_0 => MTCK) ([Input] [Output])), (3, GPIO3(_0 => MTDI) (_0 => MTDI) ([Input]
        [Output])), (4, GPIO4(_0 => MTMS) (_0 => MTMS) ([Input] [Output])), (5, GPIO5(_0
        => MTDO) (_0 => MTDO) ([Input] [Output])), (6, GPIO6(_3 => SPI2_HOLD) (_3 =>
        SPI2_HOLD) ([Input] [Output])), (7, GPIO7(_3 => SPI2_CS) (_3 => SPI2_CS) ([Input]
        [Output])), (8, GPIO8(_3 => SPI2_D) (_2 => UART0_RTS _3 => SPI2_D) ([Input]
        [Output])), (9, GPIO9(_2 => UART0_CTS _3 => SPI2_CK) (_3 => SPI2_CK) ([Input]
        [Output])), (10, GPIO10(_3 => SPI2_Q) (_2 => UART1_TXD _3 => SPI2_Q) ([Input]
        [Output])), (11, GPIO11(_2 => UART1_RXD _3 => SPI2_WP) (_3 => SPI2_WP) ([Input]
        [Output])), (12, GPIO12() (_2 => UART1_RTS) ([Input] [Output])), (13, GPIO13(_2
        => UART1_CTS) () ([Input] [Output])), (14, GPIO14() () ([Input] [Output])), (15,
        GPIO15() () ([Input] [Output])), (16, GPIO16() () ([Input] [Output])), (17,
        GPIO17() () ([Input] [Output])), (18, GPIO18() () ([Input] [Output])), (19,
        GPIO19() () ([Input] [Output])), (20, GPIO20() () ([Input] [Output])), (21,
        GPIO21() () ([Input] [Output])), (22, GPIO22(_4 => DBG_PSRAM_CK) (_4 =>
        DBG_PSRAM_CK) ([Input] [Output])), (23, GPIO23(_3 => REF_50M_CLK _4 =>
        DBG_PSRAM_CS) (_3 => REF_50M_CLK _4 => DBG_PSRAM_CS) ([Input] [Output])), (24,
        GPIO24() () ([Input] [Output])), (25, GPIO25() () ([Input] [Output])), (26,
        GPIO26() () ([Input] [Output])), (27, GPIO27() () ([Input] [Output])), (28,
        GPIO28(_2 => SPI2_CS _3 => EMAC_RXDV _4 => DBG_PSRAM_D) (_2 => SPI2_CS _4 =>
        DBG_PSRAM_D) ([Input] [Output])), (29, GPIO29(_2 => SPI2_D _3 => EMAC_RXD0 _4 =>
        DBG_PSRAM_Q) (_2 => SPI2_D _4 => DBG_PSRAM_Q) ([Input] [Output])), (30, GPIO30(_2
        => SPI2_CK _3 => EMAC_RXD1 _4 => DBG_PSRAM_WP) (_2 => SPI2_CK _4 => DBG_PSRAM_WP)
        ([Input] [Output])), (31, GPIO31(_2 => SPI2_Q _3 => EMAC_RXER _4 =>
        DBG_PSRAM_HOLD) (_2 => SPI2_Q _4 => DBG_PSRAM_HOLD) ([Input] [Output])), (32,
        GPIO32(_2 => SPI2_HOLD _3 => EMAC_RMII_CLK _4 => DBG_PSRAM_DQ4) (_2 => SPI2_HOLD
        _3 => EMAC_RMII_CLK _4 => DBG_PSRAM_DQ4) ([Input] [Output])), (33, GPIO33(_2 =>
        SPI2_WP _4 => DBG_PSRAM_DQ5) (_2 => SPI2_WP _3 => EMAC_TXEN _4 => DBG_PSRAM_DQ5)
        ([Input] [Output])), (34, GPIO34(_2 => SPI2_IO4 _4 => DBG_PSRAM_DQ6) (_2 =>
        SPI2_IO4 _3 => EMAC_TXD0 _4 => DBG_PSRAM_DQ6) ([Input] [Output])), (35, GPIO35(_2
        => SPI2_IO5 _4 => DBG_PSRAM_DQ7) (_2 => SPI2_IO5 _3 => EMAC_TXD1 _4 =>
        DBG_PSRAM_DQ7) ([Input] [Output])), (36, GPIO36(_2 => SPI2_IO6 _4 =>
        DBG_PSRAM_DQS_0) (_2 => SPI2_IO6 _3 => EMAC_TXER _4 => DBG_PSRAM_DQS_0) ([Input]
        [Output])), (37, GPIO37(_2 => SPI2_IO7) (_0 => UART0_TXD _2 => SPI2_IO7) ([Input]
        [Output])), (38, GPIO38(_0 => UART0_RXD _2 => SPI2_DQS) (_2 => SPI2_DQS) ([Input]
        [Output])), (39, GPIO39(_0 => SD1_DATA0 _2 => BIST _3 => REF_50M_CLK _4 =>
        DBG_PSRAM_DQ8) (_0 => SD1_DATA0 _2 => BIST _3 => REF_50M_CLK _4 => DBG_PSRAM_DQ8)
        ([Input] [Output])), (40, GPIO40(_0 => SD1_DATA1 _2 => BIST _4 => DBG_PSRAM_DQ9)
        (_0 => SD1_DATA1 _2 => BIST _3 => EMAC_TXEN _4 => DBG_PSRAM_DQ9) ([Input]
        [Output])), (41, GPIO41(_0 => SD1_DATA2 _2 => BIST _4 => DBG_PSRAM_DQ10) (_0 =>
        SD1_DATA2 _2 => BIST _3 => EMAC_TXD0 _4 => DBG_PSRAM_DQ10) ([Input] [Output])),
        (42, GPIO42(_0 => SD1_DATA3 _2 => BIST _4 => DBG_PSRAM_DQ11) (_0 => SD1_DATA3 _2
        => BIST _3 => EMAC_TXD1 _4 => DBG_PSRAM_DQ11) ([Input] [Output])), (43, GPIO43(_0
        => SD1_CLK _2 => BIST _4 => DBG_PSRAM_DQ12) (_0 => SD1_CLK _2 => BIST _3 =>
        EMAC_TXER _4 => DBG_PSRAM_DQ12) ([Input] [Output])), (44, GPIO44(_0 => SD1_CMD _2
        => BIST _3 => EMAC_RMII_CLK _4 => DBG_PSRAM_DQ13) (_0 => SD1_CMD _2 => BIST _3 =>
        EMAC_RMII_CLK _4 => DBG_PSRAM_DQ13) ([Input] [Output])), (45, GPIO45(_0 =>
        SD1_DATA4 _2 => BIST _3 => EMAC_RXDV _4 => DBG_PSRAM_DQ14) (_0 => SD1_DATA4 _2 =>
        BIST _4 => DBG_PSRAM_DQ14) ([Input] [Output])), (46, GPIO46(_0 => SD1_DATA5 _2 =>
        BIST _3 => EMAC_RXD0 _4 => DBG_PSRAM_DQ15) (_0 => SD1_DATA5 _2 => BIST _4 =>
        DBG_PSRAM_DQ15) ([Input] [Output])), (47, GPIO47(_0 => SD1_DATA6 _2 => BIST _3 =>
        EMAC_RXD1 _4 => DBG_PSRAM_DQS_1) (_0 => SD1_DATA6 _2 => BIST _4 =>
        DBG_PSRAM_DQS_1) ([Input] [Output])), (48, GPIO48(_0 => SD1_DATA7 _2 => BIST _3
        => EMAC_RXER) (_0 => SD1_DATA7 _2 => BIST) ([Input] [Output])), (49, GPIO49(_4 =>
        DBG_FLASH_CS) (_3 => EMAC_TXEN _4 => DBG_FLASH_CS) ([Input] [Output])), (50,
        GPIO50(_3 => EMAC_RMII_CLK _4 => DBG_FLASH_Q) (_3 => EMAC_RMII_CLK _4 =>
        DBG_FLASH_Q) ([Input] [Output])), (51, GPIO51(_3 => EMAC_RXDV _4 => DBG_FLASH_WP)
        (_4 => DBG_FLASH_WP) ([Input] [Output])), (52, GPIO52(_3 => EMAC_RXD0 _4 =>
        DBG_FLASH_HOLD) (_4 => DBG_FLASH_HOLD) ([Input] [Output])), (53, GPIO53(_3 =>
        EMAC_RXD1 _4 => DBG_FLASH_CK) (_4 => DBG_FLASH_CK) ([Input] [Output])), (54,
        GPIO54(_3 => EMAC_RXER _4 => DBG_FLASH_D) (_4 => DBG_FLASH_D) ([Input]
        [Output]))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` - expanded signal
///   case, where you need the number(s) of a signal, or the general group to which the signal
///   belongs. For example, in case of `ADC2_CH3` the expanded form looks like `(ADC2_CH3, ADCn_CHm,
///   2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((ADC1_CH0, GPIO16));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO17));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO18));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO19));
        _for_each_inner_analog_function!((ADC1_CH4, GPIO20));
        _for_each_inner_analog_function!((ADC1_CH5, GPIO21));
        _for_each_inner_analog_function!((ADC1_CH6, GPIO22));
        _for_each_inner_analog_function!((ADC1_CH7, GPIO23));
        _for_each_inner_analog_function!((USJ_DM, GPIO24));
        _for_each_inner_analog_function!((USJ_DP, GPIO25));
        _for_each_inner_analog_function!((USB_FS_DM, GPIO26));
        _for_each_inner_analog_function!((USB_FS_DP, GPIO27));
        _for_each_inner_analog_function!((ADC2_CH0, GPIO49));
        _for_each_inner_analog_function!((ADC2_CH1, GPIO50));
        _for_each_inner_analog_function!((ADC2_CH2, GPIO51));
        _for_each_inner_analog_function!((ADC2_CH3, GPIO52));
        _for_each_inner_analog_function!((ADC2_CH4, GPIO53));
        _for_each_inner_analog_function!((ADC2_CH5, GPIO54));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO16));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO17));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO18));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO19));
        _for_each_inner_analog_function!(((ADC1_CH4, ADCn_CHm, 1, 4), GPIO20));
        _for_each_inner_analog_function!(((ADC1_CH5, ADCn_CHm, 1, 5), GPIO21));
        _for_each_inner_analog_function!(((ADC1_CH6, ADCn_CHm, 1, 6), GPIO22));
        _for_each_inner_analog_function!(((ADC1_CH7, ADCn_CHm, 1, 7), GPIO23));
        _for_each_inner_analog_function!(((ADC2_CH0, ADCn_CHm, 2, 0), GPIO49));
        _for_each_inner_analog_function!(((ADC2_CH1, ADCn_CHm, 2, 1), GPIO50));
        _for_each_inner_analog_function!(((ADC2_CH2, ADCn_CHm, 2, 2), GPIO51));
        _for_each_inner_analog_function!(((ADC2_CH3, ADCn_CHm, 2, 3), GPIO52));
        _for_each_inner_analog_function!(((ADC2_CH4, ADCn_CHm, 2, 4), GPIO53));
        _for_each_inner_analog_function!(((ADC2_CH5, ADCn_CHm, 2, 5), GPIO54));
        _for_each_inner_analog_function!((all(ADC1_CH0, GPIO16), (ADC1_CH1, GPIO17),
        (ADC1_CH2, GPIO18), (ADC1_CH3, GPIO19), (ADC1_CH4, GPIO20), (ADC1_CH5, GPIO21),
        (ADC1_CH6, GPIO22), (ADC1_CH7, GPIO23), (USJ_DM, GPIO24), (USJ_DP, GPIO25),
        (USB_FS_DM, GPIO26), (USB_FS_DP, GPIO27), (ADC2_CH0, GPIO49), (ADC2_CH1, GPIO50),
        (ADC2_CH2, GPIO51), (ADC2_CH3, GPIO52), (ADC2_CH4, GPIO53), (ADC2_CH5, GPIO54)));
        _for_each_inner_analog_function!((ADCn_CHm((ADC1_CH0, ADCn_CHm, 1, 0), GPIO16),
        ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO17), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO18),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO19), ((ADC1_CH4, ADCn_CHm, 1, 4), GPIO20),
        ((ADC1_CH5, ADCn_CHm, 1, 5), GPIO21), ((ADC1_CH6, ADCn_CHm, 1, 6), GPIO22),
        ((ADC1_CH7, ADCn_CHm, 1, 7), GPIO23), ((ADC2_CH0, ADCn_CHm, 2, 0), GPIO49),
        ((ADC2_CH1, ADCn_CHm, 2, 1), GPIO50), ((ADC2_CH2, ADCn_CHm, 2, 2), GPIO51),
        ((ADC2_CH3, ADCn_CHm, 2, 3), GPIO52), ((ADC2_CH4, ADCn_CHm, 2, 4), GPIO53),
        ((ADC2_CH5, ADCn_CHm, 2, 5), GPIO54)));
    };
}
/// This macro can be used to generate code for each LP function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident, ($(
///   $lp_input_af:ident => $lp_input_signal:ident )*) ($( $lp_output_af:ident =>
///   $lp_output_signal:ident )*))` - expanded signal case, where you need the number(s) of a
///   signal, or the general group to which the signal belongs. Every expanded branch ends with the
///   pad's LP input and output function groups (empty on chips without an LP GPIO matrix).
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the LP IO MUX function, as an identifier (i.e. for function 0 this is `_0`). This is
///   the name of an `LpFunction` variant, and its number is the value to write to the pad's
///   function select field.
/// - `$lp_input_af`: the LP IO MUX function for an LP peripheral input on this pad.
/// - `$lp_input_signal`: the LP peripheral input signal name.
/// - `$lp_output_af`: the LP IO MUX function for an LP peripheral output on this pad.
/// - `$lp_output_signal`: the LP peripheral output signal name.
///
/// Example data:
/// - `(LP_GPIO15, GPIO12, _0)`
/// - `((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ())`
/// - `((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD))`
/// - `((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((LP_GPIO0, GPIO0, _1));
        _for_each_inner_lp_function!((LP_GPIO1, GPIO1, _1));
        _for_each_inner_lp_function!((LP_GPIO2, GPIO2, _1));
        _for_each_inner_lp_function!((LP_GPIO3, GPIO3, _1));
        _for_each_inner_lp_function!((LP_GPIO4, GPIO4, _1));
        _for_each_inner_lp_function!((LP_GPIO5, GPIO5, _1));
        _for_each_inner_lp_function!((LP_GPIO6, GPIO6, _1));
        _for_each_inner_lp_function!((LP_GPIO7, GPIO7, _1));
        _for_each_inner_lp_function!((LP_GPIO8, GPIO8, _1));
        _for_each_inner_lp_function!((LP_GPIO9, GPIO9, _1));
        _for_each_inner_lp_function!((LP_GPIO10, GPIO10, _1));
        _for_each_inner_lp_function!((LP_GPIO11, GPIO11, _1));
        _for_each_inner_lp_function!((LP_GPIO12, GPIO12, _1));
        _for_each_inner_lp_function!((LP_GPIO13, GPIO13, _1));
        _for_each_inner_lp_function!((LP_UART_TXD, GPIO14, _0));
        _for_each_inner_lp_function!((LP_GPIO14, GPIO14, _1));
        _for_each_inner_lp_function!((LP_UART_RXD, GPIO15, _0));
        _for_each_inner_lp_function!((LP_GPIO15, GPIO15, _1));
        _for_each_inner_lp_function!(((LP_GPIO0, LP_GPIOn, 0), GPIO0, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO1, LP_GPIOn, 1), GPIO1, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO2, LP_GPIOn, 2), GPIO2, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO3, LP_GPIOn, 3), GPIO3, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO4, LP_GPIOn, 4), GPIO4, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO5, LP_GPIOn, 5), GPIO5, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO6, LP_GPIOn, 6), GPIO6, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO7, LP_GPIOn, 7), GPIO7, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO8, LP_GPIOn, 8), GPIO8, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO9, LP_GPIOn, 9), GPIO9, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO10, LP_GPIOn, 10), GPIO10, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO11, LP_GPIOn, 11), GPIO11, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO12, LP_GPIOn, 12), GPIO12, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO13, LP_GPIOn, 13), GPIO13, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 =>
        LP_UART_TXD))); _for_each_inner_lp_function!(((LP_GPIO15, LP_GPIOn, 15), GPIO15,
        _1, (_0 => LP_UART_RXD) ())); _for_each_inner_lp_function!((all(LP_GPIO0, GPIO0,
        _1), (LP_GPIO1, GPIO1, _1), (LP_GPIO2, GPIO2, _1), (LP_GPIO3, GPIO3, _1),
        (LP_GPIO4, GPIO4, _1), (LP_GPIO5, GPIO5, _1), (LP_GPIO6, GPIO6, _1), (LP_GPIO7,
        GPIO7, _1), (LP_GPIO8, GPIO8, _1), (LP_GPIO9, GPIO9, _1), (LP_GPIO10, GPIO10,
        _1), (LP_GPIO11, GPIO11, _1), (LP_GPIO12, GPIO12, _1), (LP_GPIO13, GPIO13, _1),
        (LP_UART_TXD, GPIO14, _0), (LP_GPIO14, GPIO14, _1), (LP_UART_RXD, GPIO15, _0),
        (LP_GPIO15, GPIO15, _1))); _for_each_inner_lp_function!((LP_GPIOn((LP_GPIO0,
        LP_GPIOn, 0), GPIO0, _1, () ()), ((LP_GPIO1, LP_GPIOn, 1), GPIO1, _1, () ()),
        ((LP_GPIO2, LP_GPIOn, 2), GPIO2, _1, () ()), ((LP_GPIO3, LP_GPIOn, 3), GPIO3, _1,
        () ()), ((LP_GPIO4, LP_GPIOn, 4), GPIO4, _1, () ()), ((LP_GPIO5, LP_GPIOn, 5),
        GPIO5, _1, () ()), ((LP_GPIO6, LP_GPIOn, 6), GPIO6, _1, () ()), ((LP_GPIO7,
        LP_GPIOn, 7), GPIO7, _1, () ()), ((LP_GPIO8, LP_GPIOn, 8), GPIO8, _1, () ()),
        ((LP_GPIO9, LP_GPIOn, 9), GPIO9, _1, () ()), ((LP_GPIO10, LP_GPIOn, 10), GPIO10,
        _1, () ()), ((LP_GPIO11, LP_GPIOn, 11), GPIO11, _1, () ()), ((LP_GPIO12,
        LP_GPIOn, 12), GPIO12, _1, () ()), ((LP_GPIO13, LP_GPIOn, 13), GPIO13, _1, ()
        ()), ((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD)),
        ((LP_GPIO15, LP_GPIOn, 15), GPIO15, _1, (_0 => LP_UART_RXD) ())));
    };
}
/// This macro can be used to generate code for each IOMUX digital function of each GPIO.
///
/// IOMUX functions are the alternate digital functions configured via the IO_MUX registers.
/// Use this to implement signal-specific traits for peripherals whose pins must bypass the
/// GPIO matrix (e.g., EMAC, USB).
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the alternate function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the alternate function number, as an identifier (e.g. `_5`).
///
/// Example data:
/// - `(EMAC_RXD0, GPIO25, _5)`
/// - `((EMAC_RXDn, EMAC_RXDn, 0), GPIO25, _5)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_iomux_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_iomux_function!((MTCK, GPIO2, _0));
        _for_each_inner_iomux_function!((MTDI, GPIO3, _0));
        _for_each_inner_iomux_function!((MTMS, GPIO4, _0));
        _for_each_inner_iomux_function!((MTDO, GPIO5, _0));
        _for_each_inner_iomux_function!((SPI2_HOLD, GPIO6, _3));
        _for_each_inner_iomux_function!((SPI2_CS, GPIO7, _3));
        _for_each_inner_iomux_function!((UART0_RTS, GPIO8, _2));
        _for_each_inner_iomux_function!((SPI2_D, GPIO8, _3));
        _for_each_inner_iomux_function!((UART0_CTS, GPIO9, _2));
        _for_each_inner_iomux_function!((SPI2_CK, GPIO9, _3));
        _for_each_inner_iomux_function!((UART1_TXD, GPIO10, _2));
        _for_each_inner_iomux_function!((SPI2_Q, GPIO10, _3));
        _for_each_inner_iomux_function!((UART1_RXD, GPIO11, _2));
        _for_each_inner_iomux_function!((SPI2_WP, GPIO11, _3));
        _for_each_inner_iomux_function!((UART1_RTS, GPIO12, _2));
        _for_each_inner_iomux_function!((UART1_CTS, GPIO13, _2));
        _for_each_inner_iomux_function!((DBG_PSRAM_CK, GPIO22, _4));
        _for_each_inner_iomux_function!((REF_50M_CLK, GPIO23, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_CS, GPIO23, _4));
        _for_each_inner_iomux_function!((SPI2_CS, GPIO28, _2));
        _for_each_inner_iomux_function!((EMAC_RXDV, GPIO28, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_D, GPIO28, _4));
        _for_each_inner_iomux_function!((SPI2_D, GPIO29, _2));
        _for_each_inner_iomux_function!((EMAC_RXD0, GPIO29, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_Q, GPIO29, _4));
        _for_each_inner_iomux_function!((SPI2_CK, GPIO30, _2));
        _for_each_inner_iomux_function!((EMAC_RXD1, GPIO30, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_WP, GPIO30, _4));
        _for_each_inner_iomux_function!((SPI2_Q, GPIO31, _2));
        _for_each_inner_iomux_function!((EMAC_RXER, GPIO31, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_HOLD, GPIO31, _4));
        _for_each_inner_iomux_function!((SPI2_HOLD, GPIO32, _2));
        _for_each_inner_iomux_function!((EMAC_RMII_CLK, GPIO32, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ4, GPIO32, _4));
        _for_each_inner_iomux_function!((SPI2_WP, GPIO33, _2));
        _for_each_inner_iomux_function!((EMAC_TXEN, GPIO33, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ5, GPIO33, _4));
        _for_each_inner_iomux_function!((SPI2_IO4, GPIO34, _2));
        _for_each_inner_iomux_function!((EMAC_TXD0, GPIO34, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ6, GPIO34, _4));
        _for_each_inner_iomux_function!((SPI2_IO5, GPIO35, _2));
        _for_each_inner_iomux_function!((EMAC_TXD1, GPIO35, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ7, GPIO35, _4));
        _for_each_inner_iomux_function!((SPI2_IO6, GPIO36, _2));
        _for_each_inner_iomux_function!((EMAC_TXER, GPIO36, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQS_0, GPIO36, _4));
        _for_each_inner_iomux_function!((UART0_TXD, GPIO37, _0));
        _for_each_inner_iomux_function!((SPI2_IO7, GPIO37, _2));
        _for_each_inner_iomux_function!((UART0_RXD, GPIO38, _0));
        _for_each_inner_iomux_function!((SPI2_DQS, GPIO38, _2));
        _for_each_inner_iomux_function!((SD1_DATA0, GPIO39, _0));
        _for_each_inner_iomux_function!((BIST, GPIO39, _2));
        _for_each_inner_iomux_function!((REF_50M_CLK, GPIO39, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ8, GPIO39, _4));
        _for_each_inner_iomux_function!((SD1_DATA1, GPIO40, _0));
        _for_each_inner_iomux_function!((BIST, GPIO40, _2));
        _for_each_inner_iomux_function!((EMAC_TXEN, GPIO40, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ9, GPIO40, _4));
        _for_each_inner_iomux_function!((SD1_DATA2, GPIO41, _0));
        _for_each_inner_iomux_function!((BIST, GPIO41, _2));
        _for_each_inner_iomux_function!((EMAC_TXD0, GPIO41, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ10, GPIO41, _4));
        _for_each_inner_iomux_function!((SD1_DATA3, GPIO42, _0));
        _for_each_inner_iomux_function!((BIST, GPIO42, _2));
        _for_each_inner_iomux_function!((EMAC_TXD1, GPIO42, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ11, GPIO42, _4));
        _for_each_inner_iomux_function!((SD1_CLK, GPIO43, _0));
        _for_each_inner_iomux_function!((BIST, GPIO43, _2));
        _for_each_inner_iomux_function!((EMAC_TXER, GPIO43, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ12, GPIO43, _4));
        _for_each_inner_iomux_function!((SD1_CMD, GPIO44, _0));
        _for_each_inner_iomux_function!((BIST, GPIO44, _2));
        _for_each_inner_iomux_function!((EMAC_RMII_CLK, GPIO44, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ13, GPIO44, _4));
        _for_each_inner_iomux_function!((SD1_DATA4, GPIO45, _0));
        _for_each_inner_iomux_function!((BIST, GPIO45, _2));
        _for_each_inner_iomux_function!((EMAC_RXDV, GPIO45, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ14, GPIO45, _4));
        _for_each_inner_iomux_function!((SD1_DATA5, GPIO46, _0));
        _for_each_inner_iomux_function!((BIST, GPIO46, _2));
        _for_each_inner_iomux_function!((EMAC_RXD0, GPIO46, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQ15, GPIO46, _4));
        _for_each_inner_iomux_function!((SD1_DATA6, GPIO47, _0));
        _for_each_inner_iomux_function!((BIST, GPIO47, _2));
        _for_each_inner_iomux_function!((EMAC_RXD1, GPIO47, _3));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQS_1, GPIO47, _4));
        _for_each_inner_iomux_function!((SD1_DATA7, GPIO48, _0));
        _for_each_inner_iomux_function!((BIST, GPIO48, _2));
        _for_each_inner_iomux_function!((EMAC_RXER, GPIO48, _3));
        _for_each_inner_iomux_function!((EMAC_TXEN, GPIO49, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_CS, GPIO49, _4));
        _for_each_inner_iomux_function!((EMAC_RMII_CLK, GPIO50, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_Q, GPIO50, _4));
        _for_each_inner_iomux_function!((EMAC_RXDV, GPIO51, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_WP, GPIO51, _4));
        _for_each_inner_iomux_function!((EMAC_RXD0, GPIO52, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_HOLD, GPIO52, _4));
        _for_each_inner_iomux_function!((EMAC_RXD1, GPIO53, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_CK, GPIO53, _4));
        _for_each_inner_iomux_function!((EMAC_RXER, GPIO54, _3));
        _for_each_inner_iomux_function!((DBG_FLASH_D, GPIO54, _4));
        _for_each_inner_iomux_function!(((SPI2_HOLD, SPIn_HOLD, 2), GPIO6, _3));
        _for_each_inner_iomux_function!(((SPI2_HOLD, SPIn_HOLD, 2), GPIO32, _2));
        _for_each_inner_iomux_function!(((SPI2_CS, SPIn_CS, 2), GPIO7, _3));
        _for_each_inner_iomux_function!(((SPI2_CS, SPIn_CS, 2), GPIO28, _2));
        _for_each_inner_iomux_function!(((UART0_RTS, UARTn_RTS, 0), GPIO8, _2));
        _for_each_inner_iomux_function!(((UART1_RTS, UARTn_RTS, 1), GPIO12, _2));
        _for_each_inner_iomux_function!(((SPI2_D, SPIn_D, 2), GPIO8, _3));
        _for_each_inner_iomux_function!(((SPI2_D, SPIn_D, 2), GPIO29, _2));
        _for_each_inner_iomux_function!(((UART0_CTS, UARTn_CTS, 0), GPIO9, _2));
        _for_each_inner_iomux_function!(((UART1_CTS, UARTn_CTS, 1), GPIO13, _2));
        _for_each_inner_iomux_function!(((SPI2_CK, SPIn_CK, 2), GPIO9, _3));
        _for_each_inner_iomux_function!(((SPI2_CK, SPIn_CK, 2), GPIO30, _2));
        _for_each_inner_iomux_function!(((UART1_TXD, UARTn_TXD, 1), GPIO10, _2));
        _for_each_inner_iomux_function!(((UART0_TXD, UARTn_TXD, 0), GPIO37, _0));
        _for_each_inner_iomux_function!(((SPI2_Q, SPIn_Q, 2), GPIO10, _3));
        _for_each_inner_iomux_function!(((SPI2_Q, SPIn_Q, 2), GPIO31, _2));
        _for_each_inner_iomux_function!(((UART1_RXD, UARTn_RXD, 1), GPIO11, _2));
        _for_each_inner_iomux_function!(((UART0_RXD, UARTn_RXD, 0), GPIO38, _0));
        _for_each_inner_iomux_function!(((SPI2_WP, SPIn_WP, 2), GPIO11, _3));
        _for_each_inner_iomux_function!(((SPI2_WP, SPIn_WP, 2), GPIO33, _2));
        _for_each_inner_iomux_function!(((EMAC_RXD0, EMAC_RXDn, 0), GPIO29, _3));
        _for_each_inner_iomux_function!(((EMAC_RXD1, EMAC_RXDn, 1), GPIO30, _3));
        _for_each_inner_iomux_function!(((EMAC_RXD0, EMAC_RXDn, 0), GPIO46, _3));
        _for_each_inner_iomux_function!(((EMAC_RXD1, EMAC_RXDn, 1), GPIO47, _3));
        _for_each_inner_iomux_function!(((EMAC_RXD0, EMAC_RXDn, 0), GPIO52, _3));
        _for_each_inner_iomux_function!(((EMAC_RXD1, EMAC_RXDn, 1), GPIO53, _3));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ4, DBG_PSRAM_DQn, 4), GPIO32, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ5, DBG_PSRAM_DQn, 5), GPIO33, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ6, DBG_PSRAM_DQn, 6), GPIO34, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ7, DBG_PSRAM_DQn, 7), GPIO35, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ8, DBG_PSRAM_DQn, 8), GPIO39, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ9, DBG_PSRAM_DQn, 9), GPIO40, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ10, DBG_PSRAM_DQn, 10), GPIO41,
        _4)); _for_each_inner_iomux_function!(((DBG_PSRAM_DQ11, DBG_PSRAM_DQn, 11),
        GPIO42, _4)); _for_each_inner_iomux_function!(((DBG_PSRAM_DQ12, DBG_PSRAM_DQn,
        12), GPIO43, _4)); _for_each_inner_iomux_function!(((DBG_PSRAM_DQ13,
        DBG_PSRAM_DQn, 13), GPIO44, _4));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQ14, DBG_PSRAM_DQn, 14), GPIO45,
        _4)); _for_each_inner_iomux_function!(((DBG_PSRAM_DQ15, DBG_PSRAM_DQn, 15),
        GPIO46, _4)); _for_each_inner_iomux_function!(((SPI2_IO4, SPIn_IOm, 2, 4),
        GPIO34, _2)); _for_each_inner_iomux_function!(((SPI2_IO5, SPIn_IOm, 2, 5),
        GPIO35, _2)); _for_each_inner_iomux_function!(((SPI2_IO6, SPIn_IOm, 2, 6),
        GPIO36, _2)); _for_each_inner_iomux_function!(((SPI2_IO7, SPIn_IOm, 2, 7),
        GPIO37, _2)); _for_each_inner_iomux_function!(((EMAC_TXD0, EMAC_TXDn, 0), GPIO34,
        _3)); _for_each_inner_iomux_function!(((EMAC_TXD1, EMAC_TXDn, 1), GPIO35, _3));
        _for_each_inner_iomux_function!(((EMAC_TXD0, EMAC_TXDn, 0), GPIO41, _3));
        _for_each_inner_iomux_function!(((EMAC_TXD1, EMAC_TXDn, 1), GPIO42, _3));
        _for_each_inner_iomux_function!(((DBG_PSRAM_DQS_0, DBG_PSRAM_DQS_n, 0), GPIO36,
        _4)); _for_each_inner_iomux_function!(((DBG_PSRAM_DQS_1, DBG_PSRAM_DQS_n, 1),
        GPIO47, _4)); _for_each_inner_iomux_function!(((SPI2_DQS, SPIn_DQS, 2), GPIO38,
        _2)); _for_each_inner_iomux_function!(((SD1_DATA0, SDn_DATAm, 1, 0), GPIO39,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA1, SDn_DATAm, 1, 1), GPIO40,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA2, SDn_DATAm, 1, 2), GPIO41,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA3, SDn_DATAm, 1, 3), GPIO42,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA4, SDn_DATAm, 1, 4), GPIO45,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA5, SDn_DATAm, 1, 5), GPIO46,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA6, SDn_DATAm, 1, 6), GPIO47,
        _0)); _for_each_inner_iomux_function!(((SD1_DATA7, SDn_DATAm, 1, 7), GPIO48,
        _0)); _for_each_inner_iomux_function!(((SD1_CLK, SDn_CLK, 1), GPIO43, _0));
        _for_each_inner_iomux_function!(((SD1_CMD, SDn_CMD, 1), GPIO44, _0));
        _for_each_inner_iomux_function!((all(MTCK, GPIO2, _0), (MTDI, GPIO3, _0), (MTMS,
        GPIO4, _0), (MTDO, GPIO5, _0), (SPI2_HOLD, GPIO6, _3), (SPI2_CS, GPIO7, _3),
        (UART0_RTS, GPIO8, _2), (SPI2_D, GPIO8, _3), (UART0_CTS, GPIO9, _2), (SPI2_CK,
        GPIO9, _3), (UART1_TXD, GPIO10, _2), (SPI2_Q, GPIO10, _3), (UART1_RXD, GPIO11,
        _2), (SPI2_WP, GPIO11, _3), (UART1_RTS, GPIO12, _2), (UART1_CTS, GPIO13, _2),
        (DBG_PSRAM_CK, GPIO22, _4), (REF_50M_CLK, GPIO23, _3), (DBG_PSRAM_CS, GPIO23,
        _4), (SPI2_CS, GPIO28, _2), (EMAC_RXDV, GPIO28, _3), (DBG_PSRAM_D, GPIO28, _4),
        (SPI2_D, GPIO29, _2), (EMAC_RXD0, GPIO29, _3), (DBG_PSRAM_Q, GPIO29, _4),
        (SPI2_CK, GPIO30, _2), (EMAC_RXD1, GPIO30, _3), (DBG_PSRAM_WP, GPIO30, _4),
        (SPI2_Q, GPIO31, _2), (EMAC_RXER, GPIO31, _3), (DBG_PSRAM_HOLD, GPIO31, _4),
        (SPI2_HOLD, GPIO32, _2), (EMAC_RMII_CLK, GPIO32, _3), (DBG_PSRAM_DQ4, GPIO32,
        _4), (SPI2_WP, GPIO33, _2), (EMAC_TXEN, GPIO33, _3), (DBG_PSRAM_DQ5, GPIO33, _4),
        (SPI2_IO4, GPIO34, _2), (EMAC_TXD0, GPIO34, _3), (DBG_PSRAM_DQ6, GPIO34, _4),
        (SPI2_IO5, GPIO35, _2), (EMAC_TXD1, GPIO35, _3), (DBG_PSRAM_DQ7, GPIO35, _4),
        (SPI2_IO6, GPIO36, _2), (EMAC_TXER, GPIO36, _3), (DBG_PSRAM_DQS_0, GPIO36, _4),
        (UART0_TXD, GPIO37, _0), (SPI2_IO7, GPIO37, _2), (UART0_RXD, GPIO38, _0),
        (SPI2_DQS, GPIO38, _2), (SD1_DATA0, GPIO39, _0), (BIST, GPIO39, _2),
        (REF_50M_CLK, GPIO39, _3), (DBG_PSRAM_DQ8, GPIO39, _4), (SD1_DATA1, GPIO40, _0),
        (BIST, GPIO40, _2), (EMAC_TXEN, GPIO40, _3), (DBG_PSRAM_DQ9, GPIO40, _4),
        (SD1_DATA2, GPIO41, _0), (BIST, GPIO41, _2), (EMAC_TXD0, GPIO41, _3),
        (DBG_PSRAM_DQ10, GPIO41, _4), (SD1_DATA3, GPIO42, _0), (BIST, GPIO42, _2),
        (EMAC_TXD1, GPIO42, _3), (DBG_PSRAM_DQ11, GPIO42, _4), (SD1_CLK, GPIO43, _0),
        (BIST, GPIO43, _2), (EMAC_TXER, GPIO43, _3), (DBG_PSRAM_DQ12, GPIO43, _4),
        (SD1_CMD, GPIO44, _0), (BIST, GPIO44, _2), (EMAC_RMII_CLK, GPIO44, _3),
        (DBG_PSRAM_DQ13, GPIO44, _4), (SD1_DATA4, GPIO45, _0), (BIST, GPIO45, _2),
        (EMAC_RXDV, GPIO45, _3), (DBG_PSRAM_DQ14, GPIO45, _4), (SD1_DATA5, GPIO46, _0),
        (BIST, GPIO46, _2), (EMAC_RXD0, GPIO46, _3), (DBG_PSRAM_DQ15, GPIO46, _4),
        (SD1_DATA6, GPIO47, _0), (BIST, GPIO47, _2), (EMAC_RXD1, GPIO47, _3),
        (DBG_PSRAM_DQS_1, GPIO47, _4), (SD1_DATA7, GPIO48, _0), (BIST, GPIO48, _2),
        (EMAC_RXER, GPIO48, _3), (EMAC_TXEN, GPIO49, _3), (DBG_FLASH_CS, GPIO49, _4),
        (EMAC_RMII_CLK, GPIO50, _3), (DBG_FLASH_Q, GPIO50, _4), (EMAC_RXDV, GPIO51, _3),
        (DBG_FLASH_WP, GPIO51, _4), (EMAC_RXD0, GPIO52, _3), (DBG_FLASH_HOLD, GPIO52,
        _4), (EMAC_RXD1, GPIO53, _3), (DBG_FLASH_CK, GPIO53, _4), (EMAC_RXER, GPIO54,
        _3), (DBG_FLASH_D, GPIO54, _4)));
        _for_each_inner_iomux_function!((SPIn_HOLD((SPI2_HOLD, SPIn_HOLD, 2), GPIO6, _3),
        ((SPI2_HOLD, SPIn_HOLD, 2), GPIO32, _2)));
        _for_each_inner_iomux_function!((SPIn_CS((SPI2_CS, SPIn_CS, 2), GPIO7, _3),
        ((SPI2_CS, SPIn_CS, 2), GPIO28, _2)));
        _for_each_inner_iomux_function!((UARTn_RTS((UART0_RTS, UARTn_RTS, 0), GPIO8, _2),
        ((UART1_RTS, UARTn_RTS, 1), GPIO12, _2)));
        _for_each_inner_iomux_function!((SPIn_D((SPI2_D, SPIn_D, 2), GPIO8, _3),
        ((SPI2_D, SPIn_D, 2), GPIO29, _2)));
        _for_each_inner_iomux_function!((UARTn_CTS((UART0_CTS, UARTn_CTS, 0), GPIO9, _2),
        ((UART1_CTS, UARTn_CTS, 1), GPIO13, _2)));
        _for_each_inner_iomux_function!((SPIn_CK((SPI2_CK, SPIn_CK, 2), GPIO9, _3),
        ((SPI2_CK, SPIn_CK, 2), GPIO30, _2)));
        _for_each_inner_iomux_function!((UARTn_TXD((UART1_TXD, UARTn_TXD, 1), GPIO10,
        _2), ((UART0_TXD, UARTn_TXD, 0), GPIO37, _0)));
        _for_each_inner_iomux_function!((SPIn_Q((SPI2_Q, SPIn_Q, 2), GPIO10, _3),
        ((SPI2_Q, SPIn_Q, 2), GPIO31, _2)));
        _for_each_inner_iomux_function!((UARTn_RXD((UART1_RXD, UARTn_RXD, 1), GPIO11,
        _2), ((UART0_RXD, UARTn_RXD, 0), GPIO38, _0)));
        _for_each_inner_iomux_function!((SPIn_WP((SPI2_WP, SPIn_WP, 2), GPIO11, _3),
        ((SPI2_WP, SPIn_WP, 2), GPIO33, _2)));
        _for_each_inner_iomux_function!((EMAC_RXDn((EMAC_RXD0, EMAC_RXDn, 0), GPIO29,
        _3), ((EMAC_RXD1, EMAC_RXDn, 1), GPIO30, _3), ((EMAC_RXD0, EMAC_RXDn, 0), GPIO46,
        _3), ((EMAC_RXD1, EMAC_RXDn, 1), GPIO47, _3), ((EMAC_RXD0, EMAC_RXDn, 0), GPIO52,
        _3), ((EMAC_RXD1, EMAC_RXDn, 1), GPIO53, _3)));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQn((DBG_PSRAM_DQ4, DBG_PSRAM_DQn, 4),
        GPIO32, _4), ((DBG_PSRAM_DQ5, DBG_PSRAM_DQn, 5), GPIO33, _4), ((DBG_PSRAM_DQ6,
        DBG_PSRAM_DQn, 6), GPIO34, _4), ((DBG_PSRAM_DQ7, DBG_PSRAM_DQn, 7), GPIO35, _4),
        ((DBG_PSRAM_DQ8, DBG_PSRAM_DQn, 8), GPIO39, _4), ((DBG_PSRAM_DQ9, DBG_PSRAM_DQn,
        9), GPIO40, _4), ((DBG_PSRAM_DQ10, DBG_PSRAM_DQn, 10), GPIO41, _4),
        ((DBG_PSRAM_DQ11, DBG_PSRAM_DQn, 11), GPIO42, _4), ((DBG_PSRAM_DQ12,
        DBG_PSRAM_DQn, 12), GPIO43, _4), ((DBG_PSRAM_DQ13, DBG_PSRAM_DQn, 13), GPIO44,
        _4), ((DBG_PSRAM_DQ14, DBG_PSRAM_DQn, 14), GPIO45, _4), ((DBG_PSRAM_DQ15,
        DBG_PSRAM_DQn, 15), GPIO46, _4)));
        _for_each_inner_iomux_function!((SPIn_IOm((SPI2_IO4, SPIn_IOm, 2, 4), GPIO34,
        _2), ((SPI2_IO5, SPIn_IOm, 2, 5), GPIO35, _2), ((SPI2_IO6, SPIn_IOm, 2, 6),
        GPIO36, _2), ((SPI2_IO7, SPIn_IOm, 2, 7), GPIO37, _2)));
        _for_each_inner_iomux_function!((EMAC_TXDn((EMAC_TXD0, EMAC_TXDn, 0), GPIO34,
        _3), ((EMAC_TXD1, EMAC_TXDn, 1), GPIO35, _3), ((EMAC_TXD0, EMAC_TXDn, 0), GPIO41,
        _3), ((EMAC_TXD1, EMAC_TXDn, 1), GPIO42, _3)));
        _for_each_inner_iomux_function!((DBG_PSRAM_DQS_n((DBG_PSRAM_DQS_0,
        DBG_PSRAM_DQS_n, 0), GPIO36, _4), ((DBG_PSRAM_DQS_1, DBG_PSRAM_DQS_n, 1), GPIO47,
        _4))); _for_each_inner_iomux_function!((SPIn_DQS((SPI2_DQS, SPIn_DQS, 2), GPIO38,
        _2))); _for_each_inner_iomux_function!((SDn_DATAm((SD1_DATA0, SDn_DATAm, 1, 0),
        GPIO39, _0), ((SD1_DATA1, SDn_DATAm, 1, 1), GPIO40, _0), ((SD1_DATA2, SDn_DATAm,
        1, 2), GPIO41, _0), ((SD1_DATA3, SDn_DATAm, 1, 3), GPIO42, _0), ((SD1_DATA4,
        SDn_DATAm, 1, 4), GPIO45, _0), ((SD1_DATA5, SDn_DATAm, 1, 5), GPIO46, _0),
        ((SD1_DATA6, SDn_DATAm, 1, 6), GPIO47, _0), ((SD1_DATA7, SDn_DATAm, 1, 7),
        GPIO48, _0))); _for_each_inner_iomux_function!((SDn_CLK((SD1_CLK, SDn_CLK, 1),
        GPIO43, _0))); _for_each_inner_iomux_function!((SDn_CMD((SD1_CMD, SDn_CMD, 1),
        GPIO44, _0)));
    };
}
/// Returns the name of the GPIO that provides the given signal, as a string.
///
/// The macro takes the name of a direct function - a digital IO MUX function, an analog
/// function, or an LP IO MUX function - and expands to a string literal like `"GPIO4"`. It
/// is meant to keep documentation free of per-chip pin lists.
///
/// Signals that are not wired to a pad on this chip have to be routed through the GPIO
/// matrix, which can reach any pad. The macro has no pad to return for those, so it accepts
/// an optional fallback to expand to instead. The fallback is not validated.
///
/// If multiple pads provide the signal, the macro returns one that is not reserved for some
/// other purpose, such as booting or interfacing with flash.
///
/// Example usage:
/// - `gpio_for_signal!(ADC1_CH0)`
/// - `gpio_for_signal!(LP_I2C_SDA, "GPIO6")`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! gpio_for_signal {
    (LP_GPIO0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (LP_GPIO1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (MTCK $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (LP_GPIO2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (MTDI $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (LP_GPIO3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (MTMS $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (LP_GPIO4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (MTDO $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (LP_GPIO5 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (SPI2_HOLD $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (LP_GPIO6 $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (SPI2_CS $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (LP_GPIO7 $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (UART0_RTS $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (SPI2_D $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (LP_GPIO8 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (UART0_CTS $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (SPI2_CK $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (LP_GPIO9 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (UART1_TXD $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SPI2_Q $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (LP_GPIO10 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (UART1_RXD $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (SPI2_WP $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (LP_GPIO11 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (UART1_RTS $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (LP_GPIO12 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (UART1_CTS $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (LP_GPIO13 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (LP_UART_TXD $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (LP_GPIO14 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (LP_UART_RXD $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (LP_GPIO15 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (ADC1_CH0 $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (ADC1_CH1 $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (ADC1_CH2 $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (ADC1_CH3 $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (ADC1_CH4 $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (ADC1_CH5 $(, $_fallback:literal)?) => {
        "GPIO21"
    };
    (DBG_PSRAM_CK $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (ADC1_CH6 $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (REF_50M_CLK $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (DBG_PSRAM_CS $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (ADC1_CH7 $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (USJ_DM $(, $_fallback:literal)?) => {
        "GPIO24"
    };
    (USJ_DP $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (USB_FS_DM $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (USB_FS_DP $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (EMAC_RXDV $(, $_fallback:literal)?) => {
        "GPIO28"
    };
    (DBG_PSRAM_D $(, $_fallback:literal)?) => {
        "GPIO28"
    };
    (EMAC_RXD0 $(, $_fallback:literal)?) => {
        "GPIO29"
    };
    (DBG_PSRAM_Q $(, $_fallback:literal)?) => {
        "GPIO29"
    };
    (EMAC_RXD1 $(, $_fallback:literal)?) => {
        "GPIO30"
    };
    (DBG_PSRAM_WP $(, $_fallback:literal)?) => {
        "GPIO30"
    };
    (EMAC_RXER $(, $_fallback:literal)?) => {
        "GPIO31"
    };
    (DBG_PSRAM_HOLD $(, $_fallback:literal)?) => {
        "GPIO31"
    };
    (EMAC_RMII_CLK $(, $_fallback:literal)?) => {
        "GPIO44"
    };
    (DBG_PSRAM_DQ4 $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (EMAC_TXEN $(, $_fallback:literal)?) => {
        "GPIO40"
    };
    (DBG_PSRAM_DQ5 $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (SPI2_IO4 $(, $_fallback:literal)?) => {
        "GPIO34"
    };
    (EMAC_TXD0 $(, $_fallback:literal)?) => {
        "GPIO41"
    };
    (DBG_PSRAM_DQ6 $(, $_fallback:literal)?) => {
        "GPIO34"
    };
    (SPI2_IO5 $(, $_fallback:literal)?) => {
        "GPIO35"
    };
    (EMAC_TXD1 $(, $_fallback:literal)?) => {
        "GPIO42"
    };
    (DBG_PSRAM_DQ7 $(, $_fallback:literal)?) => {
        "GPIO35"
    };
    (SPI2_IO6 $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (EMAC_TXER $(, $_fallback:literal)?) => {
        "GPIO43"
    };
    (DBG_PSRAM_DQS_0 $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (UART0_TXD $(, $_fallback:literal)?) => {
        "GPIO37"
    };
    (SPI2_IO7 $(, $_fallback:literal)?) => {
        "GPIO37"
    };
    (UART0_RXD $(, $_fallback:literal)?) => {
        "GPIO38"
    };
    (SPI2_DQS $(, $_fallback:literal)?) => {
        "GPIO38"
    };
    (SD1_DATA0 $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    (BIST $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    (DBG_PSRAM_DQ8 $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    (SD1_DATA1 $(, $_fallback:literal)?) => {
        "GPIO40"
    };
    (DBG_PSRAM_DQ9 $(, $_fallback:literal)?) => {
        "GPIO40"
    };
    (SD1_DATA2 $(, $_fallback:literal)?) => {
        "GPIO41"
    };
    (DBG_PSRAM_DQ10 $(, $_fallback:literal)?) => {
        "GPIO41"
    };
    (SD1_DATA3 $(, $_fallback:literal)?) => {
        "GPIO42"
    };
    (DBG_PSRAM_DQ11 $(, $_fallback:literal)?) => {
        "GPIO42"
    };
    (SD1_CLK $(, $_fallback:literal)?) => {
        "GPIO43"
    };
    (DBG_PSRAM_DQ12 $(, $_fallback:literal)?) => {
        "GPIO43"
    };
    (SD1_CMD $(, $_fallback:literal)?) => {
        "GPIO44"
    };
    (DBG_PSRAM_DQ13 $(, $_fallback:literal)?) => {
        "GPIO44"
    };
    (SD1_DATA4 $(, $_fallback:literal)?) => {
        "GPIO45"
    };
    (DBG_PSRAM_DQ14 $(, $_fallback:literal)?) => {
        "GPIO45"
    };
    (SD1_DATA5 $(, $_fallback:literal)?) => {
        "GPIO46"
    };
    (DBG_PSRAM_DQ15 $(, $_fallback:literal)?) => {
        "GPIO46"
    };
    (SD1_DATA6 $(, $_fallback:literal)?) => {
        "GPIO47"
    };
    (DBG_PSRAM_DQS_1 $(, $_fallback:literal)?) => {
        "GPIO47"
    };
    (SD1_DATA7 $(, $_fallback:literal)?) => {
        "GPIO48"
    };
    (DBG_FLASH_CS $(, $_fallback:literal)?) => {
        "GPIO49"
    };
    (ADC2_CH0 $(, $_fallback:literal)?) => {
        "GPIO49"
    };
    (DBG_FLASH_Q $(, $_fallback:literal)?) => {
        "GPIO50"
    };
    (ADC2_CH1 $(, $_fallback:literal)?) => {
        "GPIO50"
    };
    (DBG_FLASH_WP $(, $_fallback:literal)?) => {
        "GPIO51"
    };
    (ADC2_CH2 $(, $_fallback:literal)?) => {
        "GPIO51"
    };
    (DBG_FLASH_HOLD $(, $_fallback:literal)?) => {
        "GPIO52"
    };
    (ADC2_CH3 $(, $_fallback:literal)?) => {
        "GPIO52"
    };
    (DBG_FLASH_CK $(, $_fallback:literal)?) => {
        "GPIO53"
    };
    (ADC2_CH4 $(, $_fallback:literal)?) => {
        "GPIO53"
    };
    (DBG_FLASH_D $(, $_fallback:literal)?) => {
        "GPIO54"
    };
    (ADC2_CH5 $(, $_fallback:literal)?) => {
        "GPIO54"
    };
    ($_signal:ident, $fallback:literal) => {
        $fallback
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            SDHOST_CCMD_IN_2        = 1,
            SDHOST_CDATA_IN_20      = 2,
            SDHOST_CDATA_IN_21      = 3,
            SDHOST_CDATA_IN_22      = 4,
            SDHOST_CDATA_IN_23      = 5,
            SDHOST_CDATA_IN_24      = 6,
            SDHOST_CDATA_IN_25      = 7,
            SDHOST_CDATA_IN_26      = 8,
            SDHOST_CDATA_IN_27      = 9,
            UART0_RXD               = 10,
            UART0_CTS               = 11,
            UART0_DSR               = 12,
            UART1_RXD               = 13,
            UART1_CTS               = 14,
            UART1_DSR               = 15,
            UART2_RXD               = 16,
            UART2_CTS               = 17,
            UART2_DSR               = 18,
            UART3_RXD               = 19,
            UART3_CTS               = 20,
            UART3_DSR               = 21,
            UART4_RXD               = 22,
            UART4_CTS               = 23,
            UART4_DSR               = 24,
            I2S0_O_BCK              = 25,
            I2S0_MCLK               = 26,
            I2S0_O_WS               = 27,
            I2S0_I_SD               = 28,
            I2S0_I_BCK              = 29,
            I2S0_I_WS               = 30,
            I2S1_O_BCK              = 31,
            I2S1_MCLK               = 32,
            I2S1_O_WS               = 33,
            I2S1_I_SD               = 34,
            I2S1_I_BCK              = 35,
            I2S1_I_WS               = 36,
            I2S2_O_BCK              = 37,
            I2S2_MCLK               = 38,
            I2S2_O_WS               = 39,
            I2S2_I_SD               = 40,
            I2S2_I_BCK              = 41,
            I2S2_I_WS               = 42,
            I2S0_I_SD1              = 43,
            I2S0_I_SD2              = 44,
            I2S0_I_SD3              = 45,
            SPI3_CK                 = 47,
            SPI3_Q                  = 48,
            SPI3_D                  = 49,
            SPI3_HOLD               = 50,
            SPI3_WP                 = 51,
            SPI3_CS                 = 52,
            SPI2_CK                 = 53,
            SPI2_Q                  = 54,
            SPI2_D                  = 55,
            SPI2_HOLD               = 56,
            SPI2_WP                 = 57,
            SPI2_IO4                = 58,
            SPI2_IO5                = 59,
            SPI2_IO6                = 60,
            SPI2_IO7                = 61,
            SPI2_CS                 = 62,
            I2C0_SCL                = 68,
            I2C0_SDA                = 69,
            I2C1_SCL                = 70,
            I2C1_SDA                = 71,
            UART0_SLP_CLK           = 74,
            UART1_SLP_CLK           = 75,
            UART2_SLP_CLK           = 76,
            UART3_SLP_CLK           = 77,
            UART4_SLP_CLK           = 78,
            TWAI0_RX                = 80,
            TWAI1_RX                = 83,
            TWAI2_RX                = 86,
            PWM0_SYNC0              = 89,
            PWM0_SYNC1              = 90,
            PWM0_SYNC2              = 91,
            PWM0_F0                 = 92,
            PWM0_F1                 = 93,
            PWM0_F2                 = 94,
            PWM0_CAP0               = 95,
            PWM0_CAP1               = 96,
            PWM0_CAP2               = 97,
            PWM1_SYNC0              = 98,
            PWM1_SYNC1              = 99,
            PWM1_SYNC2              = 100,
            PWM1_F0                 = 101,
            PWM1_F1                 = 102,
            PWM1_F2                 = 103,
            PWM1_CAP0               = 104,
            PWM1_CAP1               = 105,
            PWM1_CAP2               = 106,
            EMAC_MDI                = 107,
            EMAC_COL                = 108,
            EMAC_CRS                = 109,
            USB_FS_IDDIG            = 110,
            USB_FS_AVALID           = 111,
            USB_FS_SRP_BVALID       = 112,
            USB_FS_VBUSVALID        = 113,
            USB_SRP_SESSEND         = 114,
            ULPI_CLK                = 117,
            USB_HSPHY_REFCLK        = 118,
            SDHOST_CARD_DETECT_N_1  = 126,
            SDHOST_CARD_DETECT_N_2  = 127,
            SDHOST_CARD_INT_N_1     = 128,
            SDHOST_CARD_INT_N_2     = 129,
            SDHOST_CARD_WRITE_PRT_1 = 130,
            SDHOST_CARD_WRITE_PRT_2 = 131,
            SDHOST_DATA_STROBE_1    = 132,
            SDHOST_DATA_STROBE_2    = 133,
            I3C_MST_SCL             = 134,
            I3C_MST_SDA             = 135,
            I3C_SLV_SCL             = 136,
            I3C_SLV_SDA             = 137,
            USB_JTAG_TDO_BRIDGE     = 140,
            PCNT0_SIG_CH0           = 141,
            PCNT1_SIG_CH0           = 142,
            PCNT2_SIG_CH0           = 143,
            PCNT3_SIG_CH0           = 144,
            PCNT0_SIG_CH1           = 145,
            PCNT1_SIG_CH1           = 146,
            PCNT2_SIG_CH1           = 147,
            PCNT3_SIG_CH1           = 148,
            PCNT0_CTRL_CH0          = 149,
            PCNT1_CTRL_CH0          = 150,
            PCNT2_CTRL_CH0          = 151,
            PCNT3_CTRL_CH0          = 152,
            PCNT0_CTRL_CH1          = 153,
            PCNT1_CTRL_CH1          = 154,
            PCNT2_CTRL_CH1          = 155,
            PCNT3_CTRL_CH1          = 156,
            CAM_PCLK                = 158,
            CAM_H_ENABLE            = 159,
            CAM_H_SYNC              = 160,
            CAM_V_SYNC              = 161,
            EMAC_RXDV               = 178,
            EMAC_RXD0               = 179,
            EMAC_RXD1               = 180,
            EMAC_RXD2               = 181,
            EMAC_RXD3               = 182,
            EMAC_RXER               = 183,
            EMAC_RX_CLK             = 184,
            EMAC_TX_CLK             = 185,
            PARL_RX_CLK             = 186,
            PARL_TX_CLK             = 187,
            PARL_RX_DATA0           = 188,
            PARL_RX_DATA1           = 189,
            PARL_RX_DATA2           = 190,
            PARL_RX_DATA3           = 191,
            PARL_RX_DATA4           = 192,
            PARL_RX_DATA5           = 193,
            PARL_RX_DATA6           = 194,
            PARL_RX_DATA7           = 195,
            PARL_RX_DATA8           = 196,
            PARL_RX_DATA9           = 197,
            PARL_RX_DATA10          = 198,
            PARL_RX_DATA11          = 199,
            PARL_RX_DATA12          = 200,
            PARL_RX_DATA13          = 201,
            PARL_RX_DATA14          = 202,
            PARL_RX_DATA15          = 203,
            CPU_GPIO_0              = 214,
            CPU_GPIO_1              = 215,
            CPU_GPIO_2              = 216,
            CPU_GPIO_3              = 217,
            CPU_GPIO_4              = 218,
            CPU_GPIO_5              = 219,
            CPU_GPIO_6              = 220,
            CPU_GPIO_7              = 221,
            CPU_GPIO_8              = 222,
            CPU_GPIO_9              = 223,
            CPU_GPIO_10             = 224,
            CPU_GPIO_11             = 225,
            CPU_GPIO_12             = 226,
            CPU_GPIO_13             = 227,
            CPU_GPIO_14             = 228,
            CPU_GPIO_15             = 229,
            RMT_SIG_0               = 246,
            RMT_SIG_1               = 247,
            RMT_SIG_2               = 248,
            RMT_SIG_3               = 249,
            MTCK,
            MTDI,
            MTMS,
            MTDO,
            SD1_DATA0,
            SD1_DATA1,
            SD1_DATA2,
            SD1_DATA3,
            SD1_CLK,
            SD1_CMD,
            SD1_DATA4,
            SD1_DATA5,
            SD1_DATA6,
            SD1_DATA7,
            EMAC_RMII_CLK,
            REF_50M_CLK,
            BIST,
            DBG_PSRAM_CK,
            DBG_PSRAM_CS,
            DBG_PSRAM_D,
            DBG_PSRAM_Q,
            DBG_PSRAM_WP,
            DBG_PSRAM_HOLD,
            DBG_PSRAM_DQ4,
            DBG_PSRAM_DQ5,
            DBG_PSRAM_DQ6,
            DBG_PSRAM_DQ7,
            DBG_PSRAM_DQS_0,
            DBG_PSRAM_DQ8,
            DBG_PSRAM_DQ9,
            DBG_PSRAM_DQ10,
            DBG_PSRAM_DQ11,
            DBG_PSRAM_DQ12,
            DBG_PSRAM_DQ13,
            DBG_PSRAM_DQ14,
            DBG_PSRAM_DQ15,
            DBG_PSRAM_DQS_1,
            DBG_FLASH_CS,
            DBG_FLASH_Q,
            DBG_FLASH_WP,
            DBG_FLASH_HOLD,
            DBG_FLASH_CK,
            DBG_FLASH_D,
            SPI2_DQS,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            SDHOST_CCLK_OUT_2          = 0,
            SDHOST_CCMD_OUT_2          = 1,
            SDHOST_CDATA_OUT_20        = 2,
            SDHOST_CDATA_OUT_21        = 3,
            SDHOST_CDATA_OUT_22        = 4,
            SDHOST_CDATA_OUT_23        = 5,
            SDHOST_CDATA_OUT_24        = 6,
            SDHOST_CDATA_OUT_25        = 7,
            SDHOST_CDATA_OUT_26        = 8,
            SDHOST_CDATA_OUT_27        = 9,
            UART0_TXD                  = 10,
            UART0_RTS                  = 11,
            UART0_DTR                  = 12,
            UART1_TXD                  = 13,
            UART1_RTS                  = 14,
            UART1_DTR                  = 15,
            UART2_TXD                  = 16,
            UART2_RTS                  = 17,
            UART2_DTR                  = 18,
            UART3_TXD                  = 19,
            UART3_RTS                  = 20,
            UART3_DTR                  = 21,
            UART4_TXD                  = 22,
            UART4_RTS                  = 23,
            UART4_DTR                  = 24,
            I2S0_O_BCK                 = 25,
            I2S0_MCLK                  = 26,
            I2S0_O_WS                  = 27,
            I2S0_O_SD                  = 28,
            I2S0_I_BCK                 = 29,
            I2S0_I_WS                  = 30,
            I2S1_O_BCK                 = 31,
            I2S1_MCLK                  = 32,
            I2S1_O_WS                  = 33,
            I2S1_O_SD                  = 34,
            I2S1_I_BCK                 = 35,
            I2S1_I_WS                  = 36,
            I2S2_O_BCK                 = 37,
            I2S2_MCLK                  = 38,
            I2S2_O_WS                  = 39,
            I2S2_O_SD                  = 40,
            I2S2_I_BCK                 = 41,
            I2S2_I_WS                  = 42,
            I2S0_O_SD1                 = 43,
            SPI2_DQS                   = 44,
            SPI3_CS2                   = 45,
            SPI3_CS1                   = 46,
            SPI3_CK                    = 47,
            SPI3_Q                     = 48,
            SPI3_D                     = 49,
            SPI3_HOLD                  = 50,
            SPI3_WP                    = 51,
            SPI3_CS                    = 52,
            SPI2_CK                    = 53,
            SPI2_Q                     = 54,
            SPI2_D                     = 55,
            SPI2_HOLD                  = 56,
            SPI2_WP                    = 57,
            SPI2_IO4                   = 58,
            SPI2_IO5                   = 59,
            SPI2_IO6                   = 60,
            SPI2_IO7                   = 61,
            SPI2_CS                    = 62,
            SPI2_CS1                   = 63,
            SPI2_CS2                   = 64,
            SPI2_CS3                   = 65,
            SPI2_CS4                   = 66,
            SPI2_CS5                   = 67,
            I2C0_SCL                   = 68,
            I2C0_SDA                   = 69,
            I2C1_SCL                   = 70,
            I2C1_SDA                   = 71,
            GPIO_SD0                   = 72,
            GPIO_SD1                   = 73,
            GPIO_SD2                   = 74,
            GPIO_SD3                   = 75,
            GPIO_SD4                   = 76,
            GPIO_SD5                   = 77,
            GPIO_SD6                   = 78,
            GPIO_SD7                   = 79,
            TWAI0_TX                   = 80,
            TWAI0_BUS_OFF_ON           = 81,
            TWAI0_CLKOUT               = 82,
            TWAI1_TX                   = 83,
            TWAI1_BUS_OFF_ON           = 84,
            TWAI1_CLKOUT               = 85,
            TWAI2_TX                   = 86,
            TWAI2_BUS_OFF_ON           = 87,
            TWAI2_CLKOUT               = 88,
            PWM0_CH0_A                 = 89,
            PWM0_CH0_B                 = 90,
            PWM0_CH1_A                 = 91,
            PWM0_CH1_B                 = 92,
            PWM0_CH2_A                 = 93,
            PWM0_CH2_B                 = 94,
            PWM1_CH0_A                 = 95,
            PWM1_CH0_B                 = 96,
            PWM1_CH1_A                 = 97,
            PWM1_CH1_B                 = 98,
            PWM1_CH2_A                 = 99,
            PWM1_CH2_B                 = 100,
            TWAI0_STANDBY              = 105,
            TWAI1_STANDBY              = 106,
            TWAI2_STANDBY              = 107,
            EMAC_MDC                   = 108,
            EMAC_MDO                   = 109,
            USB_SRP_DISCHRGVBUS        = 110,
            USB_OTG11_IDPULLUP         = 111,
            USB_OTG11_DPPULLDOWN       = 112,
            USB_OTG11_DMPULLDOWN       = 113,
            USB_OTG11_DRVVBUS          = 114,
            USB_SRP_CHRGVBUS           = 115,
            RNG_CHAIN_CLK              = 117,
            I3C_MST_SCL                = 134,
            I3C_MST_SDA                = 135,
            I3C_SLV_SCL                = 136,
            I3C_SLV_SDA                = 137,
            I3C_MST_SCL_PULLUP_EN      = 138,
            I3C_MST_SDA_PULLUP_EN      = 139,
            USB_JTAG_TDI_BRIDGE        = 140,
            USB_JTAG_TMS_BRIDGE        = 141,
            USB_JTAG_TCK_BRIDGE        = 142,
            USB_JTAG_TRST_BRIDGE       = 143,
            LCD_CS                     = 144,
            LCD_DC                     = 145,
            SD_RST_N_1                 = 146,
            SD_RST_N_2                 = 147,
            SDHOST_CCMD_OD_PULLUP_EN_N = 148,
            LCD_PCLK                   = 149,
            CAM_CLK                    = 150,
            LCD_H_ENABLE               = 151,
            LCD_H_SYNC                 = 152,
            LCD_V_SYNC                 = 153,
            EMAC_TXEN                  = 178,
            EMAC_TXD0                  = 179,
            EMAC_TXD1                  = 180,
            EMAC_TXD2                  = 181,
            EMAC_TXD3                  = 182,
            EMAC_TXER                  = 183,
            PARL_RX_CLK                = 186,
            PARL_TX_CLK                = 187,
            PARL_TX_DATA0              = 188,
            PARL_TX_DATA1              = 189,
            PARL_TX_DATA2              = 190,
            PARL_TX_DATA3              = 191,
            PARL_TX_DATA4              = 192,
            PARL_TX_DATA5              = 193,
            PARL_TX_DATA6              = 194,
            PARL_TX_DATA7              = 195,
            PARL_TX_DATA8              = 196,
            PARL_TX_DATA9              = 197,
            PARL_TX_DATA10             = 198,
            PARL_TX_DATA11             = 199,
            PARL_TX_DATA12             = 200,
            PARL_TX_DATA13             = 201,
            PARL_TX_DATA14             = 202,
            PARL_TX_DATA15             = 203,
            CONSTANT0                  = 212,
            CONSTANT1                  = 213,
            CPU_GPIO_0                 = 214,
            CPU_GPIO_1                 = 215,
            CPU_GPIO_2                 = 216,
            CPU_GPIO_3                 = 217,
            CPU_GPIO_4                 = 218,
            CPU_GPIO_5                 = 219,
            CPU_GPIO_6                 = 220,
            CPU_GPIO_7                 = 221,
            CPU_GPIO_8                 = 222,
            CPU_GPIO_9                 = 223,
            CPU_GPIO_10                = 224,
            CPU_GPIO_11                = 225,
            CPU_GPIO_12                = 226,
            CPU_GPIO_13                = 227,
            CPU_GPIO_14                = 228,
            CPU_GPIO_15                = 229,
            PARL_TX_CS                 = 242,
            EMAC_PTP_PPS               = 243,
            ANA_COMP0                  = 244,
            ANA_COMP1                  = 245,
            RMT_SIG_0                  = 246,
            RMT_SIG_1                  = 247,
            RMT_SIG_2                  = 248,
            RMT_SIG_3                  = 249,
            GPIO                       = 256,
            MTCK,
            MTDI,
            MTMS,
            MTDO,
            SD1_DATA0,
            SD1_DATA1,
            SD1_DATA2,
            SD1_DATA3,
            SD1_CLK,
            SD1_CMD,
            SD1_DATA4,
            SD1_DATA5,
            SD1_DATA6,
            SD1_DATA7,
            EMAC_RMII_CLK,
            REF_50M_CLK,
            BIST,
            DBG_PSRAM_CK,
            DBG_PSRAM_CS,
            DBG_PSRAM_D,
            DBG_PSRAM_Q,
            DBG_PSRAM_WP,
            DBG_PSRAM_HOLD,
            DBG_PSRAM_DQ4,
            DBG_PSRAM_DQ5,
            DBG_PSRAM_DQ6,
            DBG_PSRAM_DQ7,
            DBG_PSRAM_DQS_0,
            DBG_PSRAM_DQ8,
            DBG_PSRAM_DQ9,
            DBG_PSRAM_DQ10,
            DBG_PSRAM_DQ11,
            DBG_PSRAM_DQ12,
            DBG_PSRAM_DQ13,
            DBG_PSRAM_DQ14,
            DBG_PSRAM_DQ15,
            DBG_PSRAM_DQS_1,
            DBG_FLASH_CS,
            DBG_FLASH_Q,
            DBG_FLASH_WP,
            DBG_FLASH_HOLD,
            DBG_FLASH_CK,
            DBG_FLASH_D,
        }
    };
}
/// Defines the `LpFunction` enum.
///
/// The enum only contains the LP IO MUX functions that the chip implements. It is
/// empty on chips without an LP IO peripheral.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_functions {
    () => {
        /// LP IO MUX function of a pad.
        ///
        /// This is the low-power counterpart of `AlternateFunction`: it selects which function
        /// drives a pad while the pad belongs to the low-power domain.
        #[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpFunction {
            /// LP IO MUX function 0.
            _0 = 0,
            /// LP IO MUX function 1.
            _1 = 1,
        }
        impl LpFunction {
            /// The function that connects the pad to the LP GPIO peripheral.
            pub const LP_GPIO: Self = Self::_1;
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO {
            crate::peripherals::IO_MUX::regs().gpio(gpio_num as usize)
        }
    };
}