esp_metadata_generated/

_generated_esp32s3.rs

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32s3"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32-S3"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32s3"
    };
    ("arch") => {
        "xtensa"
    };
    ("cores") => {
        2
    };
    ("cores", str) => {
        stringify!(2)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf"
    };
    ("gpio.version") => {
        2
    };
    ("gpio.version", str) => {
        stringify!(2)
    };
    ("gpio.has_input_sync") => {
        true
    };
    ("gpio.gpio_function") => {
        1
    };
    ("gpio.gpio_function", str) => {
        stringify!(1)
    };
    ("gpio.constant_0_input") => {
        60
    };
    ("gpio.constant_0_input", str) => {
        stringify!(60)
    };
    ("gpio.constant_1_input") => {
        56
    };
    ("gpio.constant_1_input", str) => {
        stringify!(56)
    };
    ("gpio.remap_iomux_pin_registers") => {
        false
    };
    ("gpio.func_in_sel_offset") => {
        0
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(0)
    };
    ("gpio.need_soft_isolate_during_pd") => {
        false
    };
    ("gpio.has_bank_1") => {
        true
    };
    ("gpio.input_signal_max") => {
        255
    };
    ("gpio.input_signal_max", str) => {
        stringify!(255)
    };
    ("gpio.output_signal_max") => {
        256
    };
    ("gpio.output_signal_max", str) => {
        stringify!(256)
    };
    ("dedicated_gpio.version") => {
        "esp32s3"
    };
    ("dedicated_gpio.needs_initialization") => {
        true
    };
    ("dedicated_gpio.channel_count") => {
        8
    };
    ("dedicated_gpio.channel_count", str) => {
        stringify!(8)
    };
    ("lp_io.version") => {
        "v2"
    };
    ("lp_io.has_gpio_matrix") => {
        false
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.version") => {
        1
    };
    ("uart.version", str) => {
        stringify!(1)
    };
    ("uart.peripheral_controls_mem_clk") => {
        false
    };
    ("uart.has_sclk_divider") => {
        true
    };
    ("uart.has_sclk_enable") => {
        true
    };
    ("uhci.combined_uart_selector_field") => {
        false
    };
    ("i2c_master.version") => {
        3
    };
    ("i2c_master.version", str) => {
        stringify!(3)
    };
    ("i2c_master.has_fsm_timeouts") => {
        true
    };
    ("i2c_master.has_hw_bus_clear") => {
        false
    };
    ("i2c_master.has_bus_timeout_enable") => {
        true
    };
    ("i2c_master.separate_filter_config_registers") => {
        false
    };
    ("i2c_master.can_estimate_nack_reason") => {
        true
    };
    ("i2c_master.has_conf_update") => {
        true
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        false
    };
    ("i2c_master.has_arbitration_en") => {
        true
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        true
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        true
    };
    ("i2c_master.has_pd_en") => {
        true
    };
    ("i2c_master.max_bus_timeout") => {
        31
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(31)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        32
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(32)
    };
    ("lp_i2c_master.version") => {
        "rtc_i2c"
    };
    ("spi_master.version") => {
        3
    };
    ("spi_master.version", str) => {
        stringify!(3)
    };
    ("spi_master.fifo_size") => {
        64
    };
    ("spi_master.fifo_size", str) => {
        stringify!(64)
    };
    ("spi_master.bit_order_is_bool") => {
        false
    };
    ("spi_master.has_octal") => {
        true
    };
    ("spi_master.has_app_interrupts") => {
        true
    };
    ("spi_master.has_dma_segmented_transfer") => {
        true
    };
    ("spi_master.has_clk_pre_div") => {
        false
    };
    ("spi_master.dma_can_access_flash") => {
        false
    };
    ("i2s.version") => {
        2
    };
    ("i2s.version", str) => {
        stringify!(2)
    };
    ("i2s.mclk_divider_bit_width") => {
        9
    };
    ("i2s.mclk_divider_bit_width", str) => {
        stringify!(9)
    };
    ("i2s.max_ws_width") => {
        128
    };
    ("i2s.max_ws_width", str) => {
        stringify!(128)
    };
    ("i2s.clock_configured_by_pcr") => {
        false
    };
    ("i2s.clock_configured_by_hp_sys_clkrst") => {
        false
    };
    ("i2s.supports_pdm_rx_hp_filter") => {
        false
    };
    ("i2s.supports_pdm_tx") => {
        true
    };
    ("i2s.supports_pdm_rx") => {
        true
    };
    ("i2s.supports_pcm2pdm") => {
        true
    };
    ("i2s.supports_pdm2pcm") => {
        true
    };
    ("rmt.ram_start") => {
        1610704896
    };
    ("rmt.ram_start", str) => {
        stringify!(1610704896)
    };
    ("rmt.channel_ram_size") => {
        48
    };
    ("rmt.channel_ram_size", str) => {
        stringify!(48)
    };
    ("rmt.has_tx_immediate_stop") => {
        true
    };
    ("rmt.has_tx_loop_count") => {
        true
    };
    ("rmt.has_tx_loop_auto_stop") => {
        true
    };
    ("rmt.has_tx_carrier_data_only") => {
        true
    };
    ("rmt.has_tx_sync") => {
        true
    };
    ("rmt.has_rx_wrap") => {
        true
    };
    ("rmt.has_rx_demodulation") => {
        true
    };
    ("rmt.has_per_channel_clock") => {
        false
    };
    ("sdmmc.delay_phase_num") => {
        4
    };
    ("sdmmc.delay_phase_num", str) => {
        stringify!(4)
    };
    ("sdmmc.has_iomux") => {
        false
    };
    ("sdmmc.has_gpio_matrix") => {
        true
    };
    ("sdmmc.psram_dma") => {
        false
    };
    ("sdmmc.uhs") => {
        false
    };
    ("usb_otg.fifo_depth_words") => {
        256
    };
    ("usb_otg.fifo_depth_words", str) => {
        stringify!(256)
    };
    ("bt.controller") => {
        "btdm"
    };
    ("wifi.has_wifi6") => {
        false
    };
    ("wifi.mac_version") => {
        1
    };
    ("wifi.mac_version", str) => {
        stringify!(1)
    };
    ("wifi.has_5g") => {
        false
    };
    ("wifi.csi_supported") => {
        true
    };
    ("wifi.has_nan") => {
        false
    };
    ("wifi.has_ftm") => {
        true
    };
    ("phy.combo_module") => {
        true
    };
    ("phy.backed_up_digital_register_count") => {
        21
    };
    ("phy.backed_up_digital_register_count", str) => {
        stringify!(21)
    };
    ("rgb_display.output_lines") => {
        16
    };
    ("rgb_display.output_lines", str) => {
        stringify!(16)
    };
    ("adc.controller") => {
        "rtc"
    };
    ("adc.line_calibration") => {
        true
    };
    ("adc.curve_calibration") => {
        true
    };
    ("adc.basic_calibration") => {
        true
    };
    ("adc.calibration_v1_scheme_supported") => {
        true
    };
    ("adc.channel_compensation") => {
        false
    };
    ("adc.pcr_clock") => {
        false
    };
    ("adc.pcr_sar_clk_div") => {
        false
    };
    ("adc.sar_power_override") => {
        false
    };
    ("ledc.version") => {
        2
    };
    ("ledc.version", str) => {
        stringify!(2)
    };
    ("ledc.channel_count") => {
        8
    };
    ("ledc.channel_count", str) => {
        stringify!(8)
    };
    ("sdm.channel_count") => {
        8
    };
    ("sdm.channel_count", str) => {
        stringify!(8)
    };
    ("timergroup.timg_has_timer1") => {
        true
    };
    ("timergroup.timg_has_divcnt_rst") => {
        false
    };
    ("timergroup.wdt_has_conf_update") => {
        false
    };
    ("aes.has_split_text_registers") => {
        true
    };
    ("aes.endianness_configurable") => {
        false
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rng.is_lp_sys") => {
        false
    };
    ("rsa.version") => {
        2
    };
    ("rsa.version", str) => {
        stringify!(2)
    };
    ("rsa.size_increment") => {
        32
    };
    ("rsa.size_increment", str) => {
        stringify!(32)
    };
    ("rsa.memory_size_bytes") => {
        512
    };
    ("rsa.memory_size_bytes", str) => {
        stringify!(512)
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("sleep.rejectable_mask") => {
        11583
    };
    ("sleep.ext1_version") => {
        1
    };
    ("sleep.ext1_version", str) => {
        stringify!(1)
    };
    ("sleep.pin_wakeup_version") => {
        1
    };
    ("sleep.pin_wakeup_version", str) => {
        stringify!(1)
    };
    ("sleep.deep_sleep_needs_gpio_isolation") => {
        true
    };
    ("sleep.cpu_retention_mem_size") => {
        8800
    };
    ("sleep.cpu_retention_mem_align") => {
        16
    };
    ("sleep.cpu_retention_mem_start") => {
        1070104576
    };
    ("sleep.cpu_retention_mem_end") => {
        1070530560
    };
    ("assist_debug.has_sp_monitor") => {
        false
    };
    ("assist_debug.has_region_monitor") => {
        true
    };
    ("dma.mem2mem_requires_peripheral") => {
        true
    };
    ("dma.ext_mem_configurable_block_size") => {
        true
    };
    ("dma.separate_in_out_interrupts") => {
        true
    };
    ("dma.gdma_version") => {
        1
    };
    ("dma.gdma_version", str) => {
        stringify!(1)
    };
    ("interrupts.status_registers") => {
        4
    };
    ("interrupts.status_registers", str) => {
        stringify!(4)
    };
    ("mmu.page_size") => {
        65536
    };
    ("mmu.page_size", str) => {
        stringify!(65536)
    };
    ("mmu.entry_num") => {
        384
    };
    ("mmu.entry_num", str) => {
        stringify!(384)
    };
    ("psram.octal_spi") => {
        true
    };
    ("psram.hex_spi") => {
        false
    };
    ("psram.extmem_origin") => {
        1006632960
    };
    ("psram.extmem_origin", str) => {
        stringify!(1006632960)
    };
    ("rom.has_crc_le") => {
        true
    };
    ("rom.has_crc_be") => {
        true
    };
    ("rom.has_md5_bsd") => {
        true
    };
    ("rom.has_md5_mbedtls") => {
        false
    };
    ("soc.cpu_has_branch_predictor") => {
        false
    };
    ("soc.cpu_has_csr_pc") => {
        false
    };
    ("soc.cpu_has_zcmp_workaround") => {
        false
    };
    ("soc.multi_core_enabled") => {
        true
    };
    ("soc.internal_memory_cached") => {
        false
    };
    ("soc.has_swd_watchdog") => {
        true
    };
    ("soc.cpu_mcause_mask") => {
        0
    };
    ("soc.cpu_mcause_mask", str) => {
        stringify!(0)
    };
    ("soc.cpu_pmp_granularity") => {
        4
    };
    ("soc.cpu_pmp_granularity", str) => {
        stringify!(4)
    };
    ("clock_tree.system_pre_div_in") => {
        [crate ::soc::clocks::SystemPreDivInConfig::Xtal, crate
        ::soc::clocks::SystemPreDivInConfig::RcFast]
    };
    ("clock_tree.system_pre_div.divisor") => {
        (0, 1023)
    };
    ("clock_tree.cpu_clk") => {
        [crate ::soc::clocks::CpuClkConfig::Xtal, crate
        ::soc::clocks::CpuClkConfig::RcFast, crate ::soc::clocks::CpuClkConfig::Pll]
    };
    ("clock_tree.apb_clk") => {
        [crate ::soc::clocks::ApbClkConfig::Pll, crate ::soc::clocks::ApbClkConfig::Cpu]
    };
    ("clock_tree.crypto_pwm_clk") => {
        [crate ::soc::clocks::CryptoPwmClkConfig::Pll, crate
        ::soc::clocks::CryptoPwmClkConfig::Cpu]
    };
    ("clock_tree.rc_fast_clk_div_n.divisor") => {
        (0, 3)
    };
    ("clock_tree.rtc_slow_clk") => {
        [#[cfg(use_xtal32k)] crate ::soc::clocks::RtcSlowClkConfig::Xtal32k, crate
        ::soc::clocks::RtcSlowClkConfig::RcSlow, crate
        ::soc::clocks::RtcSlowClkConfig::RcFast]
    };
    ("clock_tree.ble_lp_clk") => {
        [crate ::soc::clocks::BleLpClkConfig::Xtal, crate
        ::soc::clocks::BleLpClkConfig::RtcSlow]
    };
    ("clock_tree.rtc_fast_clk") => {
        [crate ::soc::clocks::RtcFastClkConfig::Xtal, crate
        ::soc::clocks::RtcFastClkConfig::Rc]
    };
    ("clock_tree.low_power_clk") => {
        [crate ::soc::clocks::LowPowerClkConfig::Xtal, crate
        ::soc::clocks::LowPowerClkConfig::RcFast, #[cfg(use_xtal32k)] crate
        ::soc::clocks::LowPowerClkConfig::Xtal32k, crate
        ::soc::clocks::LowPowerClkConfig::RtcSlow]
    };
    ("clock_tree.timg_calibration_clock") => {
        [crate ::soc::clocks::TimgCalibrationClockConfig::RcSlowClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcFastDivClk, #[cfg(use_xtal32k)]
        crate ::soc::clocks::TimgCalibrationClockConfig::Xtal32kClk]
    };
    ("clock_tree.timg.function_clock") => {
        [crate ::soc::clocks::TimgFunctionClockConfig::XtalClk, crate
        ::soc::clocks::TimgFunctionClockConfig::ApbClk]
    };
    ("clock_tree.rmt.sclk") => {
        [crate ::soc::clocks::RmtSclkConfig::ApbClk, crate
        ::soc::clocks::RmtSclkConfig::RcFastClk, crate
        ::soc::clocks::RmtSclkConfig::XtalClk]
    };
    ("clock_tree.uart.function_clock.sclk") => {
        [crate ::soc::clocks::UartFunctionClockSclk::Apb, crate
        ::soc::clocks::UartFunctionClockSclk::RcFast, crate
        ::soc::clocks::UartFunctionClockSclk::Xtal]
    };
    ("clock_tree.uart.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 4095)
    };
    ("clock_tree.i2c.function_clock.sclk") => {
        [crate ::soc::clocks::I2cFunctionClockSclk::Xtal, crate
        ::soc::clocks::I2cFunctionClockSclk::RcFast]
    };
    ("clock_tree.i2c.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.lcd_cam.lcd_clock.sclk") => {
        [crate ::soc::clocks::LcdCamLcdClockSclk::XtalClk, crate
        ::soc::clocks::LcdCamLcdClockSclk::PllD2, crate
        ::soc::clocks::LcdCamLcdClockSclk::Pll160m]
    };
    ("clock_tree.lcd_cam.lcd_clock.div_num") => {
        (2, 256)
    };
    ("clock_tree.lcd_cam.lcd_clock.div_a") => {
        (1, 63)
    };
    ("clock_tree.lcd_cam.lcd_clock.div_b") => {
        (0, 63)
    };
    ("clock_tree.lcd_cam.cam_clock.sclk") => {
        [crate ::soc::clocks::LcdCamCamClockSclk::XtalClk, crate
        ::soc::clocks::LcdCamCamClockSclk::PllD2, crate
        ::soc::clocks::LcdCamCamClockSclk::Pll160m]
    };
    ("clock_tree.lcd_cam.cam_clock.div_num") => {
        (2, 256)
    };
    ("clock_tree.lcd_cam.cam_clock.div_a") => {
        (1, 63)
    };
    ("clock_tree.lcd_cam.cam_clock.div_b") => {
        (0, 63)
    };
    ("clock_tree.spi.function_clock") => {
        [crate ::soc::clocks::SpiFunctionClockConfig::Xtal, crate
        ::soc::clocks::SpiFunctionClockConfig::Apb]
    };
    ("clock_tree.i2s.tx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate ::soc::clocks::I2sClkSclk::PllD2,
        crate ::soc::clocks::I2sClkSclk::Pll160m]
    };
    ("clock_tree.i2s.tx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.tx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.tx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.rx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate ::soc::clocks::I2sClkSclk::PllD2,
        crate ::soc::clocks::I2sClkSclk::Pll160m]
    };
    ("clock_tree.i2s.rx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.rx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.rx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.mclk_out") => {
        [crate ::soc::clocks::I2sMclkOutConfig::Tx, crate
        ::soc::clocks::I2sMclkOutConfig::Rx]
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dedicated_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dedicated_gpio { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_dedicated_gpio!((0));
        _for_each_inner_dedicated_gpio!((1)); _for_each_inner_dedicated_gpio!((2));
        _for_each_inner_dedicated_gpio!((3)); _for_each_inner_dedicated_gpio!((4));
        _for_each_inner_dedicated_gpio!((5)); _for_each_inner_dedicated_gpio!((6));
        _for_each_inner_dedicated_gpio!((7)); _for_each_inner_dedicated_gpio!((0, 0,
        PRO_ALONEGPIO0)); _for_each_inner_dedicated_gpio!((0, 1, PRO_ALONEGPIO1));
        _for_each_inner_dedicated_gpio!((0, 2, PRO_ALONEGPIO2));
        _for_each_inner_dedicated_gpio!((0, 3, PRO_ALONEGPIO3));
        _for_each_inner_dedicated_gpio!((0, 4, PRO_ALONEGPIO4));
        _for_each_inner_dedicated_gpio!((0, 5, PRO_ALONEGPIO5));
        _for_each_inner_dedicated_gpio!((0, 6, PRO_ALONEGPIO6));
        _for_each_inner_dedicated_gpio!((0, 7, PRO_ALONEGPIO7));
        _for_each_inner_dedicated_gpio!((1, 0, CORE1_GPIO0));
        _for_each_inner_dedicated_gpio!((1, 1, CORE1_GPIO1));
        _for_each_inner_dedicated_gpio!((1, 2, CORE1_GPIO2));
        _for_each_inner_dedicated_gpio!((1, 3, CORE1_GPIO3));
        _for_each_inner_dedicated_gpio!((1, 4, CORE1_GPIO4));
        _for_each_inner_dedicated_gpio!((1, 5, CORE1_GPIO5));
        _for_each_inner_dedicated_gpio!((1, 6, CORE1_GPIO6));
        _for_each_inner_dedicated_gpio!((1, 7, CORE1_GPIO7));
        _for_each_inner_dedicated_gpio!((channels(0), (1), (2), (3), (4), (5), (6),
        (7))); _for_each_inner_dedicated_gpio!((signals(0, 0, PRO_ALONEGPIO0), (0, 1,
        PRO_ALONEGPIO1), (0, 2, PRO_ALONEGPIO2), (0, 3, PRO_ALONEGPIO3), (0, 4,
        PRO_ALONEGPIO4), (0, 5, PRO_ALONEGPIO5), (0, 6, PRO_ALONEGPIO6), (0, 7,
        PRO_ALONEGPIO7), (1, 0, CORE1_GPIO0), (1, 1, CORE1_GPIO1), (1, 2, CORE1_GPIO2),
        (1, 3, CORE1_GPIO3), (1, 4, CORE1_GPIO4), (1, 5, CORE1_GPIO5), (1, 6,
        CORE1_GPIO6), (1, 7, CORE1_GPIO7)));
    };
}
/// Defines the `LpInputSignal` and `LpOutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_io_signals {
    () => {};
}
/// This macro can be used to generate code for each channel of the RMT peripheral.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has three options for its "Individual matcher" case:
///
/// - `all`: `($num:literal)`
/// - `tx`: `($num:literal, $idx:literal)`
/// - `rx`: `($num:literal, $idx:literal)`
///
/// Macro fragments:
///
/// - `$num`: number of the channel, e.g. `0`
/// - `$idx`: index of the channel among channels of the same capability, e.g. `0`
///
/// Example data:
///
/// - `all`: `(0)`
/// - `tx`: `(1, 1)`
/// - `rx`: `(2, 0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rmt_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rmt_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_rmt_channel!((0)); _for_each_inner_rmt_channel!((1));
        _for_each_inner_rmt_channel!((2)); _for_each_inner_rmt_channel!((3));
        _for_each_inner_rmt_channel!((4)); _for_each_inner_rmt_channel!((5));
        _for_each_inner_rmt_channel!((6)); _for_each_inner_rmt_channel!((7));
        _for_each_inner_rmt_channel!((0, 0)); _for_each_inner_rmt_channel!((1, 1));
        _for_each_inner_rmt_channel!((2, 2)); _for_each_inner_rmt_channel!((3, 3));
        _for_each_inner_rmt_channel!((4, 0)); _for_each_inner_rmt_channel!((5, 1));
        _for_each_inner_rmt_channel!((6, 2)); _for_each_inner_rmt_channel!((7, 3));
        _for_each_inner_rmt_channel!((all(0), (1), (2), (3), (4), (5), (6), (7)));
        _for_each_inner_rmt_channel!((tx(0, 0), (1, 1), (2, 2), (3, 3)));
        _for_each_inner_rmt_channel!((rx(4, 0), (5, 1), (6, 2), (7, 3)));
    };
}
/// This macro can be used to generate code for each slot of the SDMMC/SDIO host driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($slot:ident, $idx:literal, $iomux:literal, [$($clk:ident)?]
/// [$($cmd_in:ident)?] [$($cmd_out:ident)?] [$($data_in:ident),*] [$($data_out:ident),*]
/// [$($cd:ident)?] [$($wp:ident)?] [$($card_int:ident)?] [$($data_strobe:ident)?]
/// [$($rst:ident)?])`
///
/// Macro fragments:
///
/// - `$slot`: the name of the slot (`slot0`, `slot1`).
/// - `$idx`: the zero-based slot index.
/// - `$iomux`: `true` if the slot's clock/command/data signals are IO_MUX-routed.
/// - `$clk`, `$cmd_in`, `$cmd_out`, `$data_in`, `$data_out`: GPIO-matrix bus signal names (absent
///   for IO_MUX-routed slots).
/// - `$cd`, `$wp`, `$card_int`, `$data_strobe`, `$rst`: auxiliary signal names, each present only
///   when the slot routes that signal through the GPIO matrix.
///
/// Each optional signal is wrapped in brackets so the branch shape stays uniform: a set
/// signal appears as `[SIGNAL]`, an absent one as `[]`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdmmc {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdmmc { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_sdmmc!((slot0, 0, false, [SDHOST_CCLK_OUT_1],
        [SDHOST_CCMD_IN_1], [SDHOST_CCMD_OUT_1], [SDHOST_CDATA_IN_10, SDHOST_CDATA_IN_11,
        SDHOST_CDATA_IN_12, SDHOST_CDATA_IN_13, SDHOST_CDATA_IN_14, SDHOST_CDATA_IN_15,
        SDHOST_CDATA_IN_16, SDHOST_CDATA_IN_17], [SDHOST_CDATA_OUT_10,
        SDHOST_CDATA_OUT_11, SDHOST_CDATA_OUT_12, SDHOST_CDATA_OUT_13,
        SDHOST_CDATA_OUT_14, SDHOST_CDATA_OUT_15, SDHOST_CDATA_OUT_16,
        SDHOST_CDATA_OUT_17], [SDHOST_CARD_DETECT_N_1], [SDHOST_CARD_WRITE_PRT_1],
        [SDHOST_CARD_INT_N_1], [SDHOST_DATA_STROBE_1], [SDHOST_RST_N_1]));
        _for_each_inner_sdmmc!((slot1, 1, false, [SDHOST_CCLK_OUT_2], [SDHOST_CCMD_IN_2],
        [SDHOST_CCMD_OUT_2], [SDHOST_CDATA_IN_20, SDHOST_CDATA_IN_21, SDHOST_CDATA_IN_22,
        SDHOST_CDATA_IN_23, SDHOST_CDATA_IN_24, SDHOST_CDATA_IN_25, SDHOST_CDATA_IN_26,
        SDHOST_CDATA_IN_27], [SDHOST_CDATA_OUT_20, SDHOST_CDATA_OUT_21,
        SDHOST_CDATA_OUT_22, SDHOST_CDATA_OUT_23, SDHOST_CDATA_OUT_24,
        SDHOST_CDATA_OUT_25, SDHOST_CDATA_OUT_26, SDHOST_CDATA_OUT_27],
        [SDHOST_CARD_DETECT_N_2], [SDHOST_CARD_WRITE_PRT_2], [SDHOST_CARD_INT_N_2],
        [SDHOST_DATA_STROBE_2], [SDHOST_RST_N_2])); _for_each_inner_sdmmc!((all(slot0, 0,
        false, [SDHOST_CCLK_OUT_1], [SDHOST_CCMD_IN_1], [SDHOST_CCMD_OUT_1],
        [SDHOST_CDATA_IN_10, SDHOST_CDATA_IN_11, SDHOST_CDATA_IN_12, SDHOST_CDATA_IN_13,
        SDHOST_CDATA_IN_14, SDHOST_CDATA_IN_15, SDHOST_CDATA_IN_16, SDHOST_CDATA_IN_17],
        [SDHOST_CDATA_OUT_10, SDHOST_CDATA_OUT_11, SDHOST_CDATA_OUT_12,
        SDHOST_CDATA_OUT_13, SDHOST_CDATA_OUT_14, SDHOST_CDATA_OUT_15,
        SDHOST_CDATA_OUT_16, SDHOST_CDATA_OUT_17], [SDHOST_CARD_DETECT_N_1],
        [SDHOST_CARD_WRITE_PRT_1], [SDHOST_CARD_INT_N_1], [SDHOST_DATA_STROBE_1],
        [SDHOST_RST_N_1]), (slot1, 1, false, [SDHOST_CCLK_OUT_2], [SDHOST_CCMD_IN_2],
        [SDHOST_CCMD_OUT_2], [SDHOST_CDATA_IN_20, SDHOST_CDATA_IN_21, SDHOST_CDATA_IN_22,
        SDHOST_CDATA_IN_23, SDHOST_CDATA_IN_24, SDHOST_CDATA_IN_25, SDHOST_CDATA_IN_26,
        SDHOST_CDATA_IN_27], [SDHOST_CDATA_OUT_20, SDHOST_CDATA_OUT_21,
        SDHOST_CDATA_OUT_22, SDHOST_CDATA_OUT_23, SDHOST_CDATA_OUT_24,
        SDHOST_CDATA_OUT_25, SDHOST_CDATA_OUT_26, SDHOST_CDATA_OUT_27],
        [SDHOST_CARD_DETECT_N_2], [SDHOST_CARD_WRITE_PRT_2], [SDHOST_CARD_INT_N_2],
        [SDHOST_DATA_STROBE_2], [SDHOST_RST_N_2])));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdm_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdm_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_sdm_channel!((0, SDM_CH0, SdmCh0, GPIO_SD0));
        _for_each_inner_sdm_channel!((1, SDM_CH1, SdmCh1, GPIO_SD1));
        _for_each_inner_sdm_channel!((2, SDM_CH2, SdmCh2, GPIO_SD2));
        _for_each_inner_sdm_channel!((3, SDM_CH3, SdmCh3, GPIO_SD3));
        _for_each_inner_sdm_channel!((4, SDM_CH4, SdmCh4, GPIO_SD4));
        _for_each_inner_sdm_channel!((5, SDM_CH5, SdmCh5, GPIO_SD5));
        _for_each_inner_sdm_channel!((6, SDM_CH6, SdmCh6, GPIO_SD6));
        _for_each_inner_sdm_channel!((7, SDM_CH7, SdmCh7, GPIO_SD7));
        _for_each_inner_sdm_channel!((channels(0, SDM_CH0, SdmCh0, GPIO_SD0), (1,
        SDM_CH1, SdmCh1, GPIO_SD1), (2, SDM_CH2, SdmCh2, GPIO_SD2), (3, SDM_CH3, SdmCh3,
        GPIO_SD3), (4, SDM_CH4, SdmCh4, GPIO_SD4), (5, SDM_CH5, SdmCh5, GPIO_SD5), (6,
        SDM_CH6, SdmCh6, GPIO_SD6), (7, SDM_CH7, SdmCh7, GPIO_SD7)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_aes_key_length {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_aes_key_length { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_aes_key_length!((128));
        _for_each_inner_aes_key_length!((256)); _for_each_inner_aes_key_length!((128, 0,
        4)); _for_each_inner_aes_key_length!((256, 2, 6));
        _for_each_inner_aes_key_length!((bits(128), (256)));
        _for_each_inner_aes_key_length!((modes(128, 0, 4), (256, 2, 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_exponentiation {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_exponentiation { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_exponentiation!((32));
        _for_each_inner_rsa_exponentiation!((64));
        _for_each_inner_rsa_exponentiation!((96));
        _for_each_inner_rsa_exponentiation!((128));
        _for_each_inner_rsa_exponentiation!((160));
        _for_each_inner_rsa_exponentiation!((192));
        _for_each_inner_rsa_exponentiation!((224));
        _for_each_inner_rsa_exponentiation!((256));
        _for_each_inner_rsa_exponentiation!((288));
        _for_each_inner_rsa_exponentiation!((320));
        _for_each_inner_rsa_exponentiation!((352));
        _for_each_inner_rsa_exponentiation!((384));
        _for_each_inner_rsa_exponentiation!((416));
        _for_each_inner_rsa_exponentiation!((448));
        _for_each_inner_rsa_exponentiation!((480));
        _for_each_inner_rsa_exponentiation!((512));
        _for_each_inner_rsa_exponentiation!((544));
        _for_each_inner_rsa_exponentiation!((576));
        _for_each_inner_rsa_exponentiation!((608));
        _for_each_inner_rsa_exponentiation!((640));
        _for_each_inner_rsa_exponentiation!((672));
        _for_each_inner_rsa_exponentiation!((704));
        _for_each_inner_rsa_exponentiation!((736));
        _for_each_inner_rsa_exponentiation!((768));
        _for_each_inner_rsa_exponentiation!((800));
        _for_each_inner_rsa_exponentiation!((832));
        _for_each_inner_rsa_exponentiation!((864));
        _for_each_inner_rsa_exponentiation!((896));
        _for_each_inner_rsa_exponentiation!((928));
        _for_each_inner_rsa_exponentiation!((960));
        _for_each_inner_rsa_exponentiation!((992));
        _for_each_inner_rsa_exponentiation!((1024));
        _for_each_inner_rsa_exponentiation!((1056));
        _for_each_inner_rsa_exponentiation!((1088));
        _for_each_inner_rsa_exponentiation!((1120));
        _for_each_inner_rsa_exponentiation!((1152));
        _for_each_inner_rsa_exponentiation!((1184));
        _for_each_inner_rsa_exponentiation!((1216));
        _for_each_inner_rsa_exponentiation!((1248));
        _for_each_inner_rsa_exponentiation!((1280));
        _for_each_inner_rsa_exponentiation!((1312));
        _for_each_inner_rsa_exponentiation!((1344));
        _for_each_inner_rsa_exponentiation!((1376));
        _for_each_inner_rsa_exponentiation!((1408));
        _for_each_inner_rsa_exponentiation!((1440));
        _for_each_inner_rsa_exponentiation!((1472));
        _for_each_inner_rsa_exponentiation!((1504));
        _for_each_inner_rsa_exponentiation!((1536));
        _for_each_inner_rsa_exponentiation!((1568));
        _for_each_inner_rsa_exponentiation!((1600));
        _for_each_inner_rsa_exponentiation!((1632));
        _for_each_inner_rsa_exponentiation!((1664));
        _for_each_inner_rsa_exponentiation!((1696));
        _for_each_inner_rsa_exponentiation!((1728));
        _for_each_inner_rsa_exponentiation!((1760));
        _for_each_inner_rsa_exponentiation!((1792));
        _for_each_inner_rsa_exponentiation!((1824));
        _for_each_inner_rsa_exponentiation!((1856));
        _for_each_inner_rsa_exponentiation!((1888));
        _for_each_inner_rsa_exponentiation!((1920));
        _for_each_inner_rsa_exponentiation!((1952));
        _for_each_inner_rsa_exponentiation!((1984));
        _for_each_inner_rsa_exponentiation!((2016));
        _for_each_inner_rsa_exponentiation!((2048));
        _for_each_inner_rsa_exponentiation!((2080));
        _for_each_inner_rsa_exponentiation!((2112));
        _for_each_inner_rsa_exponentiation!((2144));
        _for_each_inner_rsa_exponentiation!((2176));
        _for_each_inner_rsa_exponentiation!((2208));
        _for_each_inner_rsa_exponentiation!((2240));
        _for_each_inner_rsa_exponentiation!((2272));
        _for_each_inner_rsa_exponentiation!((2304));
        _for_each_inner_rsa_exponentiation!((2336));
        _for_each_inner_rsa_exponentiation!((2368));
        _for_each_inner_rsa_exponentiation!((2400));
        _for_each_inner_rsa_exponentiation!((2432));
        _for_each_inner_rsa_exponentiation!((2464));
        _for_each_inner_rsa_exponentiation!((2496));
        _for_each_inner_rsa_exponentiation!((2528));
        _for_each_inner_rsa_exponentiation!((2560));
        _for_each_inner_rsa_exponentiation!((2592));
        _for_each_inner_rsa_exponentiation!((2624));
        _for_each_inner_rsa_exponentiation!((2656));
        _for_each_inner_rsa_exponentiation!((2688));
        _for_each_inner_rsa_exponentiation!((2720));
        _for_each_inner_rsa_exponentiation!((2752));
        _for_each_inner_rsa_exponentiation!((2784));
        _for_each_inner_rsa_exponentiation!((2816));
        _for_each_inner_rsa_exponentiation!((2848));
        _for_each_inner_rsa_exponentiation!((2880));
        _for_each_inner_rsa_exponentiation!((2912));
        _for_each_inner_rsa_exponentiation!((2944));
        _for_each_inner_rsa_exponentiation!((2976));
        _for_each_inner_rsa_exponentiation!((3008));
        _for_each_inner_rsa_exponentiation!((3040));
        _for_each_inner_rsa_exponentiation!((3072));
        _for_each_inner_rsa_exponentiation!((3104));
        _for_each_inner_rsa_exponentiation!((3136));
        _for_each_inner_rsa_exponentiation!((3168));
        _for_each_inner_rsa_exponentiation!((3200));
        _for_each_inner_rsa_exponentiation!((3232));
        _for_each_inner_rsa_exponentiation!((3264));
        _for_each_inner_rsa_exponentiation!((3296));
        _for_each_inner_rsa_exponentiation!((3328));
        _for_each_inner_rsa_exponentiation!((3360));
        _for_each_inner_rsa_exponentiation!((3392));
        _for_each_inner_rsa_exponentiation!((3424));
        _for_each_inner_rsa_exponentiation!((3456));
        _for_each_inner_rsa_exponentiation!((3488));
        _for_each_inner_rsa_exponentiation!((3520));
        _for_each_inner_rsa_exponentiation!((3552));
        _for_each_inner_rsa_exponentiation!((3584));
        _for_each_inner_rsa_exponentiation!((3616));
        _for_each_inner_rsa_exponentiation!((3648));
        _for_each_inner_rsa_exponentiation!((3680));
        _for_each_inner_rsa_exponentiation!((3712));
        _for_each_inner_rsa_exponentiation!((3744));
        _for_each_inner_rsa_exponentiation!((3776));
        _for_each_inner_rsa_exponentiation!((3808));
        _for_each_inner_rsa_exponentiation!((3840));
        _for_each_inner_rsa_exponentiation!((3872));
        _for_each_inner_rsa_exponentiation!((3904));
        _for_each_inner_rsa_exponentiation!((3936));
        _for_each_inner_rsa_exponentiation!((3968));
        _for_each_inner_rsa_exponentiation!((4000));
        _for_each_inner_rsa_exponentiation!((4032));
        _for_each_inner_rsa_exponentiation!((4064));
        _for_each_inner_rsa_exponentiation!((4096));
        _for_each_inner_rsa_exponentiation!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536),
        (1568), (1600), (1632), (1664), (1696), (1728), (1760), (1792), (1824), (1856),
        (1888), (1920), (1952), (1984), (2016), (2048), (2080), (2112), (2144), (2176),
        (2208), (2240), (2272), (2304), (2336), (2368), (2400), (2432), (2464), (2496),
        (2528), (2560), (2592), (2624), (2656), (2688), (2720), (2752), (2784), (2816),
        (2848), (2880), (2912), (2944), (2976), (3008), (3040), (3072), (3104), (3136),
        (3168), (3200), (3232), (3264), (3296), (3328), (3360), (3392), (3424), (3456),
        (3488), (3520), (3552), (3584), (3616), (3648), (3680), (3712), (3744), (3776),
        (3808), (3840), (3872), (3904), (3936), (3968), (4000), (4032), (4064), (4096)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_multiplication {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_multiplication { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_multiplication!((32));
        _for_each_inner_rsa_multiplication!((64));
        _for_each_inner_rsa_multiplication!((96));
        _for_each_inner_rsa_multiplication!((128));
        _for_each_inner_rsa_multiplication!((160));
        _for_each_inner_rsa_multiplication!((192));
        _for_each_inner_rsa_multiplication!((224));
        _for_each_inner_rsa_multiplication!((256));
        _for_each_inner_rsa_multiplication!((288));
        _for_each_inner_rsa_multiplication!((320));
        _for_each_inner_rsa_multiplication!((352));
        _for_each_inner_rsa_multiplication!((384));
        _for_each_inner_rsa_multiplication!((416));
        _for_each_inner_rsa_multiplication!((448));
        _for_each_inner_rsa_multiplication!((480));
        _for_each_inner_rsa_multiplication!((512));
        _for_each_inner_rsa_multiplication!((544));
        _for_each_inner_rsa_multiplication!((576));
        _for_each_inner_rsa_multiplication!((608));
        _for_each_inner_rsa_multiplication!((640));
        _for_each_inner_rsa_multiplication!((672));
        _for_each_inner_rsa_multiplication!((704));
        _for_each_inner_rsa_multiplication!((736));
        _for_each_inner_rsa_multiplication!((768));
        _for_each_inner_rsa_multiplication!((800));
        _for_each_inner_rsa_multiplication!((832));
        _for_each_inner_rsa_multiplication!((864));
        _for_each_inner_rsa_multiplication!((896));
        _for_each_inner_rsa_multiplication!((928));
        _for_each_inner_rsa_multiplication!((960));
        _for_each_inner_rsa_multiplication!((992));
        _for_each_inner_rsa_multiplication!((1024));
        _for_each_inner_rsa_multiplication!((1056));
        _for_each_inner_rsa_multiplication!((1088));
        _for_each_inner_rsa_multiplication!((1120));
        _for_each_inner_rsa_multiplication!((1152));
        _for_each_inner_rsa_multiplication!((1184));
        _for_each_inner_rsa_multiplication!((1216));
        _for_each_inner_rsa_multiplication!((1248));
        _for_each_inner_rsa_multiplication!((1280));
        _for_each_inner_rsa_multiplication!((1312));
        _for_each_inner_rsa_multiplication!((1344));
        _for_each_inner_rsa_multiplication!((1376));
        _for_each_inner_rsa_multiplication!((1408));
        _for_each_inner_rsa_multiplication!((1440));
        _for_each_inner_rsa_multiplication!((1472));
        _for_each_inner_rsa_multiplication!((1504));
        _for_each_inner_rsa_multiplication!((1536));
        _for_each_inner_rsa_multiplication!((1568));
        _for_each_inner_rsa_multiplication!((1600));
        _for_each_inner_rsa_multiplication!((1632));
        _for_each_inner_rsa_multiplication!((1664));
        _for_each_inner_rsa_multiplication!((1696));
        _for_each_inner_rsa_multiplication!((1728));
        _for_each_inner_rsa_multiplication!((1760));
        _for_each_inner_rsa_multiplication!((1792));
        _for_each_inner_rsa_multiplication!((1824));
        _for_each_inner_rsa_multiplication!((1856));
        _for_each_inner_rsa_multiplication!((1888));
        _for_each_inner_rsa_multiplication!((1920));
        _for_each_inner_rsa_multiplication!((1952));
        _for_each_inner_rsa_multiplication!((1984));
        _for_each_inner_rsa_multiplication!((2016));
        _for_each_inner_rsa_multiplication!((2048));
        _for_each_inner_rsa_multiplication!((all(32), (64), (96), (128), (160), (192),
        (224), (256), (288), (320), (352), (384), (416), (448), (480), (512), (544),
        (576), (608), (640), (672), (704), (736), (768), (800), (832), (864), (896),
        (928), (960), (992), (1024), (1056), (1088), (1120), (1152), (1184), (1216),
        (1248), (1280), (1312), (1344), (1376), (1408), (1440), (1472), (1504), (1536),
        (1568), (1600), (1632), (1664), (1696), (1728), (1760), (1792), (1824), (1856),
        (1888), (1920), (1952), (1984), (2016), (2048)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha224, "SHA-224"(sizes : 64, 28, 8)
        (insecure_against : "length extension"), 1));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 2));
        _for_each_inner_sha_algorithm!((Sha384, "SHA-384"(sizes : 128, 48, 16)
        (insecure_against :), 3)); _for_each_inner_sha_algorithm!((Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 4));
        _for_each_inner_sha_algorithm!((Sha512_224, "SHA-512/224"(sizes : 128, 28, 16)
        (insecure_against :), 5)); _for_each_inner_sha_algorithm!((Sha512_256,
        "SHA-512/256"(sizes : 128, 32, 16) (insecure_against :), 6));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha224,
        "SHA-224"(sizes : 64, 28, 8) (insecure_against : "length extension"), 1),
        (Sha256, "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"),
        2), (Sha384, "SHA-384"(sizes : 128, 48, 16) (insecure_against :), 3), (Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 4),
        (Sha512_224, "SHA-512/224"(sizes : 128, 28, 16) (insecure_against :), 5),
        (Sha512_256, "SHA-512/256"(sizes : 128, 32, 16) (insecure_against :), 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_wakeup_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_wakeup_source { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_wakeup_source!((Ext0, 0));
        _for_each_inner_wakeup_source!((Ext1, 1)); _for_each_inner_wakeup_source!((Gpio,
        2)); _for_each_inner_wakeup_source!((Timer, 3));
        _for_each_inner_wakeup_source!((Sdio, 4)); _for_each_inner_wakeup_source!((Wifi,
        5)); _for_each_inner_wakeup_source!((Uart0, 6));
        _for_each_inner_wakeup_source!((Uart1, 7));
        _for_each_inner_wakeup_source!((Touch, 8)); _for_each_inner_wakeup_source!((Bt,
        10)); _for_each_inner_wakeup_source!((UlpRiscv, 11));
        _for_each_inner_wakeup_source!((UlpRiscvTrap, 13));
        _for_each_inner_wakeup_source!((all(Ext0, 0), (Ext1, 1), (Gpio, 2), (Timer, 3),
        (Sdio, 4), (Wifi, 5), (Uart0, 6), (Uart1, 7), (Touch, 8), (Bt, 10), (UlpRiscv,
        11), (UlpRiscvTrap, 13)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_engine!(("AHB_GDMA"));
        _for_each_inner_dma_engine!((all("AHB_GDMA")));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH1));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH2));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH3));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH4));
        _for_each_inner_dma_channel!(("AHB_GDMA", any_channel = AhbGdmaChannel));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0, 0, interrupt_in = DMA_IN_CH0,
        interrupt_out = DMA_OUT_CH0, compatible = [SPI2, SPI3, UHCI0, I2S0, I2S1,
        LCD_CAM, AES, SHA, APB_SARADC, RMT])); _for_each_inner_dma_channel!(("AHB_GDMA",
        DMA_CH1, 1, interrupt_in = DMA_IN_CH1, interrupt_out = DMA_OUT_CH1, compatible =
        [SPI2, SPI3, UHCI0, I2S0, I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH2, 2, interrupt_in = DMA_IN_CH2,
        interrupt_out = DMA_OUT_CH2, compatible = [SPI2, SPI3, UHCI0, I2S0, I2S1,
        LCD_CAM, AES, SHA, APB_SARADC, RMT])); _for_each_inner_dma_channel!(("AHB_GDMA",
        DMA_CH3, 3, interrupt_in = DMA_IN_CH3, interrupt_out = DMA_OUT_CH3, compatible =
        [SPI2, SPI3, UHCI0, I2S0, I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH4, 4, interrupt_in = DMA_IN_CH4,
        interrupt_out = DMA_OUT_CH4, compatible = [SPI2, SPI3, UHCI0, I2S0, I2S1,
        LCD_CAM, AES, SHA, APB_SARADC, RMT]));
        _for_each_inner_dma_channel!((names("AHB_GDMA", DMA_CH0), ("AHB_GDMA", DMA_CH1),
        ("AHB_GDMA", DMA_CH2), ("AHB_GDMA", DMA_CH3), ("AHB_GDMA", DMA_CH4)));
        _for_each_inner_dma_channel!((separate_any_type("AHB_GDMA", any_channel =
        AhbGdmaChannel))); _for_each_inner_dma_channel!((shared));
        _for_each_inner_dma_channel!((split("AHB_GDMA", DMA_CH0, 0, interrupt_in =
        DMA_IN_CH0, interrupt_out = DMA_OUT_CH0, compatible = [SPI2, SPI3, UHCI0, I2S0,
        I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]), ("AHB_GDMA", DMA_CH1, 1, interrupt_in
        = DMA_IN_CH1, interrupt_out = DMA_OUT_CH1, compatible = [SPI2, SPI3, UHCI0, I2S0,
        I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]), ("AHB_GDMA", DMA_CH2, 2, interrupt_in
        = DMA_IN_CH2, interrupt_out = DMA_OUT_CH2, compatible = [SPI2, SPI3, UHCI0, I2S0,
        I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]), ("AHB_GDMA", DMA_CH3, 3, interrupt_in
        = DMA_IN_CH3, interrupt_out = DMA_OUT_CH3, compatible = [SPI2, SPI3, UHCI0, I2S0,
        I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT]), ("AHB_GDMA", DMA_CH4, 4, interrupt_in
        = DMA_IN_CH4, interrupt_out = DMA_OUT_CH4, compatible = [SPI2, SPI3, UHCI0, I2S0,
        I2S1, LCD_CAM, AES, SHA, APB_SARADC, RMT])));
        _for_each_inner_dma_channel!((no_own_interrupt));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel_peri_pair {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel_peri_pair { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        DMA_CH0, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0,
        SPI3)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, AES));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, RMT));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, AES));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, RMT));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, AES));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, RMT));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, AES));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, RMT));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, SPI3));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, AES));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, RMT));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        SPI2)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel =
        AhbGdmaChannel, SPI3)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        any_channel = AhbGdmaChannel, UHCI0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        I2S0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel =
        AhbGdmaChannel, I2S1)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        any_channel = AhbGdmaChannel, LCD_CAM));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        AES)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel =
        AhbGdmaChannel, SHA)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        any_channel = AhbGdmaChannel, APB_SARADC));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        RMT)); _for_each_inner_dma_channel_peri_pair!((channels("AHB_GDMA", DMA_CH0,
        SPI2), ("AHB_GDMA", DMA_CH0, SPI3), ("AHB_GDMA", DMA_CH0, UHCI0), ("AHB_GDMA",
        DMA_CH0, I2S0), ("AHB_GDMA", DMA_CH0, I2S1), ("AHB_GDMA", DMA_CH0, LCD_CAM),
        ("AHB_GDMA", DMA_CH0, AES), ("AHB_GDMA", DMA_CH0, SHA), ("AHB_GDMA", DMA_CH0,
        APB_SARADC), ("AHB_GDMA", DMA_CH0, RMT), ("AHB_GDMA", DMA_CH1, SPI2),
        ("AHB_GDMA", DMA_CH1, SPI3), ("AHB_GDMA", DMA_CH1, UHCI0), ("AHB_GDMA", DMA_CH1,
        I2S0), ("AHB_GDMA", DMA_CH1, I2S1), ("AHB_GDMA", DMA_CH1, LCD_CAM), ("AHB_GDMA",
        DMA_CH1, AES), ("AHB_GDMA", DMA_CH1, SHA), ("AHB_GDMA", DMA_CH1, APB_SARADC),
        ("AHB_GDMA", DMA_CH1, RMT), ("AHB_GDMA", DMA_CH2, SPI2), ("AHB_GDMA", DMA_CH2,
        SPI3), ("AHB_GDMA", DMA_CH2, UHCI0), ("AHB_GDMA", DMA_CH2, I2S0), ("AHB_GDMA",
        DMA_CH2, I2S1), ("AHB_GDMA", DMA_CH2, LCD_CAM), ("AHB_GDMA", DMA_CH2, AES),
        ("AHB_GDMA", DMA_CH2, SHA), ("AHB_GDMA", DMA_CH2, APB_SARADC), ("AHB_GDMA",
        DMA_CH2, RMT), ("AHB_GDMA", DMA_CH3, SPI2), ("AHB_GDMA", DMA_CH3, SPI3),
        ("AHB_GDMA", DMA_CH3, UHCI0), ("AHB_GDMA", DMA_CH3, I2S0), ("AHB_GDMA", DMA_CH3,
        I2S1), ("AHB_GDMA", DMA_CH3, LCD_CAM), ("AHB_GDMA", DMA_CH3, AES), ("AHB_GDMA",
        DMA_CH3, SHA), ("AHB_GDMA", DMA_CH3, APB_SARADC), ("AHB_GDMA", DMA_CH3, RMT),
        ("AHB_GDMA", DMA_CH4, SPI2), ("AHB_GDMA", DMA_CH4, SPI3), ("AHB_GDMA", DMA_CH4,
        UHCI0), ("AHB_GDMA", DMA_CH4, I2S0), ("AHB_GDMA", DMA_CH4, I2S1), ("AHB_GDMA",
        DMA_CH4, LCD_CAM), ("AHB_GDMA", DMA_CH4, AES), ("AHB_GDMA", DMA_CH4, SHA),
        ("AHB_GDMA", DMA_CH4, APB_SARADC), ("AHB_GDMA", DMA_CH4, RMT)));
        _for_each_inner_dma_channel_peri_pair!((any_channels("AHB_GDMA", any_channel =
        AhbGdmaChannel, SPI2), ("AHB_GDMA", any_channel = AhbGdmaChannel, SPI3),
        ("AHB_GDMA", any_channel = AhbGdmaChannel, UHCI0), ("AHB_GDMA", any_channel =
        AhbGdmaChannel, I2S0), ("AHB_GDMA", any_channel = AhbGdmaChannel, I2S1),
        ("AHB_GDMA", any_channel = AhbGdmaChannel, LCD_CAM), ("AHB_GDMA", any_channel =
        AhbGdmaChannel, AES), ("AHB_GDMA", any_channel = AhbGdmaChannel, SHA),
        ("AHB_GDMA", any_channel = AhbGdmaChannel, APB_SARADC), ("AHB_GDMA", any_channel
        = AhbGdmaChannel, RMT)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_mem2mem_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_mem2mem_channel { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH0, 0)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, DMA_CH1, 0));
        _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel, DMA_CH2,
        0)); _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel,
        DMA_CH3, 0)); _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH4, 0)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0));
        _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel));
        _for_each_inner_mem2mem_channel!((channels("AHB_GDMA", AhbGdma, AhbGdmaChannel,
        DMA_CH0, 0), ("AHB_GDMA", AhbGdma, AhbGdmaChannel, DMA_CH1, 0), ("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, DMA_CH2, 0), ("AHB_GDMA", AhbGdma, AhbGdmaChannel,
        DMA_CH3, 0), ("AHB_GDMA", AhbGdma, AhbGdmaChannel, DMA_CH4, 0)));
        _for_each_inner_mem2mem_channel!((erased("AHB_GDMA", AhbGdma, AhbGdmaChannel, 0,
        0, 1, 0, 2, 0, 3, 0, 4, 0)));
        _for_each_inner_mem2mem_channel!((engines("AHB_GDMA", AhbGdma, AhbGdmaChannel)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_aes_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_aes_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_aes_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_i2s_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_i2s_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_i2s_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_lcd_cam_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_lcd_cam_dma_engine { $(($pattern) => $code;)* ($other :
        tt) => {} } _with_inner_lcd_cam_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_rmt_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_rmt_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_rmt_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_sha_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_sha_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_sha_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_master_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_master_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_slave_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_slave_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_slave_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_uhci_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_uhci_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_uhci_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// fn configure_xtal_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<XtalClkConfig>,
///     _new_config: XtalClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_CLK
///
/// fn enable_pll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_pll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<PllClkConfig>,
///     _new_config: PllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL32K_CLK
///
/// #[cfg(use_xtal32k)]
/// fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_DIV_CLK
///
/// fn enable_rc_fast_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV_IN
///
/// fn enable_system_pre_div_in_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_in_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivInConfig>,
///     _new_config: SystemPreDivInConfig,
/// ) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV
///
/// fn enable_system_pre_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivConfig>,
///     _new_config: SystemPreDivConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_PLL_DIV_OUT
///
/// fn enable_cpu_pll_div_out_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_pll_div_out_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuPllDivOutConfig>,
///     _new_config: CpuPllDivOutConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CRYPTO_PWM_CLK
///
/// fn enable_crypto_pwm_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_crypto_pwm_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CryptoPwmClkConfig>,
///     _new_config: CryptoPwmClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_D2
///
/// fn enable_pll_d2_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_160M
///
/// fn enable_pll_160m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // APB_80M
///
/// fn enable_apb_80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_CLK_DIV_N
///
/// fn enable_rc_fast_clk_div_n_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rc_fast_clk_div_n_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RcFastClkDivNConfig>,
///     _new_config: RcFastClkDivNConfig,
/// ) {
///     todo!()
/// }
///
/// // XTAL_DIV_CLK
///
/// fn enable_xtal_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RTC_SLOW_CLK
///
/// fn enable_rtc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcSlowClkConfig>,
///     _new_config: RtcSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // BLE_LP_XTAL_CLK
///
/// fn enable_ble_lp_xtal_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_CLK
///
/// fn enable_ble_lp_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ble_lp_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<BleLpClkConfig>,
///     _new_config: BleLpClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RTC_FAST_CLK
///
/// fn enable_rtc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcFastClkConfig>,
///     _new_config: RtcFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LOW_POWER_CLK
///
/// fn enable_low_power_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_low_power_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LowPowerClkConfig>,
///     _new_config: LowPowerClkConfig,
/// ) {
///     todo!()
/// }
///
/// // UART_MEM_CLK
///
/// fn enable_uart_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl SdmInstance {
///     // SDM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl I2cInstance {
///     // I2C_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2cFunctionClockConfig>,
///         _new_config: I2cFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2sInstance {
///     // I2S_TX_CLK
///
///     fn enable_tx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_tx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_RX_CLK
///
///     fn enable_rx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_rx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_MCLK_OUT
///
///     fn enable_mclk_out_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_mclk_out_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sMclkOutConfig>,
///         _new_config: I2sMclkOutConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl LcdCamInstance {
///     // LCD_CAM_LCD_CLOCK
///
///     fn enable_lcd_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_lcd_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<LcdCamLcdClockConfig>,
///         _new_config: LcdCamLcdClockConfig,
///     ) {
///         todo!()
///     }
///
///     // LCD_CAM_CAM_CLOCK
///
///     fn enable_cam_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_cam_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<LcdCamCamClockConfig>,
///         _new_config: LcdCamCamClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl McpwmInstance {
///     // MCPWM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl RmtInstance {
///     // RMT_SCLK
///
///     fn enable_sclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_sclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<RmtSclkConfig>,
///         _new_config: RmtSclkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl SpiInstance {
///     // SPI_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<SpiFunctionClockConfig>,
///         _new_config: SpiFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl TimgInstance {
///     // TIMG_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgFunctionClockConfig>,
///         _new_config: TimgFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_MEM_CLOCK
///
///     fn enable_mem_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SdmInstance {
            GpioSd = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cInstance {
            I2c0 = 0,
            I2c1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sInstance {
            I2s0 = 0,
            I2s1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LcdCamInstance {
            LcdCam = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum McpwmInstance {
            Mcpwm0 = 0,
            Mcpwm1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtInstance {
            Rmt = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiInstance {
            Spi2 = 0,
            Spi3 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgInstance {
            Timg0 = 0,
            Timg1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
            Uart2 = 2,
        }
        /// Selects the output frequency of `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum XtalClkConfig {
            /// 40 MHz
            _40,
        }
        impl XtalClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    XtalClkConfig::_40 => 40000000,
                }
            }
        }
        /// Selects the output frequency of `PLL_CLK`. Depends on `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum PllClkConfig {
            /// 320 MHz
            _320,
            /// 480 MHz
            _480,
        }
        impl PllClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    PllClkConfig::_320 => 320000000,
                    PllClkConfig::_480 => 480000000,
                }
            }
        }
        /// The list of clock signals that the `SYSTEM_PRE_DIV_IN` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SystemPreDivInConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `SYSTEM_PRE_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = SYSTEM_PRE_DIV_IN / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct SystemPreDivConfig {
            divisor: u32,
        }
        impl SystemPreDivConfig {
            /// Creates a new configuration for the SYSTEM_PRE_DIV clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 1023).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 1023,
                    "`SYSTEM_PRE_DIV` divisor must be between 0 and 1023 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Selects the output frequency of `CPU_PLL_DIV_OUT`. Depends on `PLL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuPllDivOutConfig {
            /// 80 MHz
            _80,
            /// 160 MHz
            _160,
            /// 240 MHz
            _240,
        }
        impl CpuPllDivOutConfig {
            pub fn value(&self) -> u32 {
                match self {
                    CpuPllDivOutConfig::_80 => 80000000,
                    CpuPllDivOutConfig::_160 => 160000000,
                    CpuPllDivOutConfig::_240 => 240000000,
                }
            }
        }
        /// The list of clock signals that the `APB_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ApbClkConfig {
            /// Selects `APB_80M`.
            Pll,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CRYPTO_PWM_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CryptoPwmClkConfig {
            /// Selects `PLL_160M`.
            Pll,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CPU_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuClkConfig {
            /// Selects `SYSTEM_PRE_DIV`.
            Xtal,
            /// Selects `SYSTEM_PRE_DIV`.
            RcFast,
            /// Selects `CPU_PLL_DIV_OUT`.
            Pll,
        }
        /// Configures the `RC_FAST_CLK_DIV_N` clock node.
        ///
        /// The output is calculated as `OUTPUT = RC_FAST_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RcFastClkDivNConfig {
            divisor: u32,
        }
        impl RcFastClkDivNConfig {
            /// Creates a new configuration for the RC_FAST_CLK_DIV_N clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 3).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 3,
                    "`RC_FAST_CLK_DIV_N` divisor must be between 0 and 3 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `RTC_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcSlowClkConfig {
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFast,
        }
        /// The list of clock signals that the `BLE_LP_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum BleLpClkConfig {
            /// Selects `BLE_LP_XTAL_CLK`.
            Xtal,
            /// Selects `RTC_SLOW_CLK`.
            RtcSlow,
        }
        /// The list of clock signals that the `RTC_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcFastClkConfig {
            /// Selects `XTAL_DIV_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK_DIV_N`.
            Rc,
        }
        /// The list of clock signals that the `LOW_POWER_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LowPowerClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `RTC_SLOW_CLK`.
            RtcSlow,
        }
        /// The list of clock signals that the `UART_MEM_CLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartMemClkConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlowClk,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFastDivClk,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32kClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `I2C0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2cFunctionClockConfig {
            sclk: I2cFunctionClockSclk,
            div_num: u32,
        }
        impl I2cFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: I2cFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`I2C0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> I2cFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sClkSclk {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `PLL_D2`.
            PllD2,
            #[default]
            /// Selects `PLL_160M`.
            Pll160m,
        }
        /// Configures the `I2S0_TX_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2sClkConfig {
            sclk: I2sClkSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl I2sClkConfig {
            /// Creates a new configuration for the TX_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (1 ..= 255).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 511).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 511).
            pub const fn new(sclk: I2sClkSclk, div_num: u32, div_a: u32, div_b: u32) -> Self {
                ::core::assert!(
                    div_num >= 1 && div_num <= 255,
                    "`I2S0_TX_CLK` div_num must be between 1 and 255 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 511,
                    "`I2S0_TX_CLK` div_a must be between 1 and 511 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 511,
                    "`I2S0_TX_CLK` div_b must be between 0 and 511 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> I2sClkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        /// The list of clock signals that the `I2S0_MCLK_OUT` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sMclkOutConfig {
            /// Selects `TX_CLK`.
            Tx,
            #[default]
            /// Selects `RX_CLK`.
            Rx,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LcdCamLcdClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `PLL_D2`.
            PllD2,
            /// Selects `PLL_160M`.
            Pll160m,
        }
        /// Configures the `LCD_CAM_LCD_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct LcdCamLcdClockConfig {
            sclk: LcdCamLcdClockSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl LcdCamLcdClockConfig {
            /// Creates a new configuration for the LCD_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (2 ..= 256).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 63).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 63).
            pub const fn new(
                sclk: LcdCamLcdClockSclk,
                div_num: u32,
                div_a: u32,
                div_b: u32,
            ) -> Self {
                ::core::assert!(
                    div_num >= 2 && div_num <= 256,
                    "`LCD_CAM_LCD_CLOCK` div_num must be between 2 and 256 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 63,
                    "`LCD_CAM_LCD_CLOCK` div_a must be between 1 and 63 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 63,
                    "`LCD_CAM_LCD_CLOCK` div_b must be between 0 and 63 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> LcdCamLcdClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LcdCamCamClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `PLL_D2`.
            PllD2,
            /// Selects `PLL_160M`.
            Pll160m,
        }
        /// Configures the `LCD_CAM_CAM_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct LcdCamCamClockConfig {
            sclk: LcdCamCamClockSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl LcdCamCamClockConfig {
            /// Creates a new configuration for the CAM_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (2 ..= 256).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 63).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 63).
            pub const fn new(
                sclk: LcdCamCamClockSclk,
                div_num: u32,
                div_a: u32,
                div_b: u32,
            ) -> Self {
                ::core::assert!(
                    div_num >= 2 && div_num <= 256,
                    "`LCD_CAM_CAM_CLOCK` div_num must be between 2 and 256 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 63,
                    "`LCD_CAM_CAM_CLOCK` div_a must be between 1 and 63 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 63,
                    "`LCD_CAM_CAM_CLOCK` div_b must be between 0 and 63 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> LcdCamCamClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        /// The list of clock signals that the `MCPWM0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum McpwmFunctionClockConfig {
            #[default]
            /// Selects `CRYPTO_PWM_CLK`.
            CryptoPwmClk,
        }
        /// The list of clock signals that the `RMT_SCLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtSclkConfig {
            #[default]
            /// Selects `APB_CLK`.
            ApbClk,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `XTAL_CLK`.
            XtalClk,
        }
        /// The list of clock signals that the `SPI2_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiFunctionClockConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            #[default]
            /// Selects `APB_CLK`.
            Apb,
        }
        /// The list of clock signals that the `TIMG0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `APB_CLK`.
            ApbClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            /// Selects `APB_CLK`.
            Apb,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
            div_num: u32,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: UartFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`UART0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 4095).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 4095,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 4095 (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            pub fn fractional(self) -> u32 {
                self.fractional as u32
            }
            pub fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            xtal_clk: Option<XtalClkConfig>,
            pll_clk: Option<PllClkConfig>,
            system_pre_div_in: Option<SystemPreDivInConfig>,
            system_pre_div: Option<SystemPreDivConfig>,
            cpu_pll_div_out: Option<CpuPllDivOutConfig>,
            apb_clk: Option<ApbClkConfig>,
            crypto_pwm_clk: Option<CryptoPwmClkConfig>,
            cpu_clk: Option<CpuClkConfig>,
            rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            rtc_slow_clk: Option<RtcSlowClkConfig>,
            ble_lp_clk: Option<BleLpClkConfig>,
            rtc_fast_clk: Option<RtcFastClkConfig>,
            low_power_clk: Option<LowPowerClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            i2c_function_clock: [Option<I2cFunctionClockConfig>; 2],
            i2s_tx_clk: [Option<I2sClkConfig>; 2],
            i2s_rx_clk: [Option<I2sClkConfig>; 2],
            i2s_mclk_out: [Option<I2sMclkOutConfig>; 2],
            lcd_cam_lcd_clock: [Option<LcdCamLcdClockConfig>; 1],
            lcd_cam_cam_clock: [Option<LcdCamCamClockConfig>; 1],
            rmt_sclk: [Option<RmtSclkConfig>; 1],
            spi_function_clock: [Option<SpiFunctionClockConfig>; 2],
            timg_function_clock: [Option<TimgFunctionClockConfig>; 2],
            uart_function_clock: [Option<UartFunctionClockConfig>; 3],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 3],
            pll_clk_refcount: u32,
            rc_fast_clk_refcount: u32,
            #[cfg(use_xtal32k)]
            xtal32k_clk_refcount: u32,
            rc_slow_clk_refcount: u32,
            rc_fast_div_clk_refcount: u32,
            apb_clk_refcount: u32,
            crypto_pwm_clk_refcount: u32,
            pll_d2_refcount: u32,
            pll_160m_refcount: u32,
            rtc_slow_clk_refcount: u32,
            ble_lp_clk_refcount: u32,
            rtc_fast_clk_refcount: u32,
            low_power_clk_refcount: u32,
            uart_mem_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            sdm_function_clock_refcount: [u32; 1],
            i2c_function_clock_refcount: [u32; 2],
            i2s_tx_clk_refcount: [u32; 2],
            i2s_rx_clk_refcount: [u32; 2],
            i2s_mclk_out_refcount: [u32; 2],
            lcd_cam_lcd_clock_refcount: [u32; 1],
            lcd_cam_cam_clock_refcount: [u32; 1],
            mcpwm_function_clock_refcount: [u32; 2],
            rmt_sclk_refcount: [u32; 1],
            spi_function_clock_refcount: [u32; 2],
            timg_function_clock_refcount: [u32; 2],
            uart_function_clock_refcount: [u32; 3],
            uart_baud_rate_generator_refcount: [u32; 3],
            uart_mem_clock_refcount: [u32; 3],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the XTAL_CLK clock tree node
            pub fn xtal_clk(&self) -> Option<XtalClkConfig> {
                self.xtal_clk
            }
            /// Returns the current configuration of the PLL_CLK clock tree node
            pub fn pll_clk(&self) -> Option<PllClkConfig> {
                self.pll_clk
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV_IN clock tree node
            pub fn system_pre_div_in(&self) -> Option<SystemPreDivInConfig> {
                self.system_pre_div_in
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV clock tree node
            pub fn system_pre_div(&self) -> Option<SystemPreDivConfig> {
                self.system_pre_div
            }
            /// Returns the current configuration of the CPU_PLL_DIV_OUT clock tree node
            pub fn cpu_pll_div_out(&self) -> Option<CpuPllDivOutConfig> {
                self.cpu_pll_div_out
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the CRYPTO_PWM_CLK clock tree node
            pub fn crypto_pwm_clk(&self) -> Option<CryptoPwmClkConfig> {
                self.crypto_pwm_clk
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the RC_FAST_CLK_DIV_N clock tree node
            pub fn rc_fast_clk_div_n(&self) -> Option<RcFastClkDivNConfig> {
                self.rc_fast_clk_div_n
            }
            /// Returns the current configuration of the RTC_SLOW_CLK clock tree node
            pub fn rtc_slow_clk(&self) -> Option<RtcSlowClkConfig> {
                self.rtc_slow_clk
            }
            /// Returns the current configuration of the BLE_LP_CLK clock tree node
            pub fn ble_lp_clk(&self) -> Option<BleLpClkConfig> {
                self.ble_lp_clk
            }
            /// Returns the current configuration of the RTC_FAST_CLK clock tree node
            pub fn rtc_fast_clk(&self) -> Option<RtcFastClkConfig> {
                self.rtc_fast_clk
            }
            /// Returns the current configuration of the LOW_POWER_CLK clock tree node
            pub fn low_power_clk(&self) -> Option<LowPowerClkConfig> {
                self.low_power_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the I2C0_FUNCTION_CLOCK clock tree node
            pub fn i2c0_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c0 as usize]
            }
            /// Returns the current configuration of the I2C1_FUNCTION_CLOCK clock tree node
            pub fn i2c1_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c1 as usize]
            }
            /// Returns the current configuration of the I2S0_TX_CLK clock tree node
            pub fn i2s0_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_RX_CLK clock tree node
            pub fn i2s0_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_MCLK_OUT clock tree node
            pub fn i2s0_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S1_TX_CLK clock tree node
            pub fn i2s1_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the I2S1_RX_CLK clock tree node
            pub fn i2s1_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the I2S1_MCLK_OUT clock tree node
            pub fn i2s1_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the LCD_CAM_LCD_CLOCK clock tree node
            pub fn lcd_cam_lcd_clock(&self) -> Option<LcdCamLcdClockConfig> {
                self.lcd_cam_lcd_clock[LcdCamInstance::LcdCam as usize]
            }
            /// Returns the current configuration of the LCD_CAM_CAM_CLOCK clock tree node
            pub fn lcd_cam_cam_clock(&self) -> Option<LcdCamCamClockConfig> {
                self.lcd_cam_cam_clock[LcdCamInstance::LcdCam as usize]
            }
            /// Returns the current configuration of the RMT_SCLK clock tree node
            pub fn rmt_sclk(&self) -> Option<RmtSclkConfig> {
                self.rmt_sclk[RmtInstance::Rmt as usize]
            }
            /// Returns the current configuration of the SPI2_FUNCTION_CLOCK clock tree node
            pub fn spi2_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi2 as usize]
            }
            /// Returns the current configuration of the SPI3_FUNCTION_CLOCK clock tree node
            pub fn spi3_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi3 as usize]
            }
            /// Returns the current configuration of the TIMG0_FUNCTION_CLOCK clock tree node
            pub fn timg0_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG1_FUNCTION_CLOCK clock tree node
            pub fn timg1_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART2_FUNCTION_CLOCK clock tree node
            pub fn uart2_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart2 as usize]
            }
            /// Returns the current configuration of the UART2_BAUD_RATE_GENERATOR clock tree node
            pub fn uart2_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart2 as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                xtal_clk: None,
                pll_clk: None,
                system_pre_div_in: None,
                system_pre_div: None,
                cpu_pll_div_out: None,
                apb_clk: None,
                crypto_pwm_clk: None,
                cpu_clk: None,
                rc_fast_clk_div_n: None,
                rtc_slow_clk: None,
                ble_lp_clk: None,
                rtc_fast_clk: None,
                low_power_clk: None,
                timg_calibration_clock: None,
                i2c_function_clock: [None; 2],
                i2s_tx_clk: [None; 2],
                i2s_rx_clk: [None; 2],
                i2s_mclk_out: [None; 2],
                lcd_cam_lcd_clock: [None; 1],
                lcd_cam_cam_clock: [None; 1],
                rmt_sclk: [None; 1],
                spi_function_clock: [None; 2],
                timg_function_clock: [None; 2],
                uart_function_clock: [None; 3],
                uart_baud_rate_generator: [None; 3],
                pll_clk_refcount: 0,
                rc_fast_clk_refcount: 0,
                #[cfg(use_xtal32k)]
                xtal32k_clk_refcount: 0,
                rc_slow_clk_refcount: 0,
                rc_fast_div_clk_refcount: 0,
                apb_clk_refcount: 0,
                crypto_pwm_clk_refcount: 0,
                pll_d2_refcount: 0,
                pll_160m_refcount: 0,
                rtc_slow_clk_refcount: 0,
                ble_lp_clk_refcount: 0,
                rtc_fast_clk_refcount: 0,
                low_power_clk_refcount: 0,
                uart_mem_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                sdm_function_clock_refcount: [0; 1],
                i2c_function_clock_refcount: [0; 2],
                i2s_tx_clk_refcount: [0; 2],
                i2s_rx_clk_refcount: [0; 2],
                i2s_mclk_out_refcount: [0; 2],
                lcd_cam_lcd_clock_refcount: [0; 1],
                lcd_cam_cam_clock_refcount: [0; 1],
                mcpwm_function_clock_refcount: [0; 2],
                rmt_sclk_refcount: [0; 1],
                spi_function_clock_refcount: [0; 2],
                timg_function_clock_refcount: [0; 2],
                uart_function_clock_refcount: [0; 3],
                uart_baud_rate_generator_refcount: [0; 3],
                uart_mem_clock_refcount: [0; 3],
            });
        static XTAL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static PLL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSTEM_PRE_DIV_IN_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSTEM_PRE_DIV_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_PLL_DIV_OUT_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RC_FAST_CLK_DIV_N_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_SLOW_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static BLE_LP_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_FAST_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LOW_POWER_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_CALIBRATION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static I2C_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static I2S_TX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static I2S_RX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static I2S_MCLK_OUT_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static LCD_CAM_LCD_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static LCD_CAM_CAM_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static APB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CRYPTO_PWM_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RMT_SCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static SPI_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static TIMG_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static UART_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static UART_BAUD_RATE_GENERATOR_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        /// The clock sources of the device.
        ///
        /// A clock source is a node of the clock tree that other nodes derive their output
        /// from. Ask a node which source it runs on with its `..._root_source` function.
        #[derive(Debug, enumset::EnumSetType)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ClockSource {
            /// `XTAL_CLK`.
            XtalClk,
            /// `RC_FAST_CLK`.
            RcFastClk,
            #[cfg(use_xtal32k)]
            /// `XTAL32K_CLK`.
            Xtal32kClk,
            /// `RC_SLOW_CLK`.
            RcSlowClk,
        }
        /// Returns the clock source that `XTAL_CLK` currently runs on.
        pub fn xtal_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::XtalClk)
        }
        /// Returns the clock source that `PLL_CLK` currently runs on.
        pub fn pll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK` currently runs on.
        pub fn rc_fast_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcFastClk)
        }
        #[cfg(use_xtal32k)]
        /// Returns the clock source that `XTAL32K_CLK` currently runs on.
        pub fn xtal32k_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::Xtal32kClk)
        }
        /// Returns the clock source that `RC_SLOW_CLK` currently runs on.
        pub fn rc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcSlowClk)
        }
        /// Returns the clock source that `RC_FAST_DIV_CLK` currently runs on.
        pub fn rc_fast_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_fast_clk_root_source(clocks)
        }
        /// Returns the clock source that `SYSTEM_PRE_DIV_IN` currently runs on.
        pub fn system_pre_div_in_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.system_pre_div_in?;
            match config {
                SystemPreDivInConfig::Xtal => xtal_clk_root_source(clocks),
                SystemPreDivInConfig::RcFast => rc_fast_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `SYSTEM_PRE_DIV` currently runs on.
        pub fn system_pre_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            system_pre_div_in_root_source(clocks)
        }
        /// Returns the clock source that `CPU_PLL_DIV_OUT` currently runs on.
        pub fn cpu_pll_div_out_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `CPU_CLK` currently runs on.
        pub fn cpu_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.cpu_clk?;
            match config {
                CpuClkConfig::Xtal => system_pre_div_root_source(clocks),
                CpuClkConfig::RcFast => system_pre_div_root_source(clocks),
                CpuClkConfig::Pll => cpu_pll_div_out_root_source(clocks),
            }
        }
        /// Returns the clock source that `PLL_D2` currently runs on.
        pub fn pll_d2_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_160M` currently runs on.
        pub fn pll_160m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `APB_80M` currently runs on.
        pub fn apb_80m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK_DIV_N` currently runs on.
        pub fn rc_fast_clk_div_n_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_fast_clk_root_source(clocks)
        }
        /// Returns the clock source that `XTAL_DIV_CLK` currently runs on.
        pub fn xtal_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RTC_SLOW_CLK` currently runs on.
        pub fn rtc_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_slow_clk?;
            match config {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_root_source(clocks),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `BLE_LP_XTAL_CLK` currently runs on.
        pub fn ble_lp_xtal_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_CLK` currently runs on.
        pub fn ble_lp_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.ble_lp_clk?;
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_root_source(clocks),
                BleLpClkConfig::RtcSlow => rtc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `RTC_FAST_CLK` currently runs on.
        pub fn rtc_fast_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_fast_clk?;
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_root_source(clocks),
                RtcFastClkConfig::Rc => rc_fast_clk_div_n_root_source(clocks),
            }
        }
        /// Returns the clock source that `LOW_POWER_CLK` currently runs on.
        pub fn low_power_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.low_power_clk?;
            match config {
                LowPowerClkConfig::Xtal => xtal_clk_root_source(clocks),
                LowPowerClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                LowPowerClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
                LowPowerClkConfig::RtcSlow => rtc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `UART_MEM_CLK` currently runs on.
        pub fn uart_mem_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `TIMG_CALIBRATION_CLOCK` currently runs on.
        pub fn timg_calibration_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.timg_calibration_clock?;
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `APB_CLK` currently runs on.
        pub fn apb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.apb_clk?;
            match config {
                ApbClkConfig::Pll => apb_80m_root_source(clocks),
                ApbClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CRYPTO_PWM_CLK` currently runs on.
        pub fn crypto_pwm_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.crypto_pwm_clk?;
            match config {
                CryptoPwmClkConfig::Pll => pll_160m_root_source(clocks),
                CryptoPwmClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        pub fn configure_xtal_clk(clocks: &mut ClockTree, config: XtalClkConfig) {
            let old_config = clocks.xtal_clk.replace(config);
            refresh_xtal_clk_downstream(clocks);
            configure_xtal_clk_impl(clocks, old_config, config);
        }
        pub fn xtal_clk_config(clocks: &mut ClockTree) -> Option<XtalClkConfig> {
            clocks.xtal_clk
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        pub fn xtal_clk_config_frequency(config: XtalClkConfig) -> u32 {
            config.value()
        }
        pub fn xtal_clk_frequency() -> u32 {
            XTAL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn configure_pll_clk(clocks: &mut ClockTree, config: PllClkConfig) {
            if clocks.cpu_pll_div_out.is_some() {
                assert!(
                    !((config.value() == 320000000) && (cpu_pll_div_out_frequency() == 240000000))
                );
            }
            let old_config = clocks.pll_clk.replace(config);
            refresh_pll_clk_downstream(clocks);
            configure_pll_clk_impl(clocks, old_config, config);
        }
        pub fn pll_clk_config(clocks: &mut ClockTree) -> Option<PllClkConfig> {
            clocks.pll_clk
        }
        pub fn request_pll_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_CLK");
            if increment_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Enabling PLL_CLK");
                request_xtal_clk(clocks);
                enable_pll_clk_impl(clocks, true);
            }
        }
        pub fn release_pll_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_CLK");
            if decrement_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Disabling PLL_CLK");
                enable_pll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn pll_clk_config_frequency(config: PllClkConfig) -> u32 {
            config.value()
        }
        pub fn pll_clk_frequency() -> u32 {
            PLL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn pll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        static RC_FAST_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_fast_clk_nominal_frequency());
        pub const fn rc_fast_clk_nominal_frequency() -> u32 {
            17500000
        }
        pub fn rc_fast_clk_frequency() -> u32 {
            RC_FAST_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_fast_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(8750000..=26250000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_FAST_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_FAST_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_fast_clk_nominal_frequency()
            );
            RC_FAST_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_fast_clk_downstream(clocks);
        }
        #[cfg(use_xtal32k)]
        pub fn request_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL32K_CLK");
            if increment_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Enabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, true);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn release_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL32K_CLK");
            if decrement_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Disabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, false);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn xtal32k_clk_frequency() -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Enabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Disabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, false);
            }
        }
        static RC_SLOW_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_slow_clk_nominal_frequency());
        pub const fn rc_slow_clk_nominal_frequency() -> u32 {
            136000
        }
        pub fn rc_slow_clk_frequency() -> u32 {
            RC_SLOW_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_slow_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(68000..=204000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_SLOW_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_SLOW_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_slow_clk_nominal_frequency()
            );
            RC_SLOW_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_slow_clk_downstream(clocks);
        }
        pub fn request_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_DIV_CLK");
            if increment_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Enabling RC_FAST_DIV_CLK");
                request_rc_fast_clk(clocks);
                enable_rc_fast_div_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_DIV_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Disabling RC_FAST_DIV_CLK");
                enable_rc_fast_div_clk_impl(clocks, false);
                release_rc_fast_clk(clocks);
            }
        }
        pub fn rc_fast_div_clk_frequency() -> u32 {
            (rc_fast_clk_frequency() / 256)
        }
        pub fn rc_fast_div_clk_source_frequency() -> u32 {
            rc_fast_clk_frequency()
        }
        pub fn configure_system_pre_div_in(
            clocks: &mut ClockTree,
            new_selector: SystemPreDivInConfig,
        ) {
            let old_selector = clocks.system_pre_div_in.replace(new_selector);
            refresh_system_pre_div_in_downstream(clocks);
            match new_selector {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            configure_system_pre_div_in_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                    SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn system_pre_div_in_config(clocks: &mut ClockTree) -> Option<SystemPreDivInConfig> {
            clocks.system_pre_div_in
        }
        pub fn request_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Enabling SYSTEM_PRE_DIV_IN");
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            enable_system_pre_div_in_impl(clocks, true);
        }
        pub fn release_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Disabling SYSTEM_PRE_DIV_IN");
            enable_system_pre_div_in_impl(clocks, false);
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
            }
        }
        pub fn system_pre_div_in_config_frequency(config: SystemPreDivInConfig) -> u32 {
            match config {
                SystemPreDivInConfig::Xtal => xtal_clk_frequency(),
                SystemPreDivInConfig::RcFast => rc_fast_clk_frequency(),
            }
        }
        pub fn system_pre_div_in_frequency() -> u32 {
            SYSTEM_PRE_DIV_IN_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn system_pre_div_in_source_frequency(source: SystemPreDivInConfig) -> u32 {
            system_pre_div_in_config_frequency(source)
        }
        pub fn configure_system_pre_div(clocks: &mut ClockTree, config: SystemPreDivConfig) {
            let old_config = clocks.system_pre_div.replace(config);
            refresh_system_pre_div_downstream(clocks);
            configure_system_pre_div_impl(clocks, old_config, config);
        }
        pub fn system_pre_div_config(clocks: &mut ClockTree) -> Option<SystemPreDivConfig> {
            clocks.system_pre_div
        }
        pub fn request_system_pre_div(clocks: &mut ClockTree) {
            trace!("Enabling SYSTEM_PRE_DIV");
            request_system_pre_div_in(clocks);
            enable_system_pre_div_impl(clocks, true);
        }
        pub fn release_system_pre_div(clocks: &mut ClockTree) {
            trace!("Disabling SYSTEM_PRE_DIV");
            enable_system_pre_div_impl(clocks, false);
            release_system_pre_div_in(clocks);
        }
        pub fn system_pre_div_config_frequency(config: SystemPreDivConfig) -> u32 {
            (system_pre_div_in_frequency() / (config.divisor() + 1))
        }
        pub fn system_pre_div_frequency() -> u32 {
            SYSTEM_PRE_DIV_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn system_pre_div_source_frequency() -> u32 {
            system_pre_div_in_frequency()
        }
        pub fn configure_cpu_pll_div_out(clocks: &mut ClockTree, config: CpuPllDivOutConfig) {
            if clocks.pll_clk.is_some() {
                assert!(!((config.value() == 240000000) && (pll_clk_frequency() == 320000000)));
            }
            let old_config = clocks.cpu_pll_div_out.replace(config);
            refresh_cpu_pll_div_out_downstream(clocks);
            configure_cpu_pll_div_out_impl(clocks, old_config, config);
        }
        pub fn cpu_pll_div_out_config(clocks: &mut ClockTree) -> Option<CpuPllDivOutConfig> {
            clocks.cpu_pll_div_out
        }
        pub fn request_cpu_pll_div_out(clocks: &mut ClockTree) {
            trace!("Enabling CPU_PLL_DIV_OUT");
            request_pll_clk(clocks);
            enable_cpu_pll_div_out_impl(clocks, true);
        }
        pub fn release_cpu_pll_div_out(clocks: &mut ClockTree) {
            trace!("Disabling CPU_PLL_DIV_OUT");
            enable_cpu_pll_div_out_impl(clocks, false);
            release_pll_clk(clocks);
        }
        pub fn cpu_pll_div_out_config_frequency(config: CpuPllDivOutConfig) -> u32 {
            config.value()
        }
        pub fn cpu_pll_div_out_frequency() -> u32 {
            CPU_PLL_DIV_OUT_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_pll_div_out_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, new_selector: ApbClkConfig) {
            let old_selector = clocks.apb_clk.replace(new_selector);
            refresh_apb_clk_downstream(clocks);
            let active = clocks.apb_clk_refcount > 0;
            if active {
                match new_selector {
                    ApbClkConfig::Pll => request_apb_80m(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
            }
            configure_apb_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    ApbClkConfig::Pll => release_apb_80m(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Requesting APB_CLK");
            if increment_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Enabling APB_CLK");
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll => request_apb_80m(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_apb_clk_impl(clocks, true);
            }
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Releasing APB_CLK");
            if decrement_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Disabling APB_CLK");
                enable_apb_clk_impl(clocks, false);
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll => release_apb_80m(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn apb_clk_config_frequency(config: ApbClkConfig) -> u32 {
            match config {
                ApbClkConfig::Pll => apb_80m_frequency(),
                ApbClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn apb_clk_frequency() -> u32 {
            APB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apb_clk_source_frequency(source: ApbClkConfig) -> u32 {
            apb_clk_config_frequency(source)
        }
        pub fn configure_crypto_pwm_clk(clocks: &mut ClockTree, new_selector: CryptoPwmClkConfig) {
            let old_selector = clocks.crypto_pwm_clk.replace(new_selector);
            refresh_crypto_pwm_clk_downstream(clocks);
            let active = clocks.crypto_pwm_clk_refcount > 0;
            if active {
                match new_selector {
                    CryptoPwmClkConfig::Pll => request_pll_160m(clocks),
                    CryptoPwmClkConfig::Cpu => request_cpu_clk(clocks),
                }
            }
            configure_crypto_pwm_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    CryptoPwmClkConfig::Pll => release_pll_160m(clocks),
                    CryptoPwmClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn crypto_pwm_clk_config(clocks: &mut ClockTree) -> Option<CryptoPwmClkConfig> {
            clocks.crypto_pwm_clk
        }
        pub fn request_crypto_pwm_clk(clocks: &mut ClockTree) {
            trace!("Requesting CRYPTO_PWM_CLK");
            if increment_reference_count(&mut clocks.crypto_pwm_clk_refcount) {
                trace!("Enabling CRYPTO_PWM_CLK");
                match unwrap!(clocks.crypto_pwm_clk) {
                    CryptoPwmClkConfig::Pll => request_pll_160m(clocks),
                    CryptoPwmClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_crypto_pwm_clk_impl(clocks, true);
            }
        }
        pub fn release_crypto_pwm_clk(clocks: &mut ClockTree) {
            trace!("Releasing CRYPTO_PWM_CLK");
            if decrement_reference_count(&mut clocks.crypto_pwm_clk_refcount) {
                trace!("Disabling CRYPTO_PWM_CLK");
                enable_crypto_pwm_clk_impl(clocks, false);
                match unwrap!(clocks.crypto_pwm_clk) {
                    CryptoPwmClkConfig::Pll => release_pll_160m(clocks),
                    CryptoPwmClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn crypto_pwm_clk_config_frequency(config: CryptoPwmClkConfig) -> u32 {
            match config {
                CryptoPwmClkConfig::Pll => pll_160m_frequency(),
                CryptoPwmClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn crypto_pwm_clk_frequency() -> u32 {
            CRYPTO_PWM_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn crypto_pwm_clk_source_frequency(source: CryptoPwmClkConfig) -> u32 {
            crypto_pwm_clk_config_frequency(source)
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, new_selector: CpuClkConfig) {
            let old_selector = clocks.cpu_clk.replace(new_selector);
            refresh_cpu_clk_downstream(clocks);
            match new_selector {
                CpuClkConfig::Xtal => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_pwm_clk(clocks, CryptoPwmClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::Xtal);
                }
                CpuClkConfig::RcFast => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_pwm_clk(clocks, CryptoPwmClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::RcFast);
                }
                CpuClkConfig::Pll => {
                    configure_apb_clk(clocks, ApbClkConfig::Pll);
                    configure_crypto_pwm_clk(clocks, CryptoPwmClkConfig::Pll);
                }
            }
            match new_selector {
                CpuClkConfig::Xtal => request_system_pre_div(clocks),
                CpuClkConfig::RcFast => request_system_pre_div(clocks),
                CpuClkConfig::Pll => request_cpu_pll_div_out(clocks),
            }
            configure_cpu_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuClkConfig::Xtal => release_system_pre_div(clocks),
                    CpuClkConfig::RcFast => release_system_pre_div(clocks),
                    CpuClkConfig::Pll => release_cpu_pll_div_out(clocks),
                }
            }
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        fn request_cpu_clk(_clocks: &mut ClockTree) {}
        fn release_cpu_clk(_clocks: &mut ClockTree) {}
        pub fn cpu_clk_config_frequency(config: CpuClkConfig) -> u32 {
            match config {
                CpuClkConfig::Xtal => system_pre_div_frequency(),
                CpuClkConfig::RcFast => system_pre_div_frequency(),
                CpuClkConfig::Pll => cpu_pll_div_out_frequency(),
            }
        }
        pub fn cpu_clk_frequency() -> u32 {
            CPU_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn request_pll_d2(clocks: &mut ClockTree) {
            trace!("Requesting PLL_D2");
            if increment_reference_count(&mut clocks.pll_d2_refcount) {
                trace!("Enabling PLL_D2");
                request_pll_clk(clocks);
                enable_pll_d2_impl(clocks, true);
            }
        }
        pub fn release_pll_d2(clocks: &mut ClockTree) {
            trace!("Releasing PLL_D2");
            if decrement_reference_count(&mut clocks.pll_d2_refcount) {
                trace!("Disabling PLL_D2");
                enable_pll_d2_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_d2_frequency() -> u32 {
            (pll_clk_frequency() / 2)
        }
        pub fn pll_d2_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_160m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_160M");
            if increment_reference_count(&mut clocks.pll_160m_refcount) {
                trace!("Enabling PLL_160M");
                request_cpu_clk(clocks);
                enable_pll_160m_impl(clocks, true);
            }
        }
        pub fn release_pll_160m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_160M");
            if decrement_reference_count(&mut clocks.pll_160m_refcount) {
                trace!("Disabling PLL_160M");
                enable_pll_160m_impl(clocks, false);
                release_cpu_clk(clocks);
            }
        }
        pub fn pll_160m_frequency() -> u32 {
            160000000
        }
        pub fn pll_160m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn request_apb_80m(clocks: &mut ClockTree) {
            trace!("Enabling APB_80M");
            request_cpu_clk(clocks);
            enable_apb_80m_impl(clocks, true);
        }
        pub fn release_apb_80m(clocks: &mut ClockTree) {
            trace!("Disabling APB_80M");
            enable_apb_80m_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn apb_80m_frequency() -> u32 {
            80000000
        }
        pub fn apb_80m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn configure_rc_fast_clk_div_n(clocks: &mut ClockTree, config: RcFastClkDivNConfig) {
            let old_config = clocks.rc_fast_clk_div_n.replace(config);
            refresh_rc_fast_clk_div_n_downstream(clocks);
            configure_rc_fast_clk_div_n_impl(clocks, old_config, config);
        }
        pub fn rc_fast_clk_div_n_config(clocks: &mut ClockTree) -> Option<RcFastClkDivNConfig> {
            clocks.rc_fast_clk_div_n
        }
        pub fn request_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Enabling RC_FAST_CLK_DIV_N");
            request_rc_fast_clk(clocks);
            enable_rc_fast_clk_div_n_impl(clocks, true);
        }
        pub fn release_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Disabling RC_FAST_CLK_DIV_N");
            enable_rc_fast_clk_div_n_impl(clocks, false);
            release_rc_fast_clk(clocks);
        }
        pub fn rc_fast_clk_div_n_config_frequency(config: RcFastClkDivNConfig) -> u32 {
            (rc_fast_clk_frequency() / (config.divisor() + 1))
        }
        pub fn rc_fast_clk_div_n_frequency() -> u32 {
            RC_FAST_CLK_DIV_N_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rc_fast_clk_div_n_source_frequency() -> u32 {
            rc_fast_clk_frequency()
        }
        pub fn request_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Enabling XTAL_DIV_CLK");
            request_xtal_clk(clocks);
            enable_xtal_div_clk_impl(clocks, true);
        }
        pub fn release_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Disabling XTAL_DIV_CLK");
            enable_xtal_div_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_div_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 2)
        }
        pub fn xtal_div_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_rtc_slow_clk(clocks: &mut ClockTree, new_selector: RtcSlowClkConfig) {
            let old_selector = clocks.rtc_slow_clk.replace(new_selector);
            refresh_rtc_slow_clk_downstream(clocks);
            let active = clocks.rtc_slow_clk_refcount > 0;
            if active {
                match new_selector {
                    #[cfg(use_xtal32k)]
                    RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
                }
            }
            configure_rtc_slow_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    #[cfg(use_xtal32k)]
                    RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
                }
            }
        }
        pub fn rtc_slow_clk_config(clocks: &mut ClockTree) -> Option<RtcSlowClkConfig> {
            clocks.rtc_slow_clk
        }
        pub fn request_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rtc_slow_clk_refcount) {
                trace!("Enabling RTC_SLOW_CLK");
                match unwrap!(clocks.rtc_slow_clk) {
                    #[cfg(use_xtal32k)]
                    RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
                }
                enable_rtc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rtc_slow_clk_refcount) {
                trace!("Disabling RTC_SLOW_CLK");
                enable_rtc_slow_clk_impl(clocks, false);
                match unwrap!(clocks.rtc_slow_clk) {
                    #[cfg(use_xtal32k)]
                    RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
                }
            }
        }
        pub fn rtc_slow_clk_config_frequency(config: RtcSlowClkConfig) -> u32 {
            match config {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => xtal32k_clk_frequency(),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_frequency(),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_frequency(),
            }
        }
        pub fn rtc_slow_clk_frequency() -> u32 {
            RTC_SLOW_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_slow_clk_source_frequency(source: RtcSlowClkConfig) -> u32 {
            rtc_slow_clk_config_frequency(source)
        }
        pub fn request_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_XTAL_CLK");
            request_xtal_clk(clocks);
            enable_ble_lp_xtal_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_XTAL_CLK");
            enable_ble_lp_xtal_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn ble_lp_xtal_clk_frequency() -> u32 {
            1000000
        }
        pub fn ble_lp_xtal_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_ble_lp_clk(clocks: &mut ClockTree, new_selector: BleLpClkConfig) {
            let old_selector = clocks.ble_lp_clk.replace(new_selector);
            refresh_ble_lp_clk_downstream(clocks);
            let active = clocks.ble_lp_clk_refcount > 0;
            if active {
                match new_selector {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
            }
            configure_ble_lp_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config(clocks: &mut ClockTree) -> Option<BleLpClkConfig> {
            clocks.ble_lp_clk
        }
        pub fn request_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Requesting BLE_LP_CLK");
            if increment_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Enabling BLE_LP_CLK");
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                enable_ble_lp_clk_impl(clocks, true);
            }
        }
        pub fn release_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Releasing BLE_LP_CLK");
            if decrement_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Disabling BLE_LP_CLK");
                enable_ble_lp_clk_impl(clocks, false);
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config_frequency(config: BleLpClkConfig) -> u32 {
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_frequency(),
                BleLpClkConfig::RtcSlow => rtc_slow_clk_frequency(),
            }
        }
        pub fn ble_lp_clk_frequency() -> u32 {
            BLE_LP_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ble_lp_clk_source_frequency(source: BleLpClkConfig) -> u32 {
            ble_lp_clk_config_frequency(source)
        }
        pub fn configure_rtc_fast_clk(clocks: &mut ClockTree, new_selector: RtcFastClkConfig) {
            let old_selector = clocks.rtc_fast_clk.replace(new_selector);
            refresh_rtc_fast_clk_downstream(clocks);
            let active = clocks.rtc_fast_clk_refcount > 0;
            if active {
                match new_selector {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
            }
            configure_rtc_fast_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config(clocks: &mut ClockTree) -> Option<RtcFastClkConfig> {
            clocks.rtc_fast_clk
        }
        pub fn request_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_FAST_CLK");
            if increment_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Enabling RTC_FAST_CLK");
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
                enable_rtc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Disabling RTC_FAST_CLK");
                enable_rtc_fast_clk_impl(clocks, false);
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config_frequency(config: RtcFastClkConfig) -> u32 {
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_frequency(),
                RtcFastClkConfig::Rc => rc_fast_clk_div_n_frequency(),
            }
        }
        pub fn rtc_fast_clk_frequency() -> u32 {
            RTC_FAST_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_fast_clk_source_frequency(source: RtcFastClkConfig) -> u32 {
            rtc_fast_clk_config_frequency(source)
        }
        pub fn configure_low_power_clk(clocks: &mut ClockTree, new_selector: LowPowerClkConfig) {
            let old_selector = clocks.low_power_clk.replace(new_selector);
            refresh_low_power_clk_downstream(clocks);
            let active = clocks.low_power_clk_refcount > 0;
            if active {
                match new_selector {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LowPowerClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
            }
            configure_low_power_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LowPowerClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn low_power_clk_config(clocks: &mut ClockTree) -> Option<LowPowerClkConfig> {
            clocks.low_power_clk
        }
        pub fn request_low_power_clk(clocks: &mut ClockTree) {
            trace!("Requesting LOW_POWER_CLK");
            if increment_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Enabling LOW_POWER_CLK");
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LowPowerClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                enable_low_power_clk_impl(clocks, true);
            }
        }
        pub fn release_low_power_clk(clocks: &mut ClockTree) {
            trace!("Releasing LOW_POWER_CLK");
            if decrement_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Disabling LOW_POWER_CLK");
                enable_low_power_clk_impl(clocks, false);
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LowPowerClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn low_power_clk_config_frequency(config: LowPowerClkConfig) -> u32 {
            match config {
                LowPowerClkConfig::Xtal => xtal_clk_frequency(),
                LowPowerClkConfig::RcFast => rc_fast_clk_frequency(),
                #[cfg(use_xtal32k)]
                LowPowerClkConfig::Xtal32k => xtal32k_clk_frequency(),
                LowPowerClkConfig::RtcSlow => rtc_slow_clk_frequency(),
            }
        }
        pub fn low_power_clk_frequency() -> u32 {
            LOW_POWER_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn low_power_clk_source_frequency(source: LowPowerClkConfig) -> u32 {
            low_power_clk_config_frequency(source)
        }
        pub fn request_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Requesting UART_MEM_CLK");
            if increment_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Enabling UART_MEM_CLK");
                request_xtal_clk(clocks);
                enable_uart_mem_clk_impl(clocks, true);
            }
        }
        pub fn release_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Releasing UART_MEM_CLK");
            if decrement_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Disabling UART_MEM_CLK");
                enable_uart_mem_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn uart_mem_clk_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn uart_mem_clk_source_frequency(source: UartMemClkConfig) -> u32 {
            match source {
                UartMemClkConfig::Xtal => xtal_clk_frequency(),
            }
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            refresh_timg_calibration_clock_downstream(clocks);
            let active = clocks.timg_calibration_clock_refcount > 0;
            if active {
                match new_selector {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
            }
            configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::acquire();
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::release();
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config_frequency(config: TimgCalibrationClockConfig) -> u32 {
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_frequency(),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_frequency(),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_frequency(),
            }
        }
        pub fn timg_calibration_clock_frequency() -> u32 {
            TIMG_CALIBRATION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn timg_calibration_clock_source_frequency(source: TimgCalibrationClockConfig) -> u32 {
            timg_calibration_clock_config_frequency(source)
        }
        impl SdmInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    request_apb_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    release_apb_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_source_frequency() -> u32 {
                apb_clk_frequency()
            }
        }
        impl I2cInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: I2cFunctionClockConfig,
            ) {
                let old_config = clocks.i2c_function_clock[self as usize].replace(config);
                refresh_i2c_function_clock_downstream(clocks, self);
                let active = clocks.i2c_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<I2cFunctionClockConfig> {
                clocks.i2c_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: I2cFunctionClockConfig) -> u32 {
                (match config.sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: I2cFunctionClockSclk) -> u32 {
                match sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
        }
        impl I2sInstance {
            pub fn configure_tx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_tx_clk[self as usize].replace(config);
                refresh_i2s_tx_clk_downstream(clocks, self);
                let active = clocks.i2s_tx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => request_pll_d2(clocks),
                        I2sClkSclk::Pll160m => request_pll_160m(clocks),
                    }
                }
                self.configure_tx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => release_pll_d2(clocks),
                        I2sClkSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_tx_clk[self as usize]
            }
            pub fn request_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::TX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => request_pll_d2(clocks),
                        I2sClkSclk::Pll160m => request_pll_160m(clocks),
                    }
                    self.enable_tx_clk_impl(clocks, true);
                }
            }
            pub fn release_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::TX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_tx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => release_pll_d2(clocks),
                        I2sClkSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllD2 => pll_d2_frequency(),
                    I2sClkSclk::Pll160m => pll_160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn tx_clk_frequency(self) -> u32 {
                I2S_TX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn tx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllD2 => pll_d2_frequency(),
                    I2sClkSclk::Pll160m => pll_160m_frequency(),
                }
            }
            pub fn configure_rx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_rx_clk[self as usize].replace(config);
                refresh_i2s_rx_clk_downstream(clocks, self);
                let active = clocks.i2s_rx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => request_pll_d2(clocks),
                        I2sClkSclk::Pll160m => request_pll_160m(clocks),
                    }
                }
                self.configure_rx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => release_pll_d2(clocks),
                        I2sClkSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_rx_clk[self as usize]
            }
            pub fn request_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::RX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => request_pll_d2(clocks),
                        I2sClkSclk::Pll160m => request_pll_160m(clocks),
                    }
                    self.enable_rx_clk_impl(clocks, true);
                }
            }
            pub fn release_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::RX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_rx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllD2 => release_pll_d2(clocks),
                        I2sClkSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllD2 => pll_d2_frequency(),
                    I2sClkSclk::Pll160m => pll_160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn rx_clk_frequency(self) -> u32 {
                I2S_RX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn rx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllD2 => pll_d2_frequency(),
                    I2sClkSclk::Pll160m => pll_160m_frequency(),
                }
            }
            pub fn configure_mclk_out(
                self,
                clocks: &mut ClockTree,
                new_selector: I2sMclkOutConfig,
            ) {
                let old_selector = clocks.i2s_mclk_out[self as usize].replace(new_selector);
                refresh_i2s_mclk_out_downstream(clocks, self);
                let active = clocks.i2s_mclk_out_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                }
                self.configure_mclk_out_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config(self, clocks: &mut ClockTree) -> Option<I2sMclkOutConfig> {
                clocks.i2s_mclk_out[self as usize]
            }
            pub fn request_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MCLK_OUT", self);
                if increment_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Enabling {:?}::MCLK_OUT", self);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                    self.enable_mclk_out_impl(clocks, true);
                }
            }
            pub fn release_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MCLK_OUT", self);
                if decrement_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Disabling {:?}::MCLK_OUT", self);
                    self.enable_mclk_out_impl(clocks, false);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config_frequency(self, config: I2sMclkOutConfig) -> u32 {
                match config {
                    I2sMclkOutConfig::Tx => self.tx_clk_frequency(),
                    I2sMclkOutConfig::Rx => self.rx_clk_frequency(),
                }
            }
            pub fn mclk_out_frequency(self) -> u32 {
                I2S_MCLK_OUT_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        impl LcdCamInstance {
            pub fn configure_lcd_clock(self, clocks: &mut ClockTree, config: LcdCamLcdClockConfig) {
                let old_config = clocks.lcd_cam_lcd_clock[self as usize].replace(config);
                refresh_lcd_cam_lcd_clock_downstream(clocks, self);
                let active = clocks.lcd_cam_lcd_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        LcdCamLcdClockSclk::XtalClk => request_xtal_clk(clocks),
                        LcdCamLcdClockSclk::PllD2 => request_pll_d2(clocks),
                        LcdCamLcdClockSclk::Pll160m => request_pll_160m(clocks),
                    }
                }
                self.configure_lcd_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        LcdCamLcdClockSclk::XtalClk => release_xtal_clk(clocks),
                        LcdCamLcdClockSclk::PllD2 => release_pll_d2(clocks),
                        LcdCamLcdClockSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn lcd_clock_config(self, clocks: &mut ClockTree) -> Option<LcdCamLcdClockConfig> {
                clocks.lcd_cam_lcd_clock[self as usize]
            }
            pub fn request_lcd_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::LCD_CLOCK", self);
                if increment_reference_count(&mut clocks.lcd_cam_lcd_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::LCD_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.lcd_cam_lcd_clock[self as usize]).sclk {
                        LcdCamLcdClockSclk::XtalClk => request_xtal_clk(clocks),
                        LcdCamLcdClockSclk::PllD2 => request_pll_d2(clocks),
                        LcdCamLcdClockSclk::Pll160m => request_pll_160m(clocks),
                    }
                    self.enable_lcd_clock_impl(clocks, true);
                }
            }
            pub fn release_lcd_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::LCD_CLOCK", self);
                if decrement_reference_count(&mut clocks.lcd_cam_lcd_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::LCD_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_lcd_clock_impl(clocks, false);
                    match unwrap!(clocks.lcd_cam_lcd_clock[self as usize]).sclk {
                        LcdCamLcdClockSclk::XtalClk => release_xtal_clk(clocks),
                        LcdCamLcdClockSclk::PllD2 => release_pll_d2(clocks),
                        LcdCamLcdClockSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn lcd_clock_config_frequency(config: LcdCamLcdClockConfig) -> u32 {
                (((match config.sclk {
                    LcdCamLcdClockSclk::XtalClk => xtal_clk_frequency(),
                    LcdCamLcdClockSclk::PllD2 => pll_d2_frequency(),
                    LcdCamLcdClockSclk::Pll160m => pll_160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn lcd_clock_frequency(self) -> u32 {
                LCD_CAM_LCD_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn lcd_clock_source_frequency(sclk: LcdCamLcdClockSclk) -> u32 {
                match sclk {
                    LcdCamLcdClockSclk::XtalClk => xtal_clk_frequency(),
                    LcdCamLcdClockSclk::PllD2 => pll_d2_frequency(),
                    LcdCamLcdClockSclk::Pll160m => pll_160m_frequency(),
                }
            }
            pub fn configure_cam_clock(self, clocks: &mut ClockTree, config: LcdCamCamClockConfig) {
                let old_config = clocks.lcd_cam_cam_clock[self as usize].replace(config);
                refresh_lcd_cam_cam_clock_downstream(clocks, self);
                let active = clocks.lcd_cam_cam_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        LcdCamCamClockSclk::XtalClk => request_xtal_clk(clocks),
                        LcdCamCamClockSclk::PllD2 => request_pll_d2(clocks),
                        LcdCamCamClockSclk::Pll160m => request_pll_160m(clocks),
                    }
                }
                self.configure_cam_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        LcdCamCamClockSclk::XtalClk => release_xtal_clk(clocks),
                        LcdCamCamClockSclk::PllD2 => release_pll_d2(clocks),
                        LcdCamCamClockSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn cam_clock_config(self, clocks: &mut ClockTree) -> Option<LcdCamCamClockConfig> {
                clocks.lcd_cam_cam_clock[self as usize]
            }
            pub fn request_cam_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::CAM_CLOCK", self);
                if increment_reference_count(&mut clocks.lcd_cam_cam_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::CAM_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.lcd_cam_cam_clock[self as usize]).sclk {
                        LcdCamCamClockSclk::XtalClk => request_xtal_clk(clocks),
                        LcdCamCamClockSclk::PllD2 => request_pll_d2(clocks),
                        LcdCamCamClockSclk::Pll160m => request_pll_160m(clocks),
                    }
                    self.enable_cam_clock_impl(clocks, true);
                }
            }
            pub fn release_cam_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::CAM_CLOCK", self);
                if decrement_reference_count(&mut clocks.lcd_cam_cam_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::CAM_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_cam_clock_impl(clocks, false);
                    match unwrap!(clocks.lcd_cam_cam_clock[self as usize]).sclk {
                        LcdCamCamClockSclk::XtalClk => release_xtal_clk(clocks),
                        LcdCamCamClockSclk::PllD2 => release_pll_d2(clocks),
                        LcdCamCamClockSclk::Pll160m => release_pll_160m(clocks),
                    }
                }
            }
            pub fn cam_clock_config_frequency(config: LcdCamCamClockConfig) -> u32 {
                (((match config.sclk {
                    LcdCamCamClockSclk::XtalClk => xtal_clk_frequency(),
                    LcdCamCamClockSclk::PllD2 => pll_d2_frequency(),
                    LcdCamCamClockSclk::Pll160m => pll_160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn cam_clock_frequency(self) -> u32 {
                LCD_CAM_CAM_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn cam_clock_source_frequency(sclk: LcdCamCamClockSclk) -> u32 {
                match sclk {
                    LcdCamCamClockSclk::XtalClk => xtal_clk_frequency(),
                    LcdCamCamClockSclk::PllD2 => pll_d2_frequency(),
                    LcdCamCamClockSclk::Pll160m => pll_160m_frequency(),
                }
            }
        }
        impl McpwmInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.mcpwm_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    request_crypto_pwm_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.mcpwm_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    release_crypto_pwm_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                crypto_pwm_clk_frequency()
            }
            pub fn function_clock_source_frequency(source: McpwmFunctionClockConfig) -> u32 {
                match source {
                    McpwmFunctionClockConfig::CryptoPwmClk => crypto_pwm_clk_frequency(),
                }
            }
        }
        impl RmtInstance {
            pub fn configure_sclk(self, clocks: &mut ClockTree, new_selector: RmtSclkConfig) {
                let old_selector = clocks.rmt_sclk[self as usize].replace(new_selector);
                refresh_rmt_sclk_downstream(clocks, self);
                let active = clocks.rmt_sclk_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                }
                self.configure_sclk_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn sclk_config(self, clocks: &mut ClockTree) -> Option<RmtSclkConfig> {
                clocks.rmt_sclk[self as usize]
            }
            pub fn request_sclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::SCLK", self);
                if increment_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Enabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => request_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.enable_sclk_impl(clocks, true);
                }
            }
            pub fn release_sclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::SCLK", self);
                if decrement_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Disabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_sclk_impl(clocks, false);
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                        RmtSclkConfig::RcFastClk => release_rc_fast_clk(clocks),
                        RmtSclkConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn sclk_config_frequency(config: RmtSclkConfig) -> u32 {
                match config {
                    RmtSclkConfig::ApbClk => apb_clk_frequency(),
                    RmtSclkConfig::RcFastClk => rc_fast_clk_frequency(),
                    RmtSclkConfig::XtalClk => xtal_clk_frequency(),
                }
            }
            pub fn sclk_frequency(self) -> u32 {
                RMT_SCLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn sclk_source_frequency(source: RmtSclkConfig) -> u32 {
                Self::sclk_config_frequency(source)
            }
        }
        impl SpiInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: SpiFunctionClockConfig,
            ) {
                let old_selector = clocks.spi_function_clock[self as usize].replace(new_selector);
                refresh_spi_function_clock_downstream(clocks, self);
                let active = clocks.spi_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::Apb => request_apb_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::Apb => release_apb_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<SpiFunctionClockConfig> {
                clocks.spi_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::Apb => request_apb_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::Apb => release_apb_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: SpiFunctionClockConfig) -> u32 {
                match config {
                    SpiFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    SpiFunctionClockConfig::Apb => apb_clk_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: SpiFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl TimgInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgFunctionClockConfig,
            ) {
                let old_selector = clocks.timg_function_clock[self as usize].replace(new_selector);
                refresh_timg_function_clock_downstream(clocks, self);
                let active = clocks.timg_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => request_apb_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => release_apb_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<TimgFunctionClockConfig> {
                clocks.timg_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => request_apb_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::ApbClk => release_apb_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: TimgFunctionClockConfig) -> u32 {
                match config {
                    TimgFunctionClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgFunctionClockConfig::ApbClk => apb_clk_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: TimgFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                refresh_uart_function_clock_downstream(clocks, self);
                let active = clocks.uart_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: UartFunctionClockConfig) -> u32 {
                (match config.sclk {
                    UartFunctionClockSclk::Apb => apb_clk_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                UART_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: UartFunctionClockSclk) -> u32 {
                match sclk {
                    UartFunctionClockSclk::Apb => apb_clk_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                }
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                refresh_uart_baud_rate_generator_downstream(clocks, self);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            pub fn baud_rate_generator_config_frequency(
                self,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency() * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self) -> u32 {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn request_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MEM_CLOCK", self);
                if increment_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::MEM_CLOCK", self);
                    request_uart_mem_clk(clocks);
                    self.enable_mem_clock_impl(clocks, true);
                }
            }
            pub fn release_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MEM_CLOCK", self);
                if decrement_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::MEM_CLOCK", self);
                    self.enable_mem_clock_impl(clocks, false);
                    release_uart_mem_clk(clocks);
                }
            }
            pub fn mem_clock_frequency(self) -> u32 {
                uart_mem_clk_frequency()
            }
            pub fn mem_clock_source_frequency() -> u32 {
                uart_mem_clk_frequency()
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `XTAL_CLK` configuration.
            pub xtal_clk: Option<XtalClkConfig>,
            /// `PLL_CLK` configuration.
            pub pll_clk: Option<PllClkConfig>,
            /// `SYSTEM_PRE_DIV` configuration.
            pub system_pre_div: Option<SystemPreDivConfig>,
            /// `CPU_PLL_DIV_OUT` configuration.
            pub cpu_pll_div_out: Option<CpuPllDivOutConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `RC_FAST_CLK_DIV_N` configuration.
            pub rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            /// `RTC_SLOW_CLK` configuration.
            pub rtc_slow_clk: Option<RtcSlowClkConfig>,
            /// `BLE_LP_CLK` configuration.
            pub ble_lp_clk: Option<BleLpClkConfig>,
            /// `RTC_FAST_CLK` configuration.
            pub rtc_fast_clk: Option<RtcFastClkConfig>,
            /// `LOW_POWER_CLK` configuration.
            pub low_power_clk: Option<LowPowerClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self, clocks: &mut ClockTree) {
                if let Some(config) = self.xtal_clk {
                    configure_xtal_clk(clocks, config);
                }
                if let Some(config) = self.pll_clk {
                    configure_pll_clk(clocks, config);
                }
                if let Some(config) = self.system_pre_div {
                    configure_system_pre_div(clocks, config);
                }
                if let Some(config) = self.cpu_pll_div_out {
                    configure_cpu_pll_div_out(clocks, config);
                }
                if let Some(config) = self.cpu_clk {
                    configure_cpu_clk(clocks, config);
                }
                if let Some(config) = self.rc_fast_clk_div_n {
                    configure_rc_fast_clk_div_n(clocks, config);
                }
                if let Some(config) = self.rtc_slow_clk {
                    configure_rtc_slow_clk(clocks, config);
                }
                if let Some(config) = self.ble_lp_clk {
                    configure_ble_lp_clk(clocks, config);
                }
                if let Some(config) = self.rtc_fast_clk {
                    configure_rtc_fast_clk(clocks, config);
                }
                if let Some(config) = self.low_power_clk {
                    configure_low_power_clk(clocks, config);
                }
                if let Some(config) = self.timg_calibration_clock {
                    configure_timg_calibration_clock(clocks, config);
                }
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
        fn refresh_xtal_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.xtal_clk {
                XTAL_CLK_FREQ_CACHE.store(
                    xtal_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_pll_clk_downstream(clocks);
            refresh_system_pre_div_in_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_rtc_fast_clk_downstream(clocks);
            refresh_low_power_clk_downstream(clocks);
            for child_instance in [I2cInstance::I2c0, I2cInstance::I2c1] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [I2sInstance::I2s0, I2sInstance::I2s1] {
                refresh_i2s_tx_clk_downstream(clocks, child_instance);
                refresh_i2s_rx_clk_downstream(clocks, child_instance);
            }
            for child_instance in [LcdCamInstance::LcdCam] {
                refresh_lcd_cam_lcd_clock_downstream(clocks, child_instance);
                refresh_lcd_cam_cam_clock_downstream(clocks, child_instance);
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2, SpiInstance::Spi3] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0, TimgInstance::Timg1] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_pll_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.pll_clk {
                PLL_CLK_FREQ_CACHE.store(
                    pll_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_pll_div_out_downstream(clocks);
            for child_instance in [I2sInstance::I2s0, I2sInstance::I2s1] {
                refresh_i2s_tx_clk_downstream(clocks, child_instance);
                refresh_i2s_rx_clk_downstream(clocks, child_instance);
            }
            for child_instance in [LcdCamInstance::LcdCam] {
                refresh_lcd_cam_lcd_clock_downstream(clocks, child_instance);
                refresh_lcd_cam_cam_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_downstream(clocks: &mut ClockTree) {
            refresh_system_pre_div_in_downstream(clocks);
            refresh_rc_fast_clk_div_n_downstream(clocks);
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_low_power_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [I2cInstance::I2c0, I2cInstance::I2c1] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_slow_clk_downstream(clocks: &mut ClockTree) {
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_system_pre_div_in_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.system_pre_div_in {
                SYSTEM_PRE_DIV_IN_FREQ_CACHE.store(
                    system_pre_div_in_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_system_pre_div_downstream(clocks);
        }
        fn refresh_system_pre_div_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.system_pre_div {
                SYSTEM_PRE_DIV_FREQ_CACHE.store(
                    system_pre_div_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_pll_div_out_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_pll_div_out {
                CPU_PLL_DIV_OUT_FREQ_CACHE.store(
                    cpu_pll_div_out_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_clk {
                CPU_CLK_FREQ_CACHE.store(
                    cpu_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apb_clk_downstream(clocks);
            refresh_crypto_pwm_clk_downstream(clocks);
            for child_instance in [I2sInstance::I2s0, I2sInstance::I2s1] {
                refresh_i2s_tx_clk_downstream(clocks, child_instance);
                refresh_i2s_rx_clk_downstream(clocks, child_instance);
            }
            for child_instance in [LcdCamInstance::LcdCam] {
                refresh_lcd_cam_lcd_clock_downstream(clocks, child_instance);
                refresh_lcd_cam_cam_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_div_n_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rc_fast_clk_div_n {
                RC_FAST_CLK_DIV_N_FREQ_CACHE.store(
                    rc_fast_clk_div_n_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_rtc_fast_clk_downstream(clocks);
        }
        fn refresh_rtc_slow_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_slow_clk {
                RTC_SLOW_CLK_FREQ_CACHE.store(
                    rtc_slow_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ble_lp_clk_downstream(clocks);
            refresh_low_power_clk_downstream(clocks);
        }
        fn refresh_ble_lp_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ble_lp_clk {
                BLE_LP_CLK_FREQ_CACHE.store(
                    ble_lp_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_rtc_fast_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_fast_clk {
                RTC_FAST_CLK_FREQ_CACHE.store(
                    rtc_fast_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_low_power_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.low_power_clk {
                LOW_POWER_CLK_FREQ_CACHE.store(
                    low_power_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_calibration_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.timg_calibration_clock {
                TIMG_CALIBRATION_CLOCK_FREQ_CACHE.store(
                    timg_calibration_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2c_function_clock_downstream(clocks: &mut ClockTree, instance: I2cInstance) {
            if let Some(config) = clocks.i2c_function_clock[instance as usize] {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    I2cInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2s_tx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_tx_clk[instance as usize] {
                I2S_TX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::tx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_rx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_rx_clk[instance as usize] {
                I2S_RX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::rx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_mclk_out_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_mclk_out[instance as usize] {
                I2S_MCLK_OUT_FREQ_CACHE[instance as usize].store(
                    instance.mclk_out_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lcd_cam_lcd_clock_downstream(clocks: &mut ClockTree, instance: LcdCamInstance) {
            if let Some(config) = clocks.lcd_cam_lcd_clock[instance as usize] {
                LCD_CAM_LCD_CLOCK_FREQ_CACHE[instance as usize].store(
                    LcdCamInstance::lcd_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lcd_cam_cam_clock_downstream(clocks: &mut ClockTree, instance: LcdCamInstance) {
            if let Some(config) = clocks.lcd_cam_cam_clock[instance as usize] {
                LCD_CAM_CAM_CLOCK_FREQ_CACHE[instance as usize].store(
                    LcdCamInstance::cam_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_apb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apb_clk {
                APB_CLK_FREQ_CACHE.store(
                    apb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2, SpiInstance::Spi3] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0, TimgInstance::Timg1] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_crypto_pwm_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.crypto_pwm_clk {
                CRYPTO_PWM_CLK_FREQ_CACHE.store(
                    crypto_pwm_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_rmt_sclk_downstream(clocks: &mut ClockTree, instance: RmtInstance) {
            if let Some(config) = clocks.rmt_sclk[instance as usize] {
                RMT_SCLK_FREQ_CACHE[instance as usize].store(
                    RmtInstance::sclk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_spi_function_clock_downstream(clocks: &mut ClockTree, instance: SpiInstance) {
            if let Some(config) = clocks.spi_function_clock[instance as usize] {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    SpiInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_function_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_function_clock[instance as usize] {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_uart_function_clock_downstream(clocks: &mut ClockTree, instance: UartInstance) {
            if let Some(config) = clocks.uart_function_clock[instance as usize] {
                UART_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    UartInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_uart_baud_rate_generator_downstream(clocks, instance);
        }
        fn refresh_uart_baud_rate_generator_downstream(
            clocks: &mut ClockTree,
            instance: UartInstance,
        ) {
            if let Some(config) = clocks.uart_baud_rate_generator[instance as usize] {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[instance as usize].store(
                    instance.baud_rate_generator_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AES peripheral clock signal
            Aes,
            /// AHB_GDMA peripheral clock signal
            AhbGdma,
            /// APB_SAR_ADC peripheral clock signal
            ApbSarAdc,
            /// DEDICATED_GPIO peripheral clock signal
            DedicatedGpio,
            /// DS peripheral clock signal
            Ds,
            /// GPIO_SD peripheral clock signal
            GpioSd,
            /// HMAC peripheral clock signal
            Hmac,
            /// I2C_EXT0 peripheral clock signal
            I2cExt0,
            /// I2C_EXT1 peripheral clock signal
            I2cExt1,
            /// I2S0 peripheral clock signal
            I2s0,
            /// I2S1 peripheral clock signal
            I2s1,
            /// LCD_CAM peripheral clock signal
            LcdCam,
            /// LEDC peripheral clock signal
            Ledc,
            /// MCPWM0 peripheral clock signal
            Mcpwm0,
            /// MCPWM1 peripheral clock signal
            Mcpwm1,
            /// PCNT peripheral clock signal
            Pcnt,
            /// PERI_BACKUP peripheral clock signal
            PeriBackup,
            /// RMT peripheral clock signal
            Rmt,
            /// RSA peripheral clock signal
            Rsa,
            /// SDIO_HOST peripheral clock signal
            SdioHost,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SPI3 peripheral clock signal
            Spi3,
            /// SYSTIMER peripheral clock signal
            Systimer,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TIMG1 peripheral clock signal
            Timg1,
            /// TWAI0 peripheral clock signal
            Twai0,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART2 peripheral clock signal
            Uart2,
            /// UART_MEM peripheral clock signal
            UartMem,
            /// UHCI0 peripheral clock signal
            Uhci0,
            /// USB_DEVICE peripheral clock signal
            UsbDevice,
            /// USB_FS peripheral clock signal
            UsbFs,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] = &[
                Self::Systimer,
                Self::Timg0,
                Self::Uart0,
                Self::UartMem,
                Self::UsbDevice,
            ];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::Aes,
                Self::AhbGdma,
                Self::ApbSarAdc,
                Self::DedicatedGpio,
                Self::Ds,
                Self::GpioSd,
                Self::Hmac,
                Self::I2cExt0,
                Self::I2cExt1,
                Self::I2s0,
                Self::I2s1,
                Self::LcdCam,
                Self::Ledc,
                Self::Mcpwm0,
                Self::Mcpwm1,
                Self::Pcnt,
                Self::PeriBackup,
                Self::Rmt,
                Self::Rsa,
                Self::SdioHost,
                Self::Sha,
                Self::Spi2,
                Self::Spi3,
                Self::Systimer,
                Self::Timg0,
                Self::Timg1,
                Self::Twai0,
                Self::Uart0,
                Self::Uart1,
                Self::Uart2,
                Self::UartMem,
                Self::Uhci0,
                Self::UsbDevice,
                Self::UsbFs,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_aes_clk_en().bit(enable));
                }
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.dma_clk_en().bit(enable));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.apb_saradc_clk_en().bit(enable));
                }
                Peripheral::DedicatedGpio => {
                    crate::peripherals::SYSTEM::regs()
                        .cpu_peri_clk_en()
                        .modify(|_, w| w.dedicated_gpio_clk_en().bit(enable));
                }
                Peripheral::Ds => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_ds_clk_en().bit(enable));
                }
                Peripheral::GpioSd => {
                    crate::peripherals::GPIO_SD::regs()
                        .clock_gate()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Hmac => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_hmac_clk_en().bit(enable));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2c_ext0_clk_en().bit(enable));
                }
                Peripheral::I2cExt1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2c_ext1_clk_en().bit(enable));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2s0_clk_en().bit(enable));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2s1_clk_en().bit(enable));
                }
                Peripheral::LcdCam => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.lcd_cam_clk_en().bit(enable));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.ledc_clk_en().bit(enable));
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.pwm0_clk_en().bit(enable));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.pwm1_clk_en().bit(enable));
                }
                Peripheral::Pcnt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.pcnt_clk_en().bit(enable));
                }
                Peripheral::PeriBackup => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.peri_backup_clk_en().bit(enable));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.rmt_clk_en().bit(enable));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_rsa_clk_en().bit(enable));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.sdio_host_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_sha_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.spi2_clk_en().bit(enable));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.spi3_clk_en().bit(enable));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.systimer_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.timergroup_clk_en().bit(enable));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.timergroup1_clk_en().bit(enable));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.twai_clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart1_clk_en().bit(enable));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.uart2_clk_en().bit(enable));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_mem_clk_en().bit(enable));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uhci0_clk_en().bit(enable));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.usb_device_clk_en().bit(enable));
                }
                Peripheral::UsbFs => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.usb_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_aes_rst().bit(reset));
                }
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.dma_rst().bit(reset));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.apb_saradc_rst().bit(reset));
                }
                Peripheral::DedicatedGpio => {
                    crate::peripherals::SYSTEM::regs()
                        .cpu_peri_rst_en()
                        .modify(|_, w| w.dedicated_gpio_rst().bit(reset));
                }
                Peripheral::Ds => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_ds_rst().bit(reset));
                }
                Peripheral::GpioSd => {
                    let _ = reset;
                }
                Peripheral::Hmac => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_hmac_rst().bit(reset));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2c_ext0_rst().bit(reset));
                }
                Peripheral::I2cExt1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2c_ext1_rst().bit(reset));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2s0_rst().bit(reset));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2s1_rst().bit(reset));
                }
                Peripheral::LcdCam => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.lcd_cam_rst().bit(reset));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.ledc_rst().bit(reset));
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.pwm0_rst().bit(reset));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.pwm1_rst().bit(reset));
                }
                Peripheral::Pcnt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.pcnt_rst().bit(reset));
                }
                Peripheral::PeriBackup => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.peri_backup_rst().bit(reset));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.rmt_rst().bit(reset));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_rsa_rst().bit(reset));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.sdio_host_rst().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_sha_rst().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.spi2_rst().bit(reset));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.spi3_rst().bit(reset));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.systimer_rst().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.timergroup_rst().bit(reset));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.timergroup1_rst().bit(reset));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.twai_rst().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_rst().bit(reset));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart1_rst().bit(reset));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.uart2_rst().bit(reset));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_mem_rst().bit(reset));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uhci0_rst().bit(reset));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.usb_device_rst().bit(reset));
                }
                Peripheral::UsbFs => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.usb_rst().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x3FC88000..0x3FD00000
    };
    (size as str, "DRAM") => {
        "491520"
    };
    ("DRAM2_UNINIT") => {
        0x3FCDB700..0x3FCED710
    };
    (size as str, "DRAM2_UNINIT") => {
        "73744"
    };
    ("IROM") => {
        0x42000000..0x44000000
    };
    (size as str, "IROM") => {
        "33554432"
    };
    ("DROM") => {
        0x3C000000..0x3E000000
    };
    (size as str, "DROM") => {
        "33554432"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)); _for_each_inner_i2c_master!((1, I2C1, I2cExt1, I2CEXT1_SCL,
        I2CEXT1_SDA)); _for_each_inner_i2c_master!((all(0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA), (1, I2C1, I2cExt1, I2CEXT1_SCL, I2CEXT1_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2S driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $mclk:ident, $bclk:ident, $ws:ident, $bclk_rx:ident,
/// $ws_rx:ident, [$($dout:ident),*], [$($din:ident),*], $pdm_tx:literal, $pdm_rx:literal,
/// $pcm2pdm:literal, $pdm2pcm:literal)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the I2S instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$mclk`: the MCLK output signal (a placeholder on chips without a GPIO-matrix MCLK).
/// - `$bclk`, `$ws`: TX bit clock and word select output signals.
/// - `$bclk_rx`, `$ws_rx`: RX bit clock and word select output signals.
/// - `$dout`, `$din`: data-out and data-in signal names.
/// - `$pdm_tx`, `$pdm_rx`: whether the instance supports PDM TX/RX.
/// - `$pcm2pdm`, `$pdm2pcm`: whether the instance supports the hardware PCM<->PDM format conversion
///   filter on TX/RX.
///
/// Example data:
/// - `(I2S0, I2s0, I2S_MCLK, I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true,
///   true, true, true)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2s {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2s { $(($pattern) => $code;)* ($other : tt) => {} }
        _for_each_inner_i2s!((I2S0)); _for_each_inner_i2s!((I2S1));
        _for_each_inner_i2s!((I2S0, I2s0, I2S0_MCLK, I2S0O_BCK, I2S0O_WS, I2S0I_BCK,
        I2S0I_WS, [I2S0O_SD, I2S0O_SD1], [I2S0I_SD, I2S0I_SD1, I2S0I_SD2, I2S0I_SD3],
        true, true, true, true)); _for_each_inner_i2s!((I2S1, I2s1, I2S1_MCLK, I2S1O_BCK,
        I2S1O_WS, I2S1I_BCK, I2S1I_WS, [I2S1O_SD], [I2S1I_SD], true, true, false,
        false)); _for_each_inner_i2s!((names(I2S0), (I2S1)));
        _for_each_inner_i2s!((all(I2S0, I2s0, I2S0_MCLK, I2S0O_BCK, I2S0O_WS, I2S0I_BCK,
        I2S0I_WS, [I2S0O_SD, I2S0O_SD1], [I2S0I_SD, I2S0I_SD1, I2S0I_SD2, I2S0I_SD3],
        true, true, true, true), (I2S1, I2s1, I2S1_MCLK, I2S1O_BCK, I2S1O_WS, I2S1I_BCK,
        I2S1I_WS, [I2S1O_SD], [I2S1I_SD], true, true, false, false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true)); _for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD,
        U1CTS, U1RTS, wakeup_source = true)); _for_each_inner_uart!((2, UART2, Uart2,
        U2RXD, U2TXD, U2CTS, U2RTS, wakeup_source = false));
        _for_each_inner_uart!((all(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true), (1, UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS,
        wakeup_source = true), (2, UART2, Uart2, U2RXD, U2TXD, U2CTS, U2RTS,
        wakeup_source = false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2)); _for_each_inner_spi_master!((SPI3));
        _for_each_inner_spi_master!((SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2,
        FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD, FSPIIO4, FSPIIO5,
        FSPIIO6, FSPIIO7], true)); _for_each_inner_spi_master!((SPI3, Spi3,
        SPI3_CLK[SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q, SPI3_WP, SPI3_HD],
        true)); _for_each_inner_spi_master!((names(SPI2), (SPI3)));
        _for_each_inner_spi_master!((all(SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2,
        FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD, FSPIIO4, FSPIIO5,
        FSPIIO6, FSPIIO7], true), (SPI3, Spi3, SPI3_CLK[SPI3_CS0, SPI3_CS1, SPI3_CS2]
        [SPI3_D, SPI3_Q, SPI3_WP, SPI3_HD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2)); _for_each_inner_spi_slave!((SPI3));
        _for_each_inner_spi_slave!((SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0));
        _for_each_inner_spi_slave!((SPI3, Spi3, SPI3_CLK, SPI3_D, SPI3_Q, SPI3_CS0));
        _for_each_inner_spi_slave!((names(SPI2), (SPI3)));
        _for_each_inner_spi_slave!((all(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0),
        (SPI3, Spi3, SPI3_CLK, SPI3_D, SPI3_Q, SPI3_CS0)));
    };
}
/// This macro can be used to generate code for each PCNT unit.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has four options for its "Individual matcher" case:
///
/// - `names`: `($instance:ident)`
/// - `all`: `($peri:ident, $variant:ident, $sys:ident, $regs:ident, $unit:literal,
///   $interrupt:ident, $sig_ch0:ident, $sig_ch1:ident, $ctrl_ch0:ident, $ctrl_ch1:ident)`
/// - `interrupt`: `($interrupt:ident)` (repeated: one ident per unique IRQ)
/// - `regs`: `($regs:ident)` (repeated: one ident per register block)
///
/// Macro fragments:
///
/// - `$peri`: unit singleton name (`PCNT0_UNIT0`, `PCNT1_UNIT0`, …)
/// - `$variant`: `AnyPcntUnit` enum variant (`Pcnt0Unit0`, `Pcnt1Unit0`, …)
/// - `$sys`: `esp_hal::system::Peripheral` variant for clocks
/// - `$regs`: register-block singleton (`PCNT`, `PCNT1`)
/// - `$unit`: hardware unit index within that register block
/// - `$interrupt`: shared peripheral interrupt
/// - `$sig_ch0`, `$sig_ch1`, `$ctrl_ch0`, `$ctrl_ch1`: GPIO matrix input signals
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_pcnt_unit {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_pcnt_unit { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_pcnt_unit!((PCNT0_UNIT0));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT0, Pcnt0Unit0, Pcnt, PCNT, 0, PCNT,
        PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1, Pcnt0Unit1, Pcnt, PCNT, 1, PCNT,
        PCNT1_SIG_CH0, PCNT1_SIG_CH1, PCNT1_CTRL_CH0, PCNT1_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT,
        PCNT2_SIG_CH0, PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3, Pcnt0Unit3, Pcnt, PCNT, 3, PCNT,
        PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0, PCNT3_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT)); _for_each_inner_pcnt_unit!((PCNT));
        _for_each_inner_pcnt_unit!((names(PCNT0_UNIT0), (PCNT0_UNIT1), (PCNT0_UNIT2),
        (PCNT0_UNIT3))); _for_each_inner_pcnt_unit!((all(PCNT0_UNIT0, Pcnt0Unit0, Pcnt,
        PCNT, 0, PCNT, PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1),
        (PCNT0_UNIT1, Pcnt0Unit1, Pcnt, PCNT, 1, PCNT, PCNT1_SIG_CH0, PCNT1_SIG_CH1,
        PCNT1_CTRL_CH0, PCNT1_CTRL_CH1), (PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT,
        PCNT2_SIG_CH0, PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1), (PCNT0_UNIT3,
        Pcnt0Unit3, Pcnt, PCNT, 3, PCNT, PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0,
        PCNT3_CTRL_CH1))); _for_each_inner_pcnt_unit!((interrupt(PCNT)));
        _for_each_inner_pcnt_unit!((regs(PCNT)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO1 peripheral singleton"]
        GPIO1 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO4 peripheral singleton"]
        GPIO4 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO6 peripheral singleton"]
        GPIO6 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO8 peripheral singleton"]
        GPIO8 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO10 peripheral singleton"]
        GPIO10 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO12 peripheral singleton"]
        GPIO12 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO13 peripheral singleton"] GPIO13 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO14 peripheral singleton"]
        GPIO14 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO16 peripheral singleton"]
        GPIO16 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO18 peripheral singleton"]
        GPIO18 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO19 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO20 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO21 peripheral singleton"] GPIO21 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO26 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO26 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO27 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO27 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO28 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO28 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO29 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO29 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO30 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO30 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO31 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO31 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO32 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO32 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO33 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO33 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO38 peripheral singleton"]
        GPIO38 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO39 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO39 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO40 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO40 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO41 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO41 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO42 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO42 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO43 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO43 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO44 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO44 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO45 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO45 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO46 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO46 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO47 peripheral singleton"]
        GPIO47 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO48 peripheral singleton"] GPIO48 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual(DMA_IN_CH0 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH0 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH1 peripheral singleton"]
        DMA_CH1 <= virtual(DMA_IN_CH1 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH1 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH2 peripheral singleton"]
        DMA_CH2 <= virtual(DMA_IN_CH2 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH2 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH3 peripheral singleton"]
        DMA_CH3 <= virtual(DMA_IN_CH3 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH3 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH4 peripheral singleton"]
        DMA_CH4 <= virtual(DMA_IN_CH4 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH4 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT0 peripheral singleton"] PCNT0_UNIT0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH0 peripheral singleton"]
        SDM_CH0 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH1 peripheral singleton"] SDM_CH1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH2 peripheral singleton"]
        SDM_CH2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH4 peripheral singleton"]
        SDM_CH4 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH5 peripheral singleton"] SDM_CH5 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH6 peripheral singleton"]
        SDM_CH6 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH7 peripheral singleton"] SDM_CH7 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "AES peripheral singleton"] AES
        <= AES(AES : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "ASSIST_DEBUG peripheral singleton"] ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA peripheral singleton"] DMA
        <= DMA() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "DS peripheral singleton"] DS <= DS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EFUSE peripheral singleton"]
        EFUSE <= EFUSE() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "EXTMEM peripheral singleton"] EXTMEM <= EXTMEM() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO peripheral singleton"]
        GPIO <= GPIO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "HMAC peripheral singleton"]
        HMAC <= HMAC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C0 peripheral singleton"]
        I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C1 peripheral singleton"] I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2S0 peripheral singleton"]
        I2S0 <= I2S0(I2S0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "I2S1 peripheral singleton"] I2S1 <= I2S1(I2S1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE1 peripheral singleton"] INTERRUPT_CORE1 <= INTERRUPT_CORE1()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LCD_CAM peripheral singleton"]
        LCD_CAM <= LCD_CAM() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "LEDC peripheral singleton"] LEDC <= LEDC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LPWR peripheral singleton"]
        LPWR <= RTC_CNTL() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RTC_TIMER peripheral singleton"] RTC_TIMER <= RTC_CNTL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "MCPWM0 peripheral singleton"]
        MCPWM0 <= MCPWM0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MCPWM1 peripheral singleton"] MCPWM1 <= MCPWM1() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PCNT peripheral singleton"]
        PCNT <= PCNT(PCNT : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "PERI_BACKUP peripheral singleton"] PERI_BACKUP <= PERI_BACKUP()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RMT peripheral singleton"] RMT <= RMT() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RNG peripheral singleton"] RNG
        <= RNG() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RSA peripheral singleton"] RSA <= RSA(RSA : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RTC_CNTL peripheral singleton"]
        RTC_CNTL <= RTC_CNTL() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "LP_I2C0 peripheral singleton"] LP_I2C0 <= RTC_I2C() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RTC_IO peripheral singleton"]
        RTC_IO <= RTC_IO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SDHOST peripheral singleton"] SDHOST <= SDHOST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SENS peripheral singleton"]
        SENS <= SENS() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SENSITIVE peripheral singleton"] SENSITIVE <= SENSITIVE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SHA peripheral singleton"] SHA
        <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI3 peripheral singleton"]
        SPI3 <= SPI3(SPI3 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SYSTEM peripheral singleton"] SYSTEM <= SYSTEM() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTIMER peripheral singleton"]
        SYSTIMER <= SYSTIMER() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG1 peripheral singleton"]
        TIMG1 <= TIMG1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TWAI0 peripheral singleton"] TWAI0 <= TWAI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART0 peripheral singleton"]
        UART0 <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART1 peripheral singleton"] UART1 <= UART1(UART1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UHCI0 peripheral singleton"] UHCI0 <= UHCI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "USB_FS peripheral singleton"]
        USB_FS <= USB_FS(USB : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE :
        { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "USB_WRAP peripheral singleton"] USB_WRAP <= USB_WRAP() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "WCL peripheral singleton"] WCL
        <= WCL() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "XTS_AES peripheral singleton"] XTS_AES <= XTS_AES() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ADC1 peripheral singleton"]
        ADC1 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ADC2 peripheral singleton"] ADC2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "BT peripheral singleton"] BT <=
        virtual(BT_BB : { bind_bb_interrupt, enable_bb_interrupt, disable_bb_interrupt },
        RWBLE : { bind_rwble_interrupt, enable_rwble_interrupt, disable_rwble_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "CPU_CTRL peripheral singleton"] CPU_CTRL <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FLASH peripheral singleton"]
        FLASH <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PSRAM peripheral singleton"]
        PSRAM <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ULP_RISCV_CORE peripheral singleton"] ULP_RISCV_CORE <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "WIFI peripheral singleton"]
        WIFI <= virtual(WIFI_MAC : { bind_mac_interrupt, enable_mac_interrupt,
        disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt, enable_pwr_interrupt,
        disable_pwr_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "IPC peripheral singleton"] IPC <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((GPIO0)); _for_each_inner_peripheral!((GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO15));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO16));
        _for_each_inner_peripheral!((GPIO17)); _for_each_inner_peripheral!((GPIO18));
        _for_each_inner_peripheral!((GPIO19)); _for_each_inner_peripheral!((GPIO20));
        _for_each_inner_peripheral!((GPIO21)); _for_each_inner_peripheral!((GPIO26));
        _for_each_inner_peripheral!((GPIO27)); _for_each_inner_peripheral!((GPIO28));
        _for_each_inner_peripheral!((GPIO29)); _for_each_inner_peripheral!((GPIO30));
        _for_each_inner_peripheral!((GPIO31)); _for_each_inner_peripheral!((GPIO32));
        _for_each_inner_peripheral!((GPIO33)); _for_each_inner_peripheral!((GPIO34));
        _for_each_inner_peripheral!((GPIO35)); _for_each_inner_peripheral!((GPIO36));
        _for_each_inner_peripheral!((GPIO37)); _for_each_inner_peripheral!((GPIO38));
        _for_each_inner_peripheral!((GPIO39)); _for_each_inner_peripheral!((GPIO40));
        _for_each_inner_peripheral!((GPIO41)); _for_each_inner_peripheral!((GPIO42));
        _for_each_inner_peripheral!((GPIO43)); _for_each_inner_peripheral!((GPIO44));
        _for_each_inner_peripheral!((GPIO45)); _for_each_inner_peripheral!((GPIO46));
        _for_each_inner_peripheral!((GPIO47)); _for_each_inner_peripheral!((GPIO48));
        _for_each_inner_peripheral!((DMA_CH0(unstable)));
        _for_each_inner_peripheral!((DMA_CH1(unstable)));
        _for_each_inner_peripheral!((DMA_CH2(unstable)));
        _for_each_inner_peripheral!((DMA_CH3(unstable)));
        _for_each_inner_peripheral!((DMA_CH4(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT0(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT1(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT2(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT3(unstable)));
        _for_each_inner_peripheral!((SDM_CH0(unstable)));
        _for_each_inner_peripheral!((SDM_CH1(unstable)));
        _for_each_inner_peripheral!((SDM_CH2(unstable)));
        _for_each_inner_peripheral!((SDM_CH3(unstable)));
        _for_each_inner_peripheral!((SDM_CH4(unstable)));
        _for_each_inner_peripheral!((SDM_CH5(unstable)));
        _for_each_inner_peripheral!((SDM_CH6(unstable)));
        _for_each_inner_peripheral!((SDM_CH7(unstable)));
        _for_each_inner_peripheral!((AES(unstable)));
        _for_each_inner_peripheral!((APB_CTRL(unstable)));
        _for_each_inner_peripheral!((APB_SARADC(unstable)));
        _for_each_inner_peripheral!((ASSIST_DEBUG(unstable)));
        _for_each_inner_peripheral!((DMA(unstable)));
        _for_each_inner_peripheral!((DS(unstable)));
        _for_each_inner_peripheral!((EXTMEM(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((GPIO_SD(unstable)));
        _for_each_inner_peripheral!((HMAC(unstable)));
        _for_each_inner_peripheral!((I2C_ANA_MST(unstable)));
        _for_each_inner_peripheral!((I2C0)); _for_each_inner_peripheral!((I2C1));
        _for_each_inner_peripheral!((I2S0(unstable)));
        _for_each_inner_peripheral!((I2S1(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE1(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LCD_CAM(unstable)));
        _for_each_inner_peripheral!((LEDC(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((RTC_TIMER(unstable)));
        _for_each_inner_peripheral!((MCPWM0(unstable)));
        _for_each_inner_peripheral!((MCPWM1(unstable)));
        _for_each_inner_peripheral!((PCNT(unstable)));
        _for_each_inner_peripheral!((PERI_BACKUP(unstable)));
        _for_each_inner_peripheral!((RMT(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((RSA(unstable)));
        _for_each_inner_peripheral!((RTC_CNTL(unstable)));
        _for_each_inner_peripheral!((LP_I2C0(unstable)));
        _for_each_inner_peripheral!((RTC_IO(unstable)));
        _for_each_inner_peripheral!((SDHOST(unstable)));
        _for_each_inner_peripheral!((SENS(unstable)));
        _for_each_inner_peripheral!((SENSITIVE(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((SPI0(unstable)));
        _for_each_inner_peripheral!((SPI1(unstable)));
        _for_each_inner_peripheral!((SPI2)); _for_each_inner_peripheral!((SPI3));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((SYSTIMER(unstable)));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((TIMG1(unstable)));
        _for_each_inner_peripheral!((TWAI0(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((UART2));
        _for_each_inner_peripheral!((UHCI0(unstable)));
        _for_each_inner_peripheral!((USB_FS(unstable)));
        _for_each_inner_peripheral!((USB_DEVICE(unstable)));
        _for_each_inner_peripheral!((WCL(unstable)));
        _for_each_inner_peripheral!((XTS_AES(unstable)));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((ADC2(unstable)));
        _for_each_inner_peripheral!((BT(unstable)));
        _for_each_inner_peripheral!((CPU_CTRL(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((GPIO_DEDICATED(unstable)));
        _for_each_inner_peripheral!((PSRAM(unstable)));
        _for_each_inner_peripheral!((ULP_RISCV_CORE(unstable)));
        _for_each_inner_peripheral!((WIFI));
        _for_each_inner_peripheral!((IPC(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable)));
        _for_each_inner_peripheral!((SPI2, Spi2, 0, AhbGdmaChannel));
        _for_each_inner_peripheral!((SPI3, Spi3, 1, AhbGdmaChannel));
        _for_each_inner_peripheral!((UHCI0, Uhci0, 2, AhbGdmaChannel));
        _for_each_inner_peripheral!((I2S0, I2s0, 3, AhbGdmaChannel));
        _for_each_inner_peripheral!((I2S1, I2s1, 4, AhbGdmaChannel));
        _for_each_inner_peripheral!((LCD_CAM, LcdCam, 5, AhbGdmaChannel));
        _for_each_inner_peripheral!((AES, Aes, 6, AhbGdmaChannel));
        _for_each_inner_peripheral!((SHA, Sha, 7, AhbGdmaChannel));
        _for_each_inner_peripheral!((APB_SARADC, ApbSaradc, 8, AhbGdmaChannel));
        _for_each_inner_peripheral!((RMT, Rmt, 9, AhbGdmaChannel));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "GPIO21 peripheral singleton"] GPIO21 <= virtual()), (@ peri_type #[doc =
        "GPIO26 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO26 <= virtual()), (@ peri_type #[doc =
        "GPIO27 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO27 <= virtual()), (@ peri_type #[doc =
        "GPIO28 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO28 <= virtual()), (@ peri_type #[doc =
        "GPIO29 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO29 <= virtual()), (@ peri_type #[doc =
        "GPIO30 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO30 <= virtual()), (@ peri_type #[doc =
        "GPIO31 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO31 <= virtual()), (@ peri_type #[doc =
        "GPIO32 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO32 <= virtual()), (@ peri_type #[doc =
        "GPIO33 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO33 <= virtual()), (@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()), (@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()), (@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()), (@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with Octal SPI flash.</li>"] #[doc
        = "<li>This pin may be reserved for interfacing with Octal SPI PSRAM.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()), (@ peri_type #[doc =
        "GPIO38 peripheral singleton"] GPIO38 <= virtual()), (@ peri_type #[doc =
        "GPIO39 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO39 <= virtual()), (@ peri_type #[doc =
        "GPIO40 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO40 <= virtual()), (@ peri_type #[doc =
        "GPIO41 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO41 <= virtual()), (@ peri_type #[doc =
        "GPIO42 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO42 <= virtual()), (@ peri_type #[doc =
        "GPIO43 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO43 <= virtual()), (@ peri_type #[doc =
        "GPIO44 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO44 <= virtual()), (@ peri_type #[doc =
        "GPIO45 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO45 <= virtual()), (@ peri_type #[doc =
        "GPIO46 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO46 <= virtual()), (@ peri_type #[doc =
        "GPIO47 peripheral singleton"] GPIO47 <= virtual()), (@ peri_type #[doc =
        "GPIO48 peripheral singleton"] GPIO48 <= virtual()), (@ peri_type #[doc =
        "DMA_CH0 peripheral singleton"] DMA_CH0 <= virtual(DMA_IN_CH0 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH0 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual(DMA_IN_CH1 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH1 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH2 peripheral singleton"] DMA_CH2 <= virtual(DMA_IN_CH2 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH2 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH3 peripheral singleton"] DMA_CH3 <= virtual(DMA_IN_CH3 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH3 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH4 peripheral singleton"] DMA_CH4 <= virtual(DMA_IN_CH4 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH4 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "PCNT0_UNIT0 peripheral singleton"] PCNT0_UNIT0 <= virtual() (unstable)), (@
        peri_type #[doc = "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1 <= virtual()
        (unstable)), (@ peri_type #[doc = "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2
        <= virtual() (unstable)), (@ peri_type #[doc =
        "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3 <= virtual() (unstable)), (@
        peri_type #[doc = "SDM_CH0 peripheral singleton"] SDM_CH0 <= virtual()
        (unstable)), (@ peri_type #[doc = "SDM_CH1 peripheral singleton"] SDM_CH1 <=
        virtual() (unstable)), (@ peri_type #[doc = "SDM_CH2 peripheral singleton"]
        SDM_CH2 <= virtual() (unstable)), (@ peri_type #[doc =
        "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual() (unstable)), (@ peri_type
        #[doc = "SDM_CH4 peripheral singleton"] SDM_CH4 <= virtual() (unstable)), (@
        peri_type #[doc = "SDM_CH5 peripheral singleton"] SDM_CH5 <= virtual()
        (unstable)), (@ peri_type #[doc = "SDM_CH6 peripheral singleton"] SDM_CH6 <=
        virtual() (unstable)), (@ peri_type #[doc = "SDM_CH7 peripheral singleton"]
        SDM_CH7 <= virtual() (unstable)), (@ peri_type #[doc =
        "AES peripheral singleton"] AES <= AES(AES : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)), (@
        peri_type #[doc = "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC()
        (unstable)), (@ peri_type #[doc = "ASSIST_DEBUG peripheral singleton"]
        ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (@ peri_type #[doc =
        "DMA peripheral singleton"] DMA <= DMA() (unstable)), (@ peri_type #[doc =
        "DS peripheral singleton"] DS <= DS() (unstable)), (@ peri_type #[doc =
        "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)), (@ peri_type #[doc =
        "EXTMEM peripheral singleton"] EXTMEM <= EXTMEM() (unstable)), (@ peri_type #[doc
        = "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE() (unstable)), (@
        peri_type #[doc = "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)), (@
        peri_type #[doc = "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD()
        (unstable)), (@ peri_type #[doc = "HMAC peripheral singleton"] HMAC <= HMAC()
        (unstable)), (@ peri_type #[doc = "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST
        <= I2C_ANA_MST() (unstable)), (@ peri_type #[doc = "I2C0 peripheral singleton"]
        I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "I2C1 peripheral singleton"]
        I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "I2S0 peripheral singleton"]
        I2S0 <= I2S0(I2S0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "I2S1 peripheral singleton"] I2S1 <= I2S1(I2S1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable)), (@ peri_type #[doc = "INTERRUPT_CORE1 peripheral singleton"]
        INTERRUPT_CORE1 <= INTERRUPT_CORE1() (unstable)), (@ peri_type #[doc =
        "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)), (@ peri_type #[doc
        = "LCD_CAM peripheral singleton"] LCD_CAM <= LCD_CAM() (unstable)), (@ peri_type
        #[doc = "LEDC peripheral singleton"] LEDC <= LEDC() (unstable)), (@ peri_type
        #[doc = "LPWR peripheral singleton"] LPWR <= RTC_CNTL() (unstable)), (@ peri_type
        #[doc = "RTC_TIMER peripheral singleton"] RTC_TIMER <= RTC_CNTL() (unstable)), (@
        peri_type #[doc = "MCPWM0 peripheral singleton"] MCPWM0 <= MCPWM0() (unstable)),
        (@ peri_type #[doc = "MCPWM1 peripheral singleton"] MCPWM1 <= MCPWM1()
        (unstable)), (@ peri_type #[doc = "PCNT peripheral singleton"] PCNT <= PCNT(PCNT
        : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "PERI_BACKUP peripheral singleton"] PERI_BACKUP
        <= PERI_BACKUP() (unstable)), (@ peri_type #[doc = "RMT peripheral singleton"]
        RMT <= RMT() (unstable)), (@ peri_type #[doc = "RNG peripheral singleton"] RNG <=
        RNG() (unstable)), (@ peri_type #[doc = "RSA peripheral singleton"] RSA <=
        RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "RTC_CNTL peripheral singleton"] RTC_CNTL <=
        RTC_CNTL() (unstable)), (@ peri_type #[doc = "LP_I2C0 peripheral singleton"]
        LP_I2C0 <= RTC_I2C() (unstable)), (@ peri_type #[doc =
        "RTC_IO peripheral singleton"] RTC_IO <= RTC_IO() (unstable)), (@ peri_type #[doc
        = "SDHOST peripheral singleton"] SDHOST <= SDHOST() (unstable)), (@ peri_type
        #[doc = "SENS peripheral singleton"] SENS <= SENS() (unstable)), (@ peri_type
        #[doc = "SENSITIVE peripheral singleton"] SENSITIVE <= SENSITIVE() (unstable)),
        (@ peri_type #[doc = "SHA peripheral singleton"] SHA <= SHA(SHA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "SPI0 peripheral singleton"] SPI0 <= SPI0()
        (unstable)), (@ peri_type #[doc = "SPI1 peripheral singleton"] SPI1 <= SPI1()
        (unstable)), (@ peri_type #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2
        : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SPI3 peripheral singleton"] SPI3 <= SPI3(SPI3 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <= SYSTEM() (unstable)),
        (@ peri_type #[doc = "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER()
        (unstable)), (@ peri_type #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0()
        (unstable)), (@ peri_type #[doc = "TIMG1 peripheral singleton"] TIMG1 <= TIMG1()
        (unstable)), (@ peri_type #[doc = "TWAI0 peripheral singleton"] TWAI0 <= TWAI0()
        (unstable)), (@ peri_type #[doc = "UART0 peripheral singleton"] UART0 <=
        UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UHCI0 peripheral singleton"]
        UHCI0 <= UHCI0() (unstable)), (@ peri_type #[doc = "USB_FS peripheral singleton"]
        USB_FS <= USB_FS(USB : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "USB_WRAP peripheral singleton"] USB_WRAP <=
        USB_WRAP() (unstable)), (@ peri_type #[doc = "WCL peripheral singleton"] WCL <=
        WCL() (unstable)), (@ peri_type #[doc = "XTS_AES peripheral singleton"] XTS_AES
        <= XTS_AES() (unstable)), (@ peri_type #[doc = "ADC1 peripheral singleton"] ADC1
        <= virtual() (unstable)), (@ peri_type #[doc = "ADC2 peripheral singleton"] ADC2
        <= virtual() (unstable)), (@ peri_type #[doc = "BT peripheral singleton"] BT <=
        virtual(BT_BB : { bind_bb_interrupt, enable_bb_interrupt, disable_bb_interrupt },
        RWBLE : { bind_rwble_interrupt, enable_rwble_interrupt, disable_rwble_interrupt
        }) (unstable)), (@ peri_type #[doc = "CPU_CTRL peripheral singleton"] CPU_CTRL <=
        virtual() (unstable)), (@ peri_type #[doc = "FLASH peripheral singleton"] FLASH
        <= virtual() (unstable)), (@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)),
        (@ peri_type #[doc = "PSRAM peripheral singleton"] PSRAM <= virtual()
        (unstable)), (@ peri_type #[doc = "ULP_RISCV_CORE peripheral singleton"]
        ULP_RISCV_CORE <= virtual() (unstable)), (@ peri_type #[doc =
        "WIFI peripheral singleton"] WIFI <= virtual(WIFI_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt,
        enable_pwr_interrupt, disable_pwr_interrupt })), (@ peri_type #[doc =
        "IPC peripheral singleton"] IPC <= virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <=
        virtual() (unstable)))); _for_each_inner_peripheral!((singletons(GPIO0), (GPIO1),
        (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6), (GPIO7), (GPIO8), (GPIO9), (GPIO10),
        (GPIO11), (GPIO12), (GPIO13), (GPIO14), (#[cfg(not(use_xtal32k))] GPIO15),
        (#[cfg(not(use_xtal32k))] GPIO16), (GPIO17), (GPIO18), (GPIO19), (GPIO20),
        (GPIO21), (GPIO26), (GPIO27), (GPIO28), (GPIO29), (GPIO30), (GPIO31), (GPIO32),
        (GPIO33), (GPIO34), (GPIO35), (GPIO36), (GPIO37), (GPIO38), (GPIO39), (GPIO40),
        (GPIO41), (GPIO42), (GPIO43), (GPIO44), (GPIO45), (GPIO46), (GPIO47), (GPIO48),
        (DMA_CH0(unstable)), (DMA_CH1(unstable)), (DMA_CH2(unstable)),
        (DMA_CH3(unstable)), (DMA_CH4(unstable)), (PCNT0_UNIT0(unstable)),
        (PCNT0_UNIT1(unstable)), (PCNT0_UNIT2(unstable)), (PCNT0_UNIT3(unstable)),
        (SDM_CH0(unstable)), (SDM_CH1(unstable)), (SDM_CH2(unstable)),
        (SDM_CH3(unstable)), (SDM_CH4(unstable)), (SDM_CH5(unstable)),
        (SDM_CH6(unstable)), (SDM_CH7(unstable)), (AES(unstable)), (APB_CTRL(unstable)),
        (APB_SARADC(unstable)), (ASSIST_DEBUG(unstable)), (DMA(unstable)),
        (DS(unstable)), (EXTMEM(unstable)), (GPIO(unstable)), (GPIO_SD(unstable)),
        (HMAC(unstable)), (I2C_ANA_MST(unstable)), (I2C0), (I2C1), (I2S0(unstable)),
        (I2S1(unstable)), (INTERRUPT_CORE0(unstable)), (INTERRUPT_CORE1(unstable)),
        (IO_MUX(unstable)), (LCD_CAM(unstable)), (LEDC(unstable)), (LPWR(unstable)),
        (RTC_TIMER(unstable)), (MCPWM0(unstable)), (MCPWM1(unstable)), (PCNT(unstable)),
        (PERI_BACKUP(unstable)), (RMT(unstable)), (RNG(unstable)), (RSA(unstable)),
        (RTC_CNTL(unstable)), (LP_I2C0(unstable)), (RTC_IO(unstable)),
        (SDHOST(unstable)), (SENS(unstable)), (SENSITIVE(unstable)), (SHA(unstable)),
        (SPI0(unstable)), (SPI1(unstable)), (SPI2), (SPI3), (SYSTEM(unstable)),
        (SYSTIMER(unstable)), (TIMG0(unstable)), (TIMG1(unstable)), (TWAI0(unstable)),
        (UART0), (UART1), (UART2), (UHCI0(unstable)), (USB_FS(unstable)),
        (USB_DEVICE(unstable)), (WCL(unstable)), (XTS_AES(unstable)), (ADC1(unstable)),
        (ADC2(unstable)), (BT(unstable)), (CPU_CTRL(unstable)), (FLASH(unstable)),
        (GPIO_DEDICATED(unstable)), (PSRAM(unstable)), (ULP_RISCV_CORE(unstable)),
        (WIFI), (IPC(unstable)), (FROM_CPU_INTR2(unstable)),
        (FROM_CPU_INTR3(unstable)))); _for_each_inner_peripheral!((dma_eligible(SPI2,
        Spi2, 0, AhbGdmaChannel), (SPI3, Spi3, 1, AhbGdmaChannel), (UHCI0, Uhci0, 2,
        AhbGdmaChannel), (I2S0, I2s0, 3, AhbGdmaChannel), (I2S1, I2s1, 4,
        AhbGdmaChannel), (LCD_CAM, LcdCam, 5, AhbGdmaChannel), (AES, Aes, 6,
        AhbGdmaChannel), (SHA, Sha, 7, AhbGdmaChannel), (APB_SARADC, ApbSaradc, 8,
        AhbGdmaChannel), (RMT, Rmt, 9, AhbGdmaChannel)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output])));
        _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2() () ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3() () ([Input] [Output])));
        _for_each_inner_gpio!((4, GPIO4() () ([Input] [Output])));
        _for_each_inner_gpio!((5, GPIO5() () ([Input] [Output])));
        _for_each_inner_gpio!((6, GPIO6() () ([Input] [Output])));
        _for_each_inner_gpio!((7, GPIO7() () ([Input] [Output])));
        _for_each_inner_gpio!((8, GPIO8() (_3 => SUBSPICS1) ([Input] [Output])));
        _for_each_inner_gpio!((9, GPIO9(_3 => SUBSPIHD _4 => FSPIHD) (_3 => SUBSPIHD _4
        => FSPIHD) ([Input] [Output]))); _for_each_inner_gpio!((10, GPIO10(_2 => FSPIIO4
        _4 => FSPICS0) (_2 => FSPIIO4 _3 => SUBSPICS0 _4 => FSPICS0) ([Input]
        [Output]))); _for_each_inner_gpio!((11, GPIO11(_2 => FSPIIO5 _3 => SUBSPID _4 =>
        FSPID) (_2 => FSPIIO5 _3 => SUBSPID _4 => FSPID) ([Input] [Output])));
        _for_each_inner_gpio!((12, GPIO12(_2 => FSPIIO6 _4 => FSPICLK) (_2 => FSPIIO6 _3
        => SUBSPICLK _4 => FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((13,
        GPIO13(_2 => FSPIIO7 _3 => SUBSPIQ _4 => FSPIQ) (_2 => FSPIIO7 _3 => SUBSPIQ _4
        => FSPIQ) ([Input] [Output]))); _for_each_inner_gpio!((14, GPIO14(_3 => SUBSPIWP
        _4 => FSPIWP) (_2 => FSPIDQS _3 => SUBSPIWP _4 => FSPIWP) ([Input] [Output])));
        _for_each_inner_gpio!((15, GPIO15() (_2 => U0RTS) ([Input] [Output])));
        _for_each_inner_gpio!((16, GPIO16(_2 => U0CTS) () ([Input] [Output])));
        _for_each_inner_gpio!((17, GPIO17() (_2 => U1TXD) ([Input] [Output])));
        _for_each_inner_gpio!((18, GPIO18(_2 => U1RXD) (_3 => CLK_OUT3) ([Input]
        [Output]))); _for_each_inner_gpio!((19, GPIO19() (_2 => U1RTS _3 => CLK_OUT2)
        ([Input] [Output]))); _for_each_inner_gpio!((20, GPIO20(_2 => U1CTS) (_3 =>
        CLK_OUT1) ([Input] [Output]))); _for_each_inner_gpio!((21, GPIO21() () ([Input]
        [Output]))); _for_each_inner_gpio!((26, GPIO26() (_0 => SPICS1) ([Input]
        [Output]))); _for_each_inner_gpio!((27, GPIO27(_0 => SPIHD) (_0 => SPIHD)
        ([Input] [Output]))); _for_each_inner_gpio!((28, GPIO28(_0 => SPIWP) (_0 =>
        SPIWP) ([Input] [Output]))); _for_each_inner_gpio!((29, GPIO29() (_0 => SPICS0)
        ([Input] [Output]))); _for_each_inner_gpio!((30, GPIO30() (_0 => SPICLK) ([Input]
        [Output]))); _for_each_inner_gpio!((31, GPIO31(_0 => SPIQ) (_0 => SPIQ) ([Input]
        [Output]))); _for_each_inner_gpio!((32, GPIO32(_0 => SPID) (_0 => SPID) ([Input]
        [Output]))); _for_each_inner_gpio!((33, GPIO33(_2 => FSPIHD _3 => SUBSPIHD _4 =>
        SPIIO4) (_2 => FSPIHD _3 => SUBSPIHD _4 => SPIIO4) ([Input] [Output])));
        _for_each_inner_gpio!((34, GPIO34(_2 => FSPICS0 _4 => SPIIO5) (_2 => FSPICS0 _3
        => SUBSPICS0 _4 => SPIIO5) ([Input] [Output]))); _for_each_inner_gpio!((35,
        GPIO35(_2 => FSPID _3 => SUBSPID _4 => SPIIO6) (_2 => FSPID _3 => SUBSPID _4 =>
        SPIIO6) ([Input] [Output]))); _for_each_inner_gpio!((36, GPIO36(_2 => FSPICLK _4
        => SPIIO7) (_2 => FSPICLK _3 => SUBSPICLK _4 => SPIIO7) ([Input] [Output])));
        _for_each_inner_gpio!((37, GPIO37(_2 => FSPIQ _3 => SUBSPIQ _4 => SPIDQS) (_2 =>
        FSPIQ _3 => SUBSPIQ _4 => SPIDQS) ([Input] [Output])));
        _for_each_inner_gpio!((38, GPIO38(_2 => FSPIWP _3 => SUBSPIWP) (_2 => FSPIWP _3
        => SUBSPIWP) ([Input] [Output]))); _for_each_inner_gpio!((39, GPIO39(_0 => MTCK)
        (_2 => CLK_OUT3 _3 => SUBSPICS1) ([Input] [Output]))); _for_each_inner_gpio!((40,
        GPIO40() (_0 => MTDO _2 => CLK_OUT2) ([Input] [Output])));
        _for_each_inner_gpio!((41, GPIO41(_0 => MTDI) (_2 => CLK_OUT1) ([Input]
        [Output]))); _for_each_inner_gpio!((42, GPIO42(_0 => MTMS) () ([Input]
        [Output]))); _for_each_inner_gpio!((43, GPIO43() (_0 => U0TXD _2 => CLK_OUT1)
        ([Input] [Output]))); _for_each_inner_gpio!((44, GPIO44(_0 => U0RXD) (_2 =>
        CLK_OUT2) ([Input] [Output]))); _for_each_inner_gpio!((45, GPIO45() () ([Input]
        [Output]))); _for_each_inner_gpio!((46, GPIO46() () ([Input] [Output])));
        _for_each_inner_gpio!((47, GPIO47() (_0 => SPICLK_P_DIFF _2 => SUBSPICLK_P_DIFF)
        ([Input] [Output]))); _for_each_inner_gpio!((48, GPIO48() (_0 => SPICLK_N_DIFF _2
        => SUBSPICLK_N_DIFF) ([Input] [Output]))); _for_each_inner_gpio!((all(0, GPIO0()
        () ([Input] [Output])), (1, GPIO1() () ([Input] [Output])), (2, GPIO2() ()
        ([Input] [Output])), (3, GPIO3() () ([Input] [Output])), (4, GPIO4() () ([Input]
        [Output])), (5, GPIO5() () ([Input] [Output])), (6, GPIO6() () ([Input]
        [Output])), (7, GPIO7() () ([Input] [Output])), (8, GPIO8() (_3 => SUBSPICS1)
        ([Input] [Output])), (9, GPIO9(_3 => SUBSPIHD _4 => FSPIHD) (_3 => SUBSPIHD _4 =>
        FSPIHD) ([Input] [Output])), (10, GPIO10(_2 => FSPIIO4 _4 => FSPICS0) (_2 =>
        FSPIIO4 _3 => SUBSPICS0 _4 => FSPICS0) ([Input] [Output])), (11, GPIO11(_2 =>
        FSPIIO5 _3 => SUBSPID _4 => FSPID) (_2 => FSPIIO5 _3 => SUBSPID _4 => FSPID)
        ([Input] [Output])), (12, GPIO12(_2 => FSPIIO6 _4 => FSPICLK) (_2 => FSPIIO6 _3
        => SUBSPICLK _4 => FSPICLK) ([Input] [Output])), (13, GPIO13(_2 => FSPIIO7 _3 =>
        SUBSPIQ _4 => FSPIQ) (_2 => FSPIIO7 _3 => SUBSPIQ _4 => FSPIQ) ([Input]
        [Output])), (14, GPIO14(_3 => SUBSPIWP _4 => FSPIWP) (_2 => FSPIDQS _3 =>
        SUBSPIWP _4 => FSPIWP) ([Input] [Output])), (15, GPIO15() (_2 => U0RTS) ([Input]
        [Output])), (16, GPIO16(_2 => U0CTS) () ([Input] [Output])), (17, GPIO17() (_2 =>
        U1TXD) ([Input] [Output])), (18, GPIO18(_2 => U1RXD) (_3 => CLK_OUT3) ([Input]
        [Output])), (19, GPIO19() (_2 => U1RTS _3 => CLK_OUT2) ([Input] [Output])), (20,
        GPIO20(_2 => U1CTS) (_3 => CLK_OUT1) ([Input] [Output])), (21, GPIO21() ()
        ([Input] [Output])), (26, GPIO26() (_0 => SPICS1) ([Input] [Output])), (27,
        GPIO27(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output])), (28, GPIO28(_0 => SPIWP)
        (_0 => SPIWP) ([Input] [Output])), (29, GPIO29() (_0 => SPICS0) ([Input]
        [Output])), (30, GPIO30() (_0 => SPICLK) ([Input] [Output])), (31, GPIO31(_0 =>
        SPIQ) (_0 => SPIQ) ([Input] [Output])), (32, GPIO32(_0 => SPID) (_0 => SPID)
        ([Input] [Output])), (33, GPIO33(_2 => FSPIHD _3 => SUBSPIHD _4 => SPIIO4) (_2 =>
        FSPIHD _3 => SUBSPIHD _4 => SPIIO4) ([Input] [Output])), (34, GPIO34(_2 =>
        FSPICS0 _4 => SPIIO5) (_2 => FSPICS0 _3 => SUBSPICS0 _4 => SPIIO5) ([Input]
        [Output])), (35, GPIO35(_2 => FSPID _3 => SUBSPID _4 => SPIIO6) (_2 => FSPID _3
        => SUBSPID _4 => SPIIO6) ([Input] [Output])), (36, GPIO36(_2 => FSPICLK _4 =>
        SPIIO7) (_2 => FSPICLK _3 => SUBSPICLK _4 => SPIIO7) ([Input] [Output])), (37,
        GPIO37(_2 => FSPIQ _3 => SUBSPIQ _4 => SPIDQS) (_2 => FSPIQ _3 => SUBSPIQ _4 =>
        SPIDQS) ([Input] [Output])), (38, GPIO38(_2 => FSPIWP _3 => SUBSPIWP) (_2 =>
        FSPIWP _3 => SUBSPIWP) ([Input] [Output])), (39, GPIO39(_0 => MTCK) (_2 =>
        CLK_OUT3 _3 => SUBSPICS1) ([Input] [Output])), (40, GPIO40() (_0 => MTDO _2 =>
        CLK_OUT2) ([Input] [Output])), (41, GPIO41(_0 => MTDI) (_2 => CLK_OUT1) ([Input]
        [Output])), (42, GPIO42(_0 => MTMS) () ([Input] [Output])), (43, GPIO43() (_0 =>
        U0TXD _2 => CLK_OUT1) ([Input] [Output])), (44, GPIO44(_0 => U0RXD) (_2 =>
        CLK_OUT2) ([Input] [Output])), (45, GPIO45() () ([Input] [Output])), (46,
        GPIO46() () ([Input] [Output])), (47, GPIO47() (_0 => SPICLK_P_DIFF _2 =>
        SUBSPICLK_P_DIFF) ([Input] [Output])), (48, GPIO48() (_0 => SPICLK_N_DIFF _2 =>
        SUBSPICLK_N_DIFF) ([Input] [Output]))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` - expanded signal
///   case, where you need the number(s) of a signal, or the general group to which the signal
///   belongs. For example, in case of `ADC2_CH3` the expanded form looks like `(ADC2_CH3, ADCn_CHm,
///   2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((TOUCH1, GPIO1));
        _for_each_inner_analog_function!((ADC1_CH0, GPIO1));
        _for_each_inner_analog_function!((TOUCH2, GPIO2));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO2));
        _for_each_inner_analog_function!((TOUCH3, GPIO3));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO3));
        _for_each_inner_analog_function!((TOUCH4, GPIO4));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO4));
        _for_each_inner_analog_function!((TOUCH5, GPIO5));
        _for_each_inner_analog_function!((ADC1_CH4, GPIO5));
        _for_each_inner_analog_function!((TOUCH6, GPIO6));
        _for_each_inner_analog_function!((ADC1_CH5, GPIO6));
        _for_each_inner_analog_function!((TOUCH7, GPIO7));
        _for_each_inner_analog_function!((ADC1_CH6, GPIO7));
        _for_each_inner_analog_function!((TOUCH8, GPIO8));
        _for_each_inner_analog_function!((ADC1_CH7, GPIO8));
        _for_each_inner_analog_function!((TOUCH9, GPIO9));
        _for_each_inner_analog_function!((ADC1_CH8, GPIO9));
        _for_each_inner_analog_function!((TOUCH10, GPIO10));
        _for_each_inner_analog_function!((ADC1_CH9, GPIO10));
        _for_each_inner_analog_function!((TOUCH11, GPIO11));
        _for_each_inner_analog_function!((ADC2_CH0, GPIO11));
        _for_each_inner_analog_function!((TOUCH12, GPIO12));
        _for_each_inner_analog_function!((ADC2_CH1, GPIO12));
        _for_each_inner_analog_function!((TOUCH13, GPIO13));
        _for_each_inner_analog_function!((ADC2_CH2, GPIO13));
        _for_each_inner_analog_function!((TOUCH14, GPIO14));
        _for_each_inner_analog_function!((ADC2_CH3, GPIO14));
        _for_each_inner_analog_function!((XTAL_32K_P, GPIO15));
        _for_each_inner_analog_function!((ADC2_CH4, GPIO15));
        _for_each_inner_analog_function!((XTAL_32K_N, GPIO16));
        _for_each_inner_analog_function!((ADC2_CH5, GPIO16));
        _for_each_inner_analog_function!((ADC2_CH6, GPIO17));
        _for_each_inner_analog_function!((ADC2_CH7, GPIO18));
        _for_each_inner_analog_function!((USB_FS_DM, GPIO19));
        _for_each_inner_analog_function!((ADC2_CH8, GPIO19));
        _for_each_inner_analog_function!((USB_FS_DP, GPIO20));
        _for_each_inner_analog_function!((ADC2_CH9, GPIO20));
        _for_each_inner_analog_function!(((TOUCH1, TOUCHn, 1), GPIO1));
        _for_each_inner_analog_function!(((TOUCH2, TOUCHn, 2), GPIO2));
        _for_each_inner_analog_function!(((TOUCH3, TOUCHn, 3), GPIO3));
        _for_each_inner_analog_function!(((TOUCH4, TOUCHn, 4), GPIO4));
        _for_each_inner_analog_function!(((TOUCH5, TOUCHn, 5), GPIO5));
        _for_each_inner_analog_function!(((TOUCH6, TOUCHn, 6), GPIO6));
        _for_each_inner_analog_function!(((TOUCH7, TOUCHn, 7), GPIO7));
        _for_each_inner_analog_function!(((TOUCH8, TOUCHn, 8), GPIO8));
        _for_each_inner_analog_function!(((TOUCH9, TOUCHn, 9), GPIO9));
        _for_each_inner_analog_function!(((TOUCH10, TOUCHn, 10), GPIO10));
        _for_each_inner_analog_function!(((TOUCH11, TOUCHn, 11), GPIO11));
        _for_each_inner_analog_function!(((TOUCH12, TOUCHn, 12), GPIO12));
        _for_each_inner_analog_function!(((TOUCH13, TOUCHn, 13), GPIO13));
        _for_each_inner_analog_function!(((TOUCH14, TOUCHn, 14), GPIO14));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO1));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO2));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO3));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO4));
        _for_each_inner_analog_function!(((ADC1_CH4, ADCn_CHm, 1, 4), GPIO5));
        _for_each_inner_analog_function!(((ADC1_CH5, ADCn_CHm, 1, 5), GPIO6));
        _for_each_inner_analog_function!(((ADC1_CH6, ADCn_CHm, 1, 6), GPIO7));
        _for_each_inner_analog_function!(((ADC1_CH7, ADCn_CHm, 1, 7), GPIO8));
        _for_each_inner_analog_function!(((ADC1_CH8, ADCn_CHm, 1, 8), GPIO9));
        _for_each_inner_analog_function!(((ADC1_CH9, ADCn_CHm, 1, 9), GPIO10));
        _for_each_inner_analog_function!(((ADC2_CH0, ADCn_CHm, 2, 0), GPIO11));
        _for_each_inner_analog_function!(((ADC2_CH1, ADCn_CHm, 2, 1), GPIO12));
        _for_each_inner_analog_function!(((ADC2_CH2, ADCn_CHm, 2, 2), GPIO13));
        _for_each_inner_analog_function!(((ADC2_CH3, ADCn_CHm, 2, 3), GPIO14));
        _for_each_inner_analog_function!(((ADC2_CH4, ADCn_CHm, 2, 4), GPIO15));
        _for_each_inner_analog_function!(((ADC2_CH5, ADCn_CHm, 2, 5), GPIO16));
        _for_each_inner_analog_function!(((ADC2_CH6, ADCn_CHm, 2, 6), GPIO17));
        _for_each_inner_analog_function!(((ADC2_CH7, ADCn_CHm, 2, 7), GPIO18));
        _for_each_inner_analog_function!(((ADC2_CH8, ADCn_CHm, 2, 8), GPIO19));
        _for_each_inner_analog_function!(((ADC2_CH9, ADCn_CHm, 2, 9), GPIO20));
        _for_each_inner_analog_function!((all(TOUCH1, GPIO1), (ADC1_CH0, GPIO1), (TOUCH2,
        GPIO2), (ADC1_CH1, GPIO2), (TOUCH3, GPIO3), (ADC1_CH2, GPIO3), (TOUCH4, GPIO4),
        (ADC1_CH3, GPIO4), (TOUCH5, GPIO5), (ADC1_CH4, GPIO5), (TOUCH6, GPIO6),
        (ADC1_CH5, GPIO6), (TOUCH7, GPIO7), (ADC1_CH6, GPIO7), (TOUCH8, GPIO8),
        (ADC1_CH7, GPIO8), (TOUCH9, GPIO9), (ADC1_CH8, GPIO9), (TOUCH10, GPIO10),
        (ADC1_CH9, GPIO10), (TOUCH11, GPIO11), (ADC2_CH0, GPIO11), (TOUCH12, GPIO12),
        (ADC2_CH1, GPIO12), (TOUCH13, GPIO13), (ADC2_CH2, GPIO13), (TOUCH14, GPIO14),
        (ADC2_CH3, GPIO14), (XTAL_32K_P, GPIO15), (ADC2_CH4, GPIO15), (XTAL_32K_N,
        GPIO16), (ADC2_CH5, GPIO16), (ADC2_CH6, GPIO17), (ADC2_CH7, GPIO18), (USB_FS_DM,
        GPIO19), (ADC2_CH8, GPIO19), (USB_FS_DP, GPIO20), (ADC2_CH9, GPIO20)));
        _for_each_inner_analog_function!((TOUCHn((TOUCH1, TOUCHn, 1), GPIO1), ((TOUCH2,
        TOUCHn, 2), GPIO2), ((TOUCH3, TOUCHn, 3), GPIO3), ((TOUCH4, TOUCHn, 4), GPIO4),
        ((TOUCH5, TOUCHn, 5), GPIO5), ((TOUCH6, TOUCHn, 6), GPIO6), ((TOUCH7, TOUCHn, 7),
        GPIO7), ((TOUCH8, TOUCHn, 8), GPIO8), ((TOUCH9, TOUCHn, 9), GPIO9), ((TOUCH10,
        TOUCHn, 10), GPIO10), ((TOUCH11, TOUCHn, 11), GPIO11), ((TOUCH12, TOUCHn, 12),
        GPIO12), ((TOUCH13, TOUCHn, 13), GPIO13), ((TOUCH14, TOUCHn, 14), GPIO14)));
        _for_each_inner_analog_function!((ADCn_CHm((ADC1_CH0, ADCn_CHm, 1, 0), GPIO1),
        ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO2), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO3),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO4), ((ADC1_CH4, ADCn_CHm, 1, 4), GPIO5),
        ((ADC1_CH5, ADCn_CHm, 1, 5), GPIO6), ((ADC1_CH6, ADCn_CHm, 1, 6), GPIO7),
        ((ADC1_CH7, ADCn_CHm, 1, 7), GPIO8), ((ADC1_CH8, ADCn_CHm, 1, 8), GPIO9),
        ((ADC1_CH9, ADCn_CHm, 1, 9), GPIO10), ((ADC2_CH0, ADCn_CHm, 2, 0), GPIO11),
        ((ADC2_CH1, ADCn_CHm, 2, 1), GPIO12), ((ADC2_CH2, ADCn_CHm, 2, 2), GPIO13),
        ((ADC2_CH3, ADCn_CHm, 2, 3), GPIO14), ((ADC2_CH4, ADCn_CHm, 2, 4), GPIO15),
        ((ADC2_CH5, ADCn_CHm, 2, 5), GPIO16), ((ADC2_CH6, ADCn_CHm, 2, 6), GPIO17),
        ((ADC2_CH7, ADCn_CHm, 2, 7), GPIO18), ((ADC2_CH8, ADCn_CHm, 2, 8), GPIO19),
        ((ADC2_CH9, ADCn_CHm, 2, 9), GPIO20)));
    };
}
/// This macro can be used to generate code for each LP function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident, ($(
///   $lp_input_af:ident => $lp_input_signal:ident )*) ($( $lp_output_af:ident =>
///   $lp_output_signal:ident )*))` - expanded signal case, where you need the number(s) of a
///   signal, or the general group to which the signal belongs. Every expanded branch ends with the
///   pad's LP input and output function groups (empty on chips without an LP GPIO matrix).
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the LP IO MUX function, as an identifier (i.e. for function 0 this is `_0`). This is
///   the name of an `LpFunction` variant, and its number is the value to write to the pad's
///   function select field.
/// - `$lp_input_af`: the LP IO MUX function for an LP peripheral input on this pad.
/// - `$lp_input_signal`: the LP peripheral input signal name.
/// - `$lp_output_af`: the LP IO MUX function for an LP peripheral output on this pad.
/// - `$lp_output_signal`: the LP peripheral output signal name.
///
/// Example data:
/// - `(LP_GPIO15, GPIO12, _0)`
/// - `((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ())`
/// - `((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD))`
/// - `((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((LP_GPIO0, GPIO0, _0));
        _for_each_inner_lp_function!((SAR_I2C_SCL_0, GPIO0, _3));
        _for_each_inner_lp_function!((LP_GPIO1, GPIO1, _0));
        _for_each_inner_lp_function!((SAR_I2C_SDA_0, GPIO1, _3));
        _for_each_inner_lp_function!((LP_GPIO2, GPIO2, _0));
        _for_each_inner_lp_function!((SAR_I2C_SCL_1, GPIO2, _3));
        _for_each_inner_lp_function!((LP_GPIO3, GPIO3, _0));
        _for_each_inner_lp_function!((SAR_I2C_SDA_1, GPIO3, _3));
        _for_each_inner_lp_function!((LP_GPIO4, GPIO4, _0));
        _for_each_inner_lp_function!((LP_GPIO5, GPIO5, _0));
        _for_each_inner_lp_function!((LP_GPIO6, GPIO6, _0));
        _for_each_inner_lp_function!((LP_GPIO7, GPIO7, _0));
        _for_each_inner_lp_function!((LP_GPIO8, GPIO8, _0));
        _for_each_inner_lp_function!((LP_GPIO9, GPIO9, _0));
        _for_each_inner_lp_function!((LP_GPIO10, GPIO10, _0));
        _for_each_inner_lp_function!((LP_GPIO11, GPIO11, _0));
        _for_each_inner_lp_function!((LP_GPIO12, GPIO12, _0));
        _for_each_inner_lp_function!((LP_GPIO13, GPIO13, _0));
        _for_each_inner_lp_function!((LP_GPIO14, GPIO14, _0));
        _for_each_inner_lp_function!((LP_GPIO15, GPIO15, _0));
        _for_each_inner_lp_function!((LP_GPIO16, GPIO16, _0));
        _for_each_inner_lp_function!((LP_GPIO17, GPIO17, _0));
        _for_each_inner_lp_function!((LP_GPIO18, GPIO18, _0));
        _for_each_inner_lp_function!((LP_GPIO19, GPIO19, _0));
        _for_each_inner_lp_function!((LP_GPIO20, GPIO20, _0));
        _for_each_inner_lp_function!((LP_GPIO21, GPIO21, _0));
        _for_each_inner_lp_function!(((LP_GPIO0, LP_GPIOn, 0), GPIO0, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO1, LP_GPIOn, 1), GPIO1, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO2, LP_GPIOn, 2), GPIO2, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO3, LP_GPIOn, 3), GPIO3, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO4, LP_GPIOn, 4), GPIO4, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO5, LP_GPIOn, 5), GPIO5, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO6, LP_GPIOn, 6), GPIO6, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO7, LP_GPIOn, 7), GPIO7, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO8, LP_GPIOn, 8), GPIO8, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO9, LP_GPIOn, 9), GPIO9, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO10, LP_GPIOn, 10), GPIO10, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO11, LP_GPIOn, 11), GPIO11, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO12, LP_GPIOn, 12), GPIO12, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO13, LP_GPIOn, 13), GPIO13, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO14, LP_GPIOn, 14), GPIO14, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO15, LP_GPIOn, 15), GPIO15, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO16, LP_GPIOn, 16), GPIO16, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO17, LP_GPIOn, 17), GPIO17, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO18, LP_GPIOn, 18), GPIO18, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO19, LP_GPIOn, 19), GPIO19, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO20, LP_GPIOn, 20), GPIO20, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO21, LP_GPIOn, 21), GPIO21, _0, () ()));
        _for_each_inner_lp_function!(((SAR_I2C_SCL_0, SAR_I2C_SCL_n, 0), GPIO0, _3, ()
        ())); _for_each_inner_lp_function!(((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3,
        () ())); _for_each_inner_lp_function!(((SAR_I2C_SDA_0, SAR_I2C_SDA_n, 0), GPIO1,
        _3, () ())); _for_each_inner_lp_function!(((SAR_I2C_SDA_1, SAR_I2C_SDA_n, 1),
        GPIO3, _3, () ())); _for_each_inner_lp_function!((all(LP_GPIO0, GPIO0, _0),
        (SAR_I2C_SCL_0, GPIO0, _3), (LP_GPIO1, GPIO1, _0), (SAR_I2C_SDA_0, GPIO1, _3),
        (LP_GPIO2, GPIO2, _0), (SAR_I2C_SCL_1, GPIO2, _3), (LP_GPIO3, GPIO3, _0),
        (SAR_I2C_SDA_1, GPIO3, _3), (LP_GPIO4, GPIO4, _0), (LP_GPIO5, GPIO5, _0),
        (LP_GPIO6, GPIO6, _0), (LP_GPIO7, GPIO7, _0), (LP_GPIO8, GPIO8, _0), (LP_GPIO9,
        GPIO9, _0), (LP_GPIO10, GPIO10, _0), (LP_GPIO11, GPIO11, _0), (LP_GPIO12, GPIO12,
        _0), (LP_GPIO13, GPIO13, _0), (LP_GPIO14, GPIO14, _0), (LP_GPIO15, GPIO15, _0),
        (LP_GPIO16, GPIO16, _0), (LP_GPIO17, GPIO17, _0), (LP_GPIO18, GPIO18, _0),
        (LP_GPIO19, GPIO19, _0), (LP_GPIO20, GPIO20, _0), (LP_GPIO21, GPIO21, _0)));
        _for_each_inner_lp_function!((LP_GPIOn((LP_GPIO0, LP_GPIOn, 0), GPIO0, _0, ()
        ()), ((LP_GPIO1, LP_GPIOn, 1), GPIO1, _0, () ()), ((LP_GPIO2, LP_GPIOn, 2),
        GPIO2, _0, () ()), ((LP_GPIO3, LP_GPIOn, 3), GPIO3, _0, () ()), ((LP_GPIO4,
        LP_GPIOn, 4), GPIO4, _0, () ()), ((LP_GPIO5, LP_GPIOn, 5), GPIO5, _0, () ()),
        ((LP_GPIO6, LP_GPIOn, 6), GPIO6, _0, () ()), ((LP_GPIO7, LP_GPIOn, 7), GPIO7, _0,
        () ()), ((LP_GPIO8, LP_GPIOn, 8), GPIO8, _0, () ()), ((LP_GPIO9, LP_GPIOn, 9),
        GPIO9, _0, () ()), ((LP_GPIO10, LP_GPIOn, 10), GPIO10, _0, () ()), ((LP_GPIO11,
        LP_GPIOn, 11), GPIO11, _0, () ()), ((LP_GPIO12, LP_GPIOn, 12), GPIO12, _0, ()
        ()), ((LP_GPIO13, LP_GPIOn, 13), GPIO13, _0, () ()), ((LP_GPIO14, LP_GPIOn, 14),
        GPIO14, _0, () ()), ((LP_GPIO15, LP_GPIOn, 15), GPIO15, _0, () ()), ((LP_GPIO16,
        LP_GPIOn, 16), GPIO16, _0, () ()), ((LP_GPIO17, LP_GPIOn, 17), GPIO17, _0, ()
        ()), ((LP_GPIO18, LP_GPIOn, 18), GPIO18, _0, () ()), ((LP_GPIO19, LP_GPIOn, 19),
        GPIO19, _0, () ()), ((LP_GPIO20, LP_GPIOn, 20), GPIO20, _0, () ()), ((LP_GPIO21,
        LP_GPIOn, 21), GPIO21, _0, () ())));
        _for_each_inner_lp_function!((SAR_I2C_SCL_n((SAR_I2C_SCL_0, SAR_I2C_SCL_n, 0),
        GPIO0, _3, () ()), ((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())));
        _for_each_inner_lp_function!((SAR_I2C_SDA_n((SAR_I2C_SDA_0, SAR_I2C_SDA_n, 0),
        GPIO1, _3, () ()), ((SAR_I2C_SDA_1, SAR_I2C_SDA_n, 1), GPIO3, _3, () ())));
    };
}
/// This macro can be used to generate code for each IOMUX digital function of each GPIO.
///
/// IOMUX functions are the alternate digital functions configured via the IO_MUX registers.
/// Use this to implement signal-specific traits for peripherals whose pins must bypass the
/// GPIO matrix (e.g., EMAC, USB).
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the alternate function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the alternate function number, as an identifier (e.g. `_5`).
///
/// Example data:
/// - `(EMAC_RXD0, GPIO25, _5)`
/// - `((EMAC_RXDn, EMAC_RXDn, 0), GPIO25, _5)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_iomux_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_iomux_function!((SUBSPICS1, GPIO8, _3));
        _for_each_inner_iomux_function!((SUBSPIHD, GPIO9, _3));
        _for_each_inner_iomux_function!((FSPIHD, GPIO9, _4));
        _for_each_inner_iomux_function!((FSPIIO4, GPIO10, _2));
        _for_each_inner_iomux_function!((SUBSPICS0, GPIO10, _3));
        _for_each_inner_iomux_function!((FSPICS0, GPIO10, _4));
        _for_each_inner_iomux_function!((FSPIIO5, GPIO11, _2));
        _for_each_inner_iomux_function!((SUBSPID, GPIO11, _3));
        _for_each_inner_iomux_function!((FSPID, GPIO11, _4));
        _for_each_inner_iomux_function!((FSPIIO6, GPIO12, _2));
        _for_each_inner_iomux_function!((SUBSPICLK, GPIO12, _3));
        _for_each_inner_iomux_function!((FSPICLK, GPIO12, _4));
        _for_each_inner_iomux_function!((FSPIIO7, GPIO13, _2));
        _for_each_inner_iomux_function!((SUBSPIQ, GPIO13, _3));
        _for_each_inner_iomux_function!((FSPIQ, GPIO13, _4));
        _for_each_inner_iomux_function!((FSPIDQS, GPIO14, _2));
        _for_each_inner_iomux_function!((SUBSPIWP, GPIO14, _3));
        _for_each_inner_iomux_function!((FSPIWP, GPIO14, _4));
        _for_each_inner_iomux_function!((U0RTS, GPIO15, _2));
        _for_each_inner_iomux_function!((U0CTS, GPIO16, _2));
        _for_each_inner_iomux_function!((U1TXD, GPIO17, _2));
        _for_each_inner_iomux_function!((U1RXD, GPIO18, _2));
        _for_each_inner_iomux_function!((CLK_OUT3, GPIO18, _3));
        _for_each_inner_iomux_function!((U1RTS, GPIO19, _2));
        _for_each_inner_iomux_function!((CLK_OUT2, GPIO19, _3));
        _for_each_inner_iomux_function!((U1CTS, GPIO20, _2));
        _for_each_inner_iomux_function!((CLK_OUT1, GPIO20, _3));
        _for_each_inner_iomux_function!((SPICS1, GPIO26, _0));
        _for_each_inner_iomux_function!((SPIHD, GPIO27, _0));
        _for_each_inner_iomux_function!((SPIWP, GPIO28, _0));
        _for_each_inner_iomux_function!((SPICS0, GPIO29, _0));
        _for_each_inner_iomux_function!((SPICLK, GPIO30, _0));
        _for_each_inner_iomux_function!((SPIQ, GPIO31, _0));
        _for_each_inner_iomux_function!((SPID, GPIO32, _0));
        _for_each_inner_iomux_function!((FSPIHD, GPIO33, _2));
        _for_each_inner_iomux_function!((SUBSPIHD, GPIO33, _3));
        _for_each_inner_iomux_function!((SPIIO4, GPIO33, _4));
        _for_each_inner_iomux_function!((FSPICS0, GPIO34, _2));
        _for_each_inner_iomux_function!((SUBSPICS0, GPIO34, _3));
        _for_each_inner_iomux_function!((SPIIO5, GPIO34, _4));
        _for_each_inner_iomux_function!((FSPID, GPIO35, _2));
        _for_each_inner_iomux_function!((SUBSPID, GPIO35, _3));
        _for_each_inner_iomux_function!((SPIIO6, GPIO35, _4));
        _for_each_inner_iomux_function!((FSPICLK, GPIO36, _2));
        _for_each_inner_iomux_function!((SUBSPICLK, GPIO36, _3));
        _for_each_inner_iomux_function!((SPIIO7, GPIO36, _4));
        _for_each_inner_iomux_function!((FSPIQ, GPIO37, _2));
        _for_each_inner_iomux_function!((SUBSPIQ, GPIO37, _3));
        _for_each_inner_iomux_function!((SPIDQS, GPIO37, _4));
        _for_each_inner_iomux_function!((FSPIWP, GPIO38, _2));
        _for_each_inner_iomux_function!((SUBSPIWP, GPIO38, _3));
        _for_each_inner_iomux_function!((MTCK, GPIO39, _0));
        _for_each_inner_iomux_function!((CLK_OUT3, GPIO39, _2));
        _for_each_inner_iomux_function!((SUBSPICS1, GPIO39, _3));
        _for_each_inner_iomux_function!((MTDO, GPIO40, _0));
        _for_each_inner_iomux_function!((CLK_OUT2, GPIO40, _2));
        _for_each_inner_iomux_function!((MTDI, GPIO41, _0));
        _for_each_inner_iomux_function!((CLK_OUT1, GPIO41, _2));
        _for_each_inner_iomux_function!((MTMS, GPIO42, _0));
        _for_each_inner_iomux_function!((U0TXD, GPIO43, _0));
        _for_each_inner_iomux_function!((CLK_OUT1, GPIO43, _2));
        _for_each_inner_iomux_function!((U0RXD, GPIO44, _0));
        _for_each_inner_iomux_function!((CLK_OUT2, GPIO44, _2));
        _for_each_inner_iomux_function!((SPICLK_P_DIFF, GPIO47, _0));
        _for_each_inner_iomux_function!((SUBSPICLK_P_DIFF, GPIO47, _2));
        _for_each_inner_iomux_function!((SPICLK_N_DIFF, GPIO48, _0));
        _for_each_inner_iomux_function!((SUBSPICLK_N_DIFF, GPIO48, _2));
        _for_each_inner_iomux_function!(((SUBSPICS1, SUBSPICSn, 1), GPIO8, _3));
        _for_each_inner_iomux_function!(((SUBSPICS0, SUBSPICSn, 0), GPIO10, _3));
        _for_each_inner_iomux_function!(((SUBSPICS0, SUBSPICSn, 0), GPIO34, _3));
        _for_each_inner_iomux_function!(((SUBSPICS1, SUBSPICSn, 1), GPIO39, _3));
        _for_each_inner_iomux_function!(((FSPIIO4, FSPIIOn, 4), GPIO10, _2));
        _for_each_inner_iomux_function!(((FSPIIO5, FSPIIOn, 5), GPIO11, _2));
        _for_each_inner_iomux_function!(((FSPIIO6, FSPIIOn, 6), GPIO12, _2));
        _for_each_inner_iomux_function!(((FSPIIO7, FSPIIOn, 7), GPIO13, _2));
        _for_each_inner_iomux_function!(((FSPICS0, FSPICSn, 0), GPIO10, _4));
        _for_each_inner_iomux_function!(((FSPICS0, FSPICSn, 0), GPIO34, _2));
        _for_each_inner_iomux_function!(((CLK_OUT3, CLK_OUTn, 3), GPIO18, _3));
        _for_each_inner_iomux_function!(((CLK_OUT2, CLK_OUTn, 2), GPIO19, _3));
        _for_each_inner_iomux_function!(((CLK_OUT1, CLK_OUTn, 1), GPIO20, _3));
        _for_each_inner_iomux_function!(((CLK_OUT3, CLK_OUTn, 3), GPIO39, _2));
        _for_each_inner_iomux_function!(((CLK_OUT2, CLK_OUTn, 2), GPIO40, _2));
        _for_each_inner_iomux_function!(((CLK_OUT1, CLK_OUTn, 1), GPIO41, _2));
        _for_each_inner_iomux_function!(((CLK_OUT1, CLK_OUTn, 1), GPIO43, _2));
        _for_each_inner_iomux_function!(((CLK_OUT2, CLK_OUTn, 2), GPIO44, _2));
        _for_each_inner_iomux_function!(((SPICS1, SPICSn, 1), GPIO26, _0));
        _for_each_inner_iomux_function!(((SPICS0, SPICSn, 0), GPIO29, _0));
        _for_each_inner_iomux_function!(((SPIIO4, SPIIOn, 4), GPIO33, _4));
        _for_each_inner_iomux_function!(((SPIIO5, SPIIOn, 5), GPIO34, _4));
        _for_each_inner_iomux_function!(((SPIIO6, SPIIOn, 6), GPIO35, _4));
        _for_each_inner_iomux_function!(((SPIIO7, SPIIOn, 7), GPIO36, _4));
        _for_each_inner_iomux_function!((all(SUBSPICS1, GPIO8, _3), (SUBSPIHD, GPIO9,
        _3), (FSPIHD, GPIO9, _4), (FSPIIO4, GPIO10, _2), (SUBSPICS0, GPIO10, _3),
        (FSPICS0, GPIO10, _4), (FSPIIO5, GPIO11, _2), (SUBSPID, GPIO11, _3), (FSPID,
        GPIO11, _4), (FSPIIO6, GPIO12, _2), (SUBSPICLK, GPIO12, _3), (FSPICLK, GPIO12,
        _4), (FSPIIO7, GPIO13, _2), (SUBSPIQ, GPIO13, _3), (FSPIQ, GPIO13, _4), (FSPIDQS,
        GPIO14, _2), (SUBSPIWP, GPIO14, _3), (FSPIWP, GPIO14, _4), (U0RTS, GPIO15, _2),
        (U0CTS, GPIO16, _2), (U1TXD, GPIO17, _2), (U1RXD, GPIO18, _2), (CLK_OUT3, GPIO18,
        _3), (U1RTS, GPIO19, _2), (CLK_OUT2, GPIO19, _3), (U1CTS, GPIO20, _2), (CLK_OUT1,
        GPIO20, _3), (SPICS1, GPIO26, _0), (SPIHD, GPIO27, _0), (SPIWP, GPIO28, _0),
        (SPICS0, GPIO29, _0), (SPICLK, GPIO30, _0), (SPIQ, GPIO31, _0), (SPID, GPIO32,
        _0), (FSPIHD, GPIO33, _2), (SUBSPIHD, GPIO33, _3), (SPIIO4, GPIO33, _4),
        (FSPICS0, GPIO34, _2), (SUBSPICS0, GPIO34, _3), (SPIIO5, GPIO34, _4), (FSPID,
        GPIO35, _2), (SUBSPID, GPIO35, _3), (SPIIO6, GPIO35, _4), (FSPICLK, GPIO36, _2),
        (SUBSPICLK, GPIO36, _3), (SPIIO7, GPIO36, _4), (FSPIQ, GPIO37, _2), (SUBSPIQ,
        GPIO37, _3), (SPIDQS, GPIO37, _4), (FSPIWP, GPIO38, _2), (SUBSPIWP, GPIO38, _3),
        (MTCK, GPIO39, _0), (CLK_OUT3, GPIO39, _2), (SUBSPICS1, GPIO39, _3), (MTDO,
        GPIO40, _0), (CLK_OUT2, GPIO40, _2), (MTDI, GPIO41, _0), (CLK_OUT1, GPIO41, _2),
        (MTMS, GPIO42, _0), (U0TXD, GPIO43, _0), (CLK_OUT1, GPIO43, _2), (U0RXD, GPIO44,
        _0), (CLK_OUT2, GPIO44, _2), (SPICLK_P_DIFF, GPIO47, _0), (SUBSPICLK_P_DIFF,
        GPIO47, _2), (SPICLK_N_DIFF, GPIO48, _0), (SUBSPICLK_N_DIFF, GPIO48, _2)));
        _for_each_inner_iomux_function!((SUBSPICSn((SUBSPICS1, SUBSPICSn, 1), GPIO8, _3),
        ((SUBSPICS0, SUBSPICSn, 0), GPIO10, _3), ((SUBSPICS0, SUBSPICSn, 0), GPIO34, _3),
        ((SUBSPICS1, SUBSPICSn, 1), GPIO39, _3)));
        _for_each_inner_iomux_function!((FSPIIOn((FSPIIO4, FSPIIOn, 4), GPIO10, _2),
        ((FSPIIO5, FSPIIOn, 5), GPIO11, _2), ((FSPIIO6, FSPIIOn, 6), GPIO12, _2),
        ((FSPIIO7, FSPIIOn, 7), GPIO13, _2)));
        _for_each_inner_iomux_function!((FSPICSn((FSPICS0, FSPICSn, 0), GPIO10, _4),
        ((FSPICS0, FSPICSn, 0), GPIO34, _2)));
        _for_each_inner_iomux_function!((CLK_OUTn((CLK_OUT3, CLK_OUTn, 3), GPIO18, _3),
        ((CLK_OUT2, CLK_OUTn, 2), GPIO19, _3), ((CLK_OUT1, CLK_OUTn, 1), GPIO20, _3),
        ((CLK_OUT3, CLK_OUTn, 3), GPIO39, _2), ((CLK_OUT2, CLK_OUTn, 2), GPIO40, _2),
        ((CLK_OUT1, CLK_OUTn, 1), GPIO41, _2), ((CLK_OUT1, CLK_OUTn, 1), GPIO43, _2),
        ((CLK_OUT2, CLK_OUTn, 2), GPIO44, _2)));
        _for_each_inner_iomux_function!((SPICSn((SPICS1, SPICSn, 1), GPIO26, _0),
        ((SPICS0, SPICSn, 0), GPIO29, _0)));
        _for_each_inner_iomux_function!((SPIIOn((SPIIO4, SPIIOn, 4), GPIO33, _4),
        ((SPIIO5, SPIIOn, 5), GPIO34, _4), ((SPIIO6, SPIIOn, 6), GPIO35, _4), ((SPIIO7,
        SPIIOn, 7), GPIO36, _4)));
    };
}
/// Returns the name of the GPIO that provides the given signal, as a string.
///
/// The macro takes the name of a direct function - a digital IO MUX function, an analog
/// function, or an LP IO MUX function - and expands to a string literal like `"GPIO4"`. It
/// is meant to keep documentation free of per-chip pin lists.
///
/// Signals that are not wired to a pad on this chip have to be routed through the GPIO
/// matrix, which can reach any pad. The macro has no pad to return for those, so it accepts
/// an optional fallback to expand to instead. The fallback is not validated.
///
/// If multiple pads provide the signal, the macro returns one that is not reserved for some
/// other purpose, such as booting or interfacing with flash.
///
/// Example usage:
/// - `gpio_for_signal!(ADC1_CH0)`
/// - `gpio_for_signal!(LP_I2C_SDA, "GPIO6")`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! gpio_for_signal {
    (LP_GPIO0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (SAR_I2C_SCL_0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (TOUCH1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (ADC1_CH0 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (LP_GPIO1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (SAR_I2C_SDA_0 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (TOUCH2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (ADC1_CH1 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (LP_GPIO2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (SAR_I2C_SCL_1 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (TOUCH3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (ADC1_CH2 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (LP_GPIO3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (SAR_I2C_SDA_1 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (TOUCH4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (ADC1_CH3 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (LP_GPIO4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (TOUCH5 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (ADC1_CH4 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (LP_GPIO5 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (TOUCH6 $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (ADC1_CH5 $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (LP_GPIO6 $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (TOUCH7 $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (ADC1_CH6 $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (LP_GPIO7 $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (SUBSPICS1 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (TOUCH8 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (ADC1_CH7 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (LP_GPIO8 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (SUBSPIHD $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (FSPIHD $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (TOUCH9 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (ADC1_CH8 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (LP_GPIO9 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (FSPIIO4 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SUBSPICS0 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (FSPICS0 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (TOUCH10 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (ADC1_CH9 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (LP_GPIO10 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (FSPIIO5 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (SUBSPID $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (FSPID $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (TOUCH11 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (ADC2_CH0 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (LP_GPIO11 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (FSPIIO6 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (SUBSPICLK $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (FSPICLK $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (TOUCH12 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (ADC2_CH1 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (LP_GPIO12 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (FSPIIO7 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (SUBSPIQ $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (FSPIQ $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (TOUCH13 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (ADC2_CH2 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (LP_GPIO13 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (FSPIDQS $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (SUBSPIWP $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (FSPIWP $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (TOUCH14 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (ADC2_CH3 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (LP_GPIO14 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (U0RTS $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (XTAL_32K_P $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (ADC2_CH4 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (LP_GPIO15 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (U0CTS $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (XTAL_32K_N $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (ADC2_CH5 $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (LP_GPIO16 $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (U1TXD $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (ADC2_CH6 $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (LP_GPIO17 $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (U1RXD $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (CLK_OUT3 $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (ADC2_CH7 $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (LP_GPIO18 $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (U1RTS $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (CLK_OUT2 $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (USB_FS_DM $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (ADC2_CH8 $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (LP_GPIO19 $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (U1CTS $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (CLK_OUT1 $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (USB_FS_DP $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (ADC2_CH9 $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (LP_GPIO20 $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    (LP_GPIO21 $(, $_fallback:literal)?) => {
        "GPIO21"
    };
    (SPICS1 $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (SPIHD $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (SPIWP $(, $_fallback:literal)?) => {
        "GPIO28"
    };
    (SPICS0 $(, $_fallback:literal)?) => {
        "GPIO29"
    };
    (SPICLK $(, $_fallback:literal)?) => {
        "GPIO30"
    };
    (SPIQ $(, $_fallback:literal)?) => {
        "GPIO31"
    };
    (SPID $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (SPIIO4 $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (SPIIO5 $(, $_fallback:literal)?) => {
        "GPIO34"
    };
    (SPIIO6 $(, $_fallback:literal)?) => {
        "GPIO35"
    };
    (SPIIO7 $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (SPIDQS $(, $_fallback:literal)?) => {
        "GPIO37"
    };
    (MTCK $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    (MTDO $(, $_fallback:literal)?) => {
        "GPIO40"
    };
    (MTDI $(, $_fallback:literal)?) => {
        "GPIO41"
    };
    (MTMS $(, $_fallback:literal)?) => {
        "GPIO42"
    };
    (U0TXD $(, $_fallback:literal)?) => {
        "GPIO43"
    };
    (U0RXD $(, $_fallback:literal)?) => {
        "GPIO44"
    };
    (SPICLK_P_DIFF $(, $_fallback:literal)?) => {
        "GPIO47"
    };
    (SUBSPICLK_P_DIFF $(, $_fallback:literal)?) => {
        "GPIO47"
    };
    (SPICLK_N_DIFF $(, $_fallback:literal)?) => {
        "GPIO48"
    };
    (SUBSPICLK_N_DIFF $(, $_fallback:literal)?) => {
        "GPIO48"
    };
    ($_signal:ident, $fallback:literal) => {
        $fallback
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            SPIQ                    = 0,
            SPID                    = 1,
            SPIHD                   = 2,
            SPIWP                   = 3,
            SPID4                   = 7,
            SPID5                   = 8,
            SPID6                   = 9,
            SPID7                   = 10,
            SPIDQS                  = 11,
            U0RXD                   = 12,
            U0CTS                   = 13,
            U0DSR                   = 14,
            U1RXD                   = 15,
            U1CTS                   = 16,
            U1DSR                   = 17,
            U2RXD                   = 18,
            U2CTS                   = 19,
            U2DSR                   = 20,
            I2S1_MCLK               = 21,
            I2S0O_BCK               = 22,
            I2S0_MCLK               = 23,
            I2S0O_WS                = 24,
            I2S0I_SD                = 25,
            I2S0I_BCK               = 26,
            I2S0I_WS                = 27,
            I2S1O_BCK               = 28,
            I2S1O_WS                = 29,
            I2S1I_SD                = 30,
            I2S1I_BCK               = 31,
            I2S1I_WS                = 32,
            PCNT0_SIG_CH0           = 33,
            PCNT0_SIG_CH1           = 34,
            PCNT0_CTRL_CH0          = 35,
            PCNT0_CTRL_CH1          = 36,
            PCNT1_SIG_CH0           = 37,
            PCNT1_SIG_CH1           = 38,
            PCNT1_CTRL_CH0          = 39,
            PCNT1_CTRL_CH1          = 40,
            PCNT2_SIG_CH0           = 41,
            PCNT2_SIG_CH1           = 42,
            PCNT2_CTRL_CH0          = 43,
            PCNT2_CTRL_CH1          = 44,
            PCNT3_SIG_CH0           = 45,
            PCNT3_SIG_CH1           = 46,
            PCNT3_CTRL_CH0          = 47,
            PCNT3_CTRL_CH1          = 48,
            I2S0I_SD1               = 51,
            I2S0I_SD2               = 52,
            I2S0I_SD3               = 53,
            CORE1_GPIO7             = 54,
            USB_EXTPHY_VP           = 55,
            USB_EXTPHY_VM           = 56,
            USB_EXTPHY_RCV          = 57,
            USB_FS_IDDIG            = 58,
            USB_FS_AVALID           = 59,
            USB_FS_SRP_BVALID       = 60,
            USB_FS_VBUSVALID        = 61,
            USB_SRP_SESSEND         = 62,
            SPI3_CLK                = 66,
            SPI3_Q                  = 67,
            SPI3_D                  = 68,
            SPI3_HD                 = 69,
            SPI3_WP                 = 70,
            SPI3_CS0                = 71,
            RMT_SIG_0               = 81,
            RMT_SIG_1               = 82,
            RMT_SIG_2               = 83,
            RMT_SIG_3               = 84,
            I2CEXT0_SCL             = 89,
            I2CEXT0_SDA             = 90,
            I2CEXT1_SCL             = 91,
            I2CEXT1_SDA             = 92,
            FSPICLK                 = 101,
            FSPIQ                   = 102,
            FSPID                   = 103,
            FSPIHD                  = 104,
            FSPIWP                  = 105,
            FSPIIO4                 = 106,
            FSPIIO5                 = 107,
            FSPIIO6                 = 108,
            FSPIIO7                 = 109,
            FSPICS0                 = 110,
            TWAI_RX                 = 116,
            SUBSPIQ                 = 120,
            SUBSPID                 = 121,
            SUBSPIHD                = 122,
            SUBSPIWP                = 123,
            CORE1_GPIO0             = 129,
            CORE1_GPIO1             = 130,
            CORE1_GPIO2             = 131,
            CAM_DATA_0              = 133,
            CAM_DATA_1              = 134,
            CAM_DATA_2              = 135,
            CAM_DATA_3              = 136,
            CAM_DATA_4              = 137,
            CAM_DATA_5              = 138,
            CAM_DATA_6              = 139,
            CAM_DATA_7              = 140,
            CAM_DATA_8              = 141,
            CAM_DATA_9              = 142,
            CAM_DATA_10             = 143,
            CAM_DATA_11             = 144,
            CAM_DATA_12             = 145,
            CAM_DATA_13             = 146,
            CAM_DATA_14             = 147,
            CAM_DATA_15             = 148,
            CAM_PCLK                = 149,
            CAM_H_ENABLE            = 150,
            CAM_H_SYNC              = 151,
            CAM_V_SYNC              = 152,
            SUBSPID4                = 155,
            SUBSPID5                = 156,
            SUBSPID6                = 157,
            SUBSPID7                = 158,
            SUBSPIDQS               = 159,
            PWM0_SYNC0              = 160,
            PWM0_SYNC1              = 161,
            PWM0_SYNC2              = 162,
            PWM0_F0                 = 163,
            PWM0_F1                 = 164,
            PWM0_F2                 = 165,
            PWM0_CAP0               = 166,
            PWM0_CAP1               = 167,
            PWM0_CAP2               = 168,
            PWM1_SYNC0              = 169,
            PWM1_SYNC1              = 170,
            PWM1_SYNC2              = 171,
            PWM1_F0                 = 172,
            PWM1_F1                 = 173,
            PWM1_F2                 = 174,
            PWM1_CAP0               = 175,
            PWM1_CAP1               = 176,
            PWM1_CAP2               = 177,
            SDHOST_CCMD_IN_1        = 178,
            SDHOST_CCMD_IN_2        = 179,
            SDHOST_CDATA_IN_10      = 180,
            SDHOST_CDATA_IN_11      = 181,
            SDHOST_CDATA_IN_12      = 182,
            SDHOST_CDATA_IN_13      = 183,
            SDHOST_CDATA_IN_14      = 184,
            SDHOST_CDATA_IN_15      = 185,
            SDHOST_CDATA_IN_16      = 186,
            SDHOST_CDATA_IN_17      = 187,
            SDHOST_DATA_STROBE_1    = 192,
            SDHOST_DATA_STROBE_2    = 193,
            SDHOST_CARD_DETECT_N_1  = 194,
            SDHOST_CARD_DETECT_N_2  = 195,
            SDHOST_CARD_WRITE_PRT_1 = 196,
            SDHOST_CARD_WRITE_PRT_2 = 197,
            SDHOST_CARD_INT_N_1     = 198,
            SDHOST_CARD_INT_N_2     = 199,
            SDHOST_CDATA_IN_20      = 213,
            SDHOST_CDATA_IN_21      = 214,
            SDHOST_CDATA_IN_22      = 215,
            SDHOST_CDATA_IN_23      = 216,
            SDHOST_CDATA_IN_24      = 217,
            SDHOST_CDATA_IN_25      = 218,
            SDHOST_CDATA_IN_26      = 219,
            SDHOST_CDATA_IN_27      = 220,
            PRO_ALONEGPIO0          = 221,
            PRO_ALONEGPIO1          = 222,
            PRO_ALONEGPIO2          = 223,
            PRO_ALONEGPIO3          = 224,
            PRO_ALONEGPIO4          = 225,
            PRO_ALONEGPIO5          = 226,
            PRO_ALONEGPIO6          = 227,
            PRO_ALONEGPIO7          = 228,
            USB_JTAG_TDO_BRIDGE     = 251,
            CORE1_GPIO3             = 252,
            CORE1_GPIO4             = 253,
            CORE1_GPIO5             = 254,
            CORE1_GPIO6             = 255,
            SPIIO4,
            SPIIO5,
            SPIIO6,
            SPIIO7,
            MTDI,
            MTCK,
            MTMS,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            SPIQ                       = 0,
            SPID                       = 1,
            SPIHD                      = 2,
            SPIWP                      = 3,
            SPICLK                     = 4,
            SPICS0                     = 5,
            SPICS1                     = 6,
            SPID4                      = 7,
            SPID5                      = 8,
            SPID6                      = 9,
            SPID7                      = 10,
            SPIDQS                     = 11,
            U0TXD                      = 12,
            U0RTS                      = 13,
            U0DTR                      = 14,
            U1TXD                      = 15,
            U1RTS                      = 16,
            U1DTR                      = 17,
            U2TXD                      = 18,
            U2RTS                      = 19,
            U2DTR                      = 20,
            I2S1_MCLK                  = 21,
            I2S0O_BCK                  = 22,
            I2S0_MCLK                  = 23,
            I2S0O_WS                   = 24,
            I2S0O_SD                   = 25,
            I2S0I_BCK                  = 26,
            I2S0I_WS                   = 27,
            I2S1O_BCK                  = 28,
            I2S1O_WS                   = 29,
            I2S1O_SD                   = 30,
            I2S1I_BCK                  = 31,
            I2S1I_WS                   = 32,
            CORE1_GPIO7                = 54,
            USB_EXTPHY_OEN             = 55,
            USB_EXTPHY_VPO             = 57,
            USB_EXTPHY_VMO             = 58,
            SPI3_CLK                   = 66,
            SPI3_Q                     = 67,
            SPI3_D                     = 68,
            SPI3_HD                    = 69,
            SPI3_WP                    = 70,
            SPI3_CS0                   = 71,
            SPI3_CS1                   = 72,
            LEDC_LS_SIG0               = 73,
            LEDC_LS_SIG1               = 74,
            LEDC_LS_SIG2               = 75,
            LEDC_LS_SIG3               = 76,
            LEDC_LS_SIG4               = 77,
            LEDC_LS_SIG5               = 78,
            LEDC_LS_SIG6               = 79,
            LEDC_LS_SIG7               = 80,
            RMT_SIG_0                  = 81,
            RMT_SIG_1                  = 82,
            RMT_SIG_2                  = 83,
            RMT_SIG_3                  = 84,
            I2CEXT0_SCL                = 89,
            I2CEXT0_SDA                = 90,
            I2CEXT1_SCL                = 91,
            I2CEXT1_SDA                = 92,
            GPIO_SD0                   = 93,
            GPIO_SD1                   = 94,
            GPIO_SD2                   = 95,
            GPIO_SD3                   = 96,
            GPIO_SD4                   = 97,
            GPIO_SD5                   = 98,
            GPIO_SD6                   = 99,
            GPIO_SD7                   = 100,
            FSPICLK                    = 101,
            FSPIQ                      = 102,
            FSPID                      = 103,
            FSPIHD                     = 104,
            FSPIWP                     = 105,
            FSPIIO4                    = 106,
            FSPIIO5                    = 107,
            FSPIIO6                    = 108,
            FSPIIO7                    = 109,
            FSPICS0                    = 110,
            FSPICS1                    = 111,
            FSPICS2                    = 112,
            FSPICS3                    = 113,
            FSPICS4                    = 114,
            FSPICS5                    = 115,
            TWAI_TX                    = 116,
            SUBSPICLK                  = 119,
            SUBSPIQ                    = 120,
            SUBSPID                    = 121,
            SUBSPIHD                   = 122,
            SUBSPIWP                   = 123,
            SUBSPICS0                  = 124,
            SUBSPICS1                  = 125,
            FSPIDQS                    = 126,
            SPI3_CS2                   = 127,
            I2S0O_SD1                  = 128,
            CORE1_GPIO0                = 129,
            CORE1_GPIO1                = 130,
            CORE1_GPIO2                = 131,
            LCD_CS                     = 132,
            LCD_DATA_0                 = 133,
            LCD_DATA_1                 = 134,
            LCD_DATA_2                 = 135,
            LCD_DATA_3                 = 136,
            LCD_DATA_4                 = 137,
            LCD_DATA_5                 = 138,
            LCD_DATA_6                 = 139,
            LCD_DATA_7                 = 140,
            LCD_DATA_8                 = 141,
            LCD_DATA_9                 = 142,
            LCD_DATA_10                = 143,
            LCD_DATA_11                = 144,
            LCD_DATA_12                = 145,
            LCD_DATA_13                = 146,
            LCD_DATA_14                = 147,
            LCD_DATA_15                = 148,
            CAM_CLK                    = 149,
            LCD_H_ENABLE               = 150,
            LCD_H_SYNC                 = 151,
            LCD_V_SYNC                 = 152,
            LCD_DC                     = 153,
            LCD_PCLK                   = 154,
            SUBSPID4                   = 155,
            SUBSPID5                   = 156,
            SUBSPID6                   = 157,
            SUBSPID7                   = 158,
            SUBSPIDQS                  = 159,
            PWM0_0A                    = 160,
            PWM0_0B                    = 161,
            PWM0_1A                    = 162,
            PWM0_1B                    = 163,
            PWM0_2A                    = 164,
            PWM0_2B                    = 165,
            PWM1_0A                    = 166,
            PWM1_0B                    = 167,
            PWM1_1A                    = 168,
            PWM1_1B                    = 169,
            PWM1_2A                    = 170,
            PWM1_2B                    = 171,
            SDHOST_CCLK_OUT_1          = 172,
            SDHOST_CCLK_OUT_2          = 173,
            SDHOST_RST_N_1             = 174,
            SDHOST_RST_N_2             = 175,
            SDHOST_CCMD_OD_PULLUP_EN_N = 176,
            SDIO_TOHOST_INT            = 177,
            SDHOST_CCMD_OUT_1          = 178,
            SDHOST_CCMD_OUT_2          = 179,
            SDHOST_CDATA_OUT_10        = 180,
            SDHOST_CDATA_OUT_11        = 181,
            SDHOST_CDATA_OUT_12        = 182,
            SDHOST_CDATA_OUT_13        = 183,
            SDHOST_CDATA_OUT_14        = 184,
            SDHOST_CDATA_OUT_15        = 185,
            SDHOST_CDATA_OUT_16        = 186,
            SDHOST_CDATA_OUT_17        = 187,
            SDHOST_CDATA_OUT_20        = 213,
            SDHOST_CDATA_OUT_21        = 214,
            SDHOST_CDATA_OUT_22        = 215,
            SDHOST_CDATA_OUT_23        = 216,
            SDHOST_CDATA_OUT_24        = 217,
            SDHOST_CDATA_OUT_25        = 218,
            SDHOST_CDATA_OUT_26        = 219,
            SDHOST_CDATA_OUT_27        = 220,
            PRO_ALONEGPIO0             = 221,
            PRO_ALONEGPIO1             = 222,
            PRO_ALONEGPIO2             = 223,
            PRO_ALONEGPIO3             = 224,
            PRO_ALONEGPIO4             = 225,
            PRO_ALONEGPIO5             = 226,
            PRO_ALONEGPIO6             = 227,
            PRO_ALONEGPIO7             = 228,
            USB_JTAG_TRST              = 251,
            CORE1_GPIO3                = 252,
            CORE1_GPIO4                = 253,
            CORE1_GPIO5                = 254,
            CORE1_GPIO6                = 255,
            GPIO                       = 256,
            SPIIO4,
            SPIIO5,
            SPIIO6,
            SPIIO7,
            CLK_OUT1,
            CLK_OUT2,
            CLK_OUT3,
            SPICLK_P_DIFF,
            SPICLK_N_DIFF,
            SUBSPICLK_P_DIFF,
            SUBSPICLK_N_DIFF,
            MTDO,
        }
    };
}
/// Defines the `LpFunction` enum.
///
/// The enum only contains the LP IO MUX functions that the chip implements. It is
/// empty on chips without an LP IO peripheral.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_functions {
    () => {
        /// LP IO MUX function of a pad.
        ///
        /// This is the low-power counterpart of `AlternateFunction`: it selects which function
        /// drives a pad while the pad belongs to the low-power domain.
        #[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpFunction {
            /// LP IO MUX function 0.
            _0 = 0,
            /// LP IO MUX function 3.
            _3 = 3,
        }
        impl LpFunction {
            /// The function that connects the pad to the LP GPIO peripheral.
            pub const LP_GPIO: Self = Self::_0;
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO {
            crate::peripherals::IO_MUX::regs().gpio(gpio_num as usize)
        }
    };
}