esp_rom_sys/rom/
mod.rs

1//! # Wrappers for selected ROM functions
2//!
3//! ## Overview
4//!
5//! For some selected ROM functions safe wrappers are provided for convenience.
6
7#[cfg(any(rom_crc_be, rom_crc_le))]
8pub mod crc;
9#[cfg(any(rom_md5_bsd, rom_md5_mbedtls))]
10pub mod md5;
11pub mod spiflash;
12
13/// Busy-loop CPU for the given about of us.
14#[inline(always)]
15pub fn ets_delay_us(us: u32) {
16    unsafe extern "C" {
17        fn ets_delay_us(us: u32);
18    }
19
20    unsafe { ets_delay_us(us) };
21}
22
23/// Set the real CPU ticks per us to the ets, so that ets_delay_us will be
24/// accurate. Call this function when CPU frequency is changed.
25#[inline(always)]
26pub fn ets_update_cpu_frequency_rom(ticks_per_us: u32) {
27    unsafe extern "C" {
28        fn ets_update_cpu_frequency(ticks_per_us: u32);
29    }
30
31    unsafe { ets_update_cpu_frequency(ticks_per_us) };
32}
33
34/// Get the reset reason for CPU.
35#[inline(always)]
36pub fn rtc_get_reset_reason(cpu_num: u32) -> u32 {
37    unsafe extern "C" {
38        fn rtc_get_reset_reason(cpu_num: u32) -> u32;
39    }
40
41    unsafe { rtc_get_reset_reason(cpu_num) }
42}
43
44/// Software Reset digital core.
45#[inline(always)]
46pub fn software_reset_cpu(cpu_num: u32) {
47    unsafe extern "C" {
48        fn software_reset_cpu(cpu_num: u32);
49    }
50
51    unsafe { software_reset_cpu(cpu_num) };
52}
53
54/// Software Reset digital core.
55#[inline(always)]
56pub fn software_reset() -> ! {
57    unsafe extern "C" {
58        fn software_reset() -> !;
59    }
60
61    unsafe { software_reset() }
62}
63
64/// Set App cpu Entry code, code can be called in PRO CPU.
65#[cfg(esp32s3)]
66#[inline(always)]
67pub fn ets_set_appcpu_boot_addr(boot_addr: u32) {
68    unsafe extern "C" {
69        fn ets_set_appcpu_boot_addr(boot_addr: u32);
70    }
71
72    unsafe { ets_set_appcpu_boot_addr(boot_addr) };
73}
74
75// libphy.a can pull this in on some chips, we provide it here
76// so that either ieee or esp-wifi gets it for free without duplicating in both
77#[unsafe(no_mangle)]
78extern "C" fn rtc_clk_xtal_freq_get() -> i32 {
79    cfg_if::cfg_if! {
80        if #[cfg(any(esp32c6, esp32h2))] {
81            unsafe extern "C" {
82                fn ets_clk_get_xtal_freq() -> i32;
83            }
84            (unsafe { ets_clk_get_xtal_freq() }) / 1_000_000
85        } else if #[cfg(any(esp32s2, esp32s3, esp32c3))] {
86            unsafe extern "C" {
87                fn ets_get_xtal_freq() -> i32;
88            }
89            (unsafe { ets_get_xtal_freq() }) / 1_000_000
90        } else if #[cfg(esp32)] {
91            // the ROM function returns something close to 80_000_000
92            // just rely on RTC_CNTL_STORE4
93            let rtc_cntl_store4: *const u32 = 0x3FF480B0 as *const u32;
94            ((unsafe { rtc_cntl_store4.read_volatile() })  & 0xff) as i32
95        } else if #[cfg(esp32c2)] {
96            // the ROM function returns 40 also for a 26 MHz xtal
97            // just rely on RTC_CNTL_STORE4
98            let rtc_cntl_store4: *const u32 = 0x600080AC  as *const u32;
99            ((unsafe { rtc_cntl_store4.read_volatile() })  & 0xff) as i32
100        } else {
101            compile_error!("rtc_clk_xtal_freq_get not implemented for this chip");
102        }
103    }
104}
esp_rom_sys/rom/mod.rs

esp_rom_sys/rom/
mod.rs
