esp_rom_sys/rom/
spiflash.rs

1//! Definitions of ROM functions related to flash memory.
2
3/// The operation succeeded
4pub const ESP_ROM_SPIFLASH_RESULT_OK: i32 = 0;
5
6/// The operation errored
7pub const ESP_ROM_SPIFLASH_RESULT_ERR: i32 = 1;
8
9/// The operation timed out
10pub const ESP_ROM_SPIFLASH_RESULT_TIMEOUT: i32 = 2;
11
12unsafe extern "C" {
13    /// Read Data from Flash via ROM code, you should Erase it yourself if need.
14    ///
15    /// `src_addr` should be 4 bytes aligned.
16    /// `len` should be 4 bytes aligned.
17    pub fn esp_rom_spiflash_read(src_addr: u32, data: *const u32, len: u32) -> i32;
18
19    /// Clear all SR bits except QE bit.
20    pub fn esp_rom_spiflash_unlock() -> i32;
21
22    /// Erase a sector of flash. Uses SPI flash command 20H.
23    pub fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32;
24
25    /// Erase a block of flash.
26    pub fn esp_rom_spiflash_erase_block(block_number: u32) -> i32;
27
28    /// Write Data to Flash, you should Erase it yourself if need.
29    ///
30    /// `dest_addr` should be 4 bytes aligned.
31    /// `len` should be 4 bytes aligned.
32    pub fn esp_rom_spiflash_write(dest_addr: u32, data: *const u32, len: u32) -> i32;
33
34    /// Write data to flash with transparent encryption.
35    ///
36    /// `flash_addr` and `len` must be 32-byte aligned. The sector must already be
37    /// erased.
38    pub fn esp_rom_spiflash_write_encrypted(flash_addr: u32, data: *mut u32, len: u32) -> i32;
39
40    /// Enable SPI flash encryption mode.
41    pub fn esp_rom_spiflash_write_encrypted_enable();
42
43    /// Disable SPI flash encryption mode.
44    pub fn esp_rom_spiflash_write_encrypted_disable();
45
46    /// Prepare 32 bytes of data for encrypted writing (ESP32 only).
47    #[cfg(esp32)]
48    pub fn esp_rom_spiflash_prepare_encrypted_data(flash_addr: u32, data: *mut u32) -> i32;
49}
esp_rom_sys/rom/spiflash.rs

esp_rom_sys/rom/
spiflash.rs
