xtensa_lx_rt/
lib.rs

1//! Minimal startup/runtime for Xtensa LX CPUs.
2//!
3//! ## Minimum Supported Rust Version (MSRV)
4//!
5//! This crate is guaranteed to compile on stable Rust 1.65 and up. It might
6//! compile with older versions but that may change in any new patch release.
7//!
8//! ## Feature Flags
9#![doc = document_features::document_features!()]
10#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
11#![allow(asm_sub_register, named_asm_labels)]
12#![feature(asm_experimental_arch, naked_functions)]
13#![no_std]
14
15use core::{
16    arch::asm,
17    ptr::{addr_of, addr_of_mut},
18};
19
20pub use macros::{entry, exception, interrupt, pre_init};
21pub use r0::{init_data, zero_bss};
22pub use xtensa_lx;
23
24pub mod exception;
25pub mod interrupt;
26
27#[doc(hidden)]
28#[unsafe(no_mangle)]
29pub unsafe extern "C" fn DefaultPreInit() {}
30
31#[doc(hidden)]
32#[unsafe(no_mangle)]
33pub unsafe extern "C" fn Reset() -> ! {
34    unsafe {
35        // These symbols come from `link.x`
36        unsafe extern "C" {
37            static mut _bss_start: u32;
38            static mut _bss_end: u32;
39
40            static mut _data_start: u32;
41            static mut _data_end: u32;
42            static _sidata: u32;
43
44            static mut _init_start: u32;
45
46        }
47
48        unsafe extern "Rust" {
49            // This symbol will be provided by the user via `#[entry]`
50            fn main() -> !;
51
52            // This symbol will be provided by the user via `#[pre_init]`
53            fn __pre_init();
54
55            fn __post_init();
56
57            fn __zero_bss() -> bool;
58
59            fn __init_data() -> bool;
60        }
61
62        __pre_init();
63
64        if __zero_bss() {
65            r0::zero_bss(addr_of_mut!(_bss_start), addr_of_mut!(_bss_end));
66        }
67
68        if __init_data() {
69            r0::init_data(addr_of_mut!(_data_start), addr_of_mut!(_data_end), &_sidata);
70        }
71
72        // Copy of data segment is done by bootloader
73
74        // According to 4.4.6.2 of the xtensa isa, ccount and compare are undefined on
75        // reset, set all values to zero to disable
76        reset_internal_timers();
77
78        // move vec table
79        set_vecbase(addr_of!(_init_start));
80
81        __post_init();
82
83        main();
84    }
85}
86
87#[doc(hidden)]
88#[unsafe(no_mangle)]
89#[rustfmt::skip]
90pub unsafe extern "Rust" fn default_post_init() {}
91
92// We redefine these functions to avoid pulling in `xtensa-lx` as a dependency:
93
94#[doc(hidden)]
95#[inline]
96unsafe fn reset_internal_timers() {
97    unsafe {
98        #[cfg(any(
99            XCHAL_HAVE_TIMER0,
100            XCHAL_HAVE_TIMER1,
101            XCHAL_HAVE_TIMER2,
102            XCHAL_HAVE_TIMER3
103        ))]
104        {
105            let value = 0;
106            cfg_asm!(
107        {
108            #[cfg(XCHAL_HAVE_TIMER0)]
109            "wsr.ccompare0 {0}",
110            #[cfg(XCHAL_HAVE_TIMER1)]
111            "wsr.ccompare1 {0}",
112            #[cfg(XCHAL_HAVE_TIMER2)]
113            "wsr.ccompare2 {0}",
114            #[cfg(XCHAL_HAVE_TIMER3)]
115            "wsr.ccompare3 {0}",
116            "isync",
117        }, in(reg) value, options(nostack));
118        }
119    }
120}
121
122// CPU Interrupts
123unsafe extern "C" {
124    #[cfg(XCHAL_HAVE_TIMER0)]
125    pub fn Timer0(save_frame: &mut crate::exception::Context);
126    #[cfg(XCHAL_HAVE_TIMER1)]
127    pub fn Timer1(save_frame: &mut crate::exception::Context);
128    #[cfg(XCHAL_HAVE_TIMER2)]
129    pub fn Timer2(save_frame: &mut crate::exception::Context);
130    #[cfg(XCHAL_HAVE_TIMER3)]
131    pub fn Timer3(save_frame: &mut crate::exception::Context);
132
133    #[cfg(XCHAL_HAVE_PROFILING)]
134    pub fn Profiling(save_frame: &mut crate::exception::Context);
135
136    #[cfg(XCHAL_HAVE_SOFTWARE0)]
137    pub fn Software0(save_frame: &mut crate::exception::Context);
138    #[cfg(XCHAL_HAVE_SOFTWARE1)]
139    pub fn Software1(save_frame: &mut crate::exception::Context);
140
141    #[cfg(XCHAL_HAVE_NMI)]
142    pub fn NMI(save_frame: &mut crate::exception::Context);
143}
144
145#[doc(hidden)]
146#[inline]
147unsafe fn set_vecbase(base: *const u32) {
148    unsafe {
149        asm!("wsr.vecbase {0}", in(reg) base, options(nostack));
150    }
151}
152
153#[doc(hidden)]
154#[unsafe(no_mangle)]
155#[rustfmt::skip]
156pub extern "Rust" fn default_mem_hook() -> bool {
157    true // default to zeroing bss & initializing data
158}
159
160#[doc(hidden)]
161#[macro_export]
162macro_rules! cfg_asm {
163    (@inner, [$($x:tt)*], [$($opts:tt)*], ) => {
164        asm!($($x)* $($opts)*)
165    };
166    (@inner, [$($x:tt)*], [$($opts:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
167        #[cfg($meta)]
168        cfg_asm!(@inner, [$($x)* $asm,], [$($opts)*], $($rest)*);
169        #[cfg(not($meta))]
170        cfg_asm!(@inner, [$($x)*], [$($opts)*], $($rest)*)
171    };
172    (@inner, [$($x:tt)*], [$($opts:tt)*], $asm:literal, $($rest:tt)*) => {
173        cfg_asm!(@inner, [$($x)* $asm,], [$($opts)*], $($rest)*)
174    };
175    ({$($asms:tt)*}, $($opts:tt)*) => {
176        cfg_asm!(@inner, [], [$($opts)*], $($asms)*)
177    };
178}
179
180#[doc(hidden)]
181#[macro_export]
182macro_rules! cfg_global_asm {
183    {@inner, [$($x:tt)*], } => {
184        global_asm!{$($x)*}
185    };
186    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
187        #[cfg($meta)]
188        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
189        #[cfg(not($meta))]
190        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
191    };
192    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
193        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
194    };
195    {$($asms:tt)*} => {
196        cfg_global_asm!{@inner, [], $($asms)*}
197    };
198}
xtensa_lx_rt/lib.rs

xtensa_lx_rt/
lib.rs
