xtensa_lx_rt/
exception.rs

1//! Exception handling
2//!
3//! Currently specialized for ESP32 (LX6) configuration: which extra registers
4//! to store, how many interrupt levels etc.
5//!
6//! First level interrupts and exceptions save full processor state to the user
7//! stack. This includes the coprocessor registers contrary to the esp-idf where
8//! these are lazily saved. (Kernel mode option is currently not used.)
9//!
10//! WindowUnder/Overflow and AllocA use default Xtensa implementation.
11//!
12//! LoadStoreError and Unaligned are not (yet) implemented: so all accesses to
13//! IRAM must be word sized and aligned.
14//!
15//! Syscall 0 is not (yet) implemented: it doesn't seem to be used in rust.
16//!
17//! Double Exceptions can only occur during the early setup of the exception
18//! handler. Afterwards PS.EXCM is set to 0 to be able to handle
19//! WindowUnderflow/Overflow and recursive exceptions will happen instead.
20//!
21//! In various places call0 are used as long jump: `j.l` syntax is not supported
22//! and `call0` can always be expanded to `mov a0,label; call a0`. Care must be
23//! taken since A0 is overwritten.
24
25mod asm;
26mod context;
27
28pub use context::Context;
29
30/// EXCCAUSE register values
31///
32/// General Exception Causes. (Values of EXCCAUSE special register set by
33/// general exceptions, which vector to the user, kernel, or double-exception
34/// vectors).
35#[allow(unused)]
36#[derive(Debug, PartialEq)]
37#[repr(C)]
38pub enum ExceptionCause {
39    /// Illegal Instruction
40    Illegal                        = 0,
41    /// System Call (Syscall Instruction)
42    Syscall                        = 1,
43    /// Instruction Fetch Error
44    InstrError                     = 2,
45    /// Load Store Error
46    LoadStoreError                 = 3,
47    /// Level 1 Interrupt
48    LevelOneInterrupt              = 4,
49    /// Stack Extension Assist (movsp Instruction) For Alloca
50    Alloca                         = 5,
51    /// Integer Divide By Zero
52    DivideByZero                   = 6,
53    /// Use Of Failed Speculative Access (Not Implemented)
54    NextPCValueIllegal             = 7,
55    /// Privileged Instruction
56    Privileged                     = 8,
57    /// Unaligned Load Or Store
58    Unaligned                      = 9,
59    /// Reserved
60    ExternalRegisterPrivilegeError = 10,
61    /// Reserved
62    ExclusiveError                 = 11,
63    /// Pif Data Error On Instruction Fetch (Rb-200x And Later)
64    InstrDataError                 = 12,
65    /// Pif Data Error On Load Or Store (Rb-200x And Later)
66    LoadStoreDataError             = 13,
67    /// Pif Address Error On Instruction Fetch (Rb-200x And Later)
68    InstrAddrError                 = 14,
69    /// Pif Address Error On Load Or Store (Rb-200x And Later)
70    LoadStoreAddrError             = 15,
71    /// Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)
72    ItlbMiss                       = 16,
73    /// Itlb Multihit (Multiple Itlb Entries Match)
74    ItlbMultiHit                   = 17,
75    /// Ring Privilege Violation On Instruction Fetch
76    InstrRing                      = 18,
77    /// Size Restriction On Ifetch (Not Implemented)
78    Reserved19                     = 19,
79    /// Cache Attribute Does Not Allow Instruction Fetch
80    InstrProhibited                = 20,
81    /// Reserved
82    Reserved21                     = 21,
83    /// Reserved
84    Reserved22                     = 22,
85    /// Reserved
86    Reserved23                     = 23,
87    /// Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)
88    DtlbMiss                       = 24,
89    /// Dtlb Multihit (Multiple Dtlb Entries Match)
90    DtlbMultiHit                   = 25,
91    /// Ring Privilege Violation On Load Or Store
92    LoadStoreRing                  = 26,
93    /// Size Restriction On Load/Store (Not Implemented)
94    Reserved27                     = 27,
95    /// Cache Attribute Does Not Allow Load
96    LoadProhibited                 = 28,
97    /// Cache Attribute Does Not Allow Store
98    StoreProhibited                = 29,
99    /// Reserved
100    Reserved30                     = 30,
101    /// Reserved
102    Reserved31                     = 31,
103    /// Access To Coprocessor 0 When Disabled
104    Cp0Disabled                    = 32,
105    /// Access To Coprocessor 1 When Disabled
106    Cp1Disabled                    = 33,
107    /// Access To Coprocessor 2 When Disabled
108    Cp2Disabled                    = 34,
109    /// Access To Coprocessor 3 When Disabled
110    Cp3Disabled                    = 35,
111    /// Access To Coprocessor 4 When Disabled
112    Cp4Disabled                    = 36,
113    /// Access To Coprocessor 5 When Disabled
114    Cp5Disabled                    = 37,
115    /// Access To Coprocessor 6 When Disabled
116    Cp6Disabled                    = 38,
117    /// Access To Coprocessor 7 When Disabled
118    Cp7Disabled                    = 39,
119
120    None                           = 255,
121}
xtensa_lx_rt/exception.rs

xtensa_lx_rt/
exception.rs
