xtensa_lx_rt/
exception.rs

1//! Exception handling
2//!
3//! Currently specialized for ESP32 (LX6) configuration: which extra registers
4//! to store, how many interrupt levels etc.
5//!
6//! First level interrupts and exceptions save full processor state to the user
7//! stack. This includes the coprocessor registers contrary to the esp-idf where
8//! these are lazily saved. (Kernel mode option is currently not used.)
9//!
10//! WindowUnder/Overflow and AllocA use default Xtensa implementation.
11//!
12//! LoadStoreError and Unaligned are not (yet) implemented: so all accesses to
13//! IRAM must be word sized and aligned.
14//!
15//! Syscall 0 is not (yet) implemented: it doesn't seem to be used in rust.
16//!
17//! Double Exceptions can only occur during the early setup of the exception
18//! handler. Afterwards PS.EXCM is set to 0 to be able to handle
19//! WindowUnderflow/Overflow and recursive exceptions will happen instead.
20//!
21//! In various places call0 are used as long jump: `j.l` syntax is not supported
22//! and `call0` can always be expanded to `mov a0,label; call a0`. Care must be
23//! taken since A0 is overwritten.
24
25mod asm;
26mod context;
27
28pub use context::Context;
29
30/// EXCCAUSE register values
31///
32/// General Exception Causes. (Values of EXCCAUSE special register set by
33/// general exceptions, which vector to the user, kernel, or double-exception
34/// vectors).
35#[allow(unused)]
36#[derive(Debug, PartialEq)]
37#[cfg_attr(feature = "defmt", derive(defmt::Format))]
38#[repr(C)]
39pub enum ExceptionCause {
40    /// Illegal Instruction
41    Illegal                        = 0,
42    /// System Call (Syscall Instruction)
43    Syscall                        = 1,
44    /// Instruction Fetch Error
45    InstrError                     = 2,
46    /// Load Store Error
47    LoadStoreError                 = 3,
48    /// Level 1 Interrupt
49    LevelOneInterrupt              = 4,
50    /// Stack Extension Assist (movsp Instruction) For Alloca
51    Alloca                         = 5,
52    /// Integer Divide By Zero
53    DivideByZero                   = 6,
54    /// Use Of Failed Speculative Access (Not Implemented)
55    NextPCValueIllegal             = 7,
56    /// Privileged Instruction
57    Privileged                     = 8,
58    /// Unaligned Load Or Store
59    Unaligned                      = 9,
60    /// Reserved
61    ExternalRegisterPrivilegeError = 10,
62    /// Reserved
63    ExclusiveError                 = 11,
64    /// Pif Data Error On Instruction Fetch (Rb-200x And Later)
65    InstrDataError                 = 12,
66    /// Pif Data Error On Load Or Store (Rb-200x And Later)
67    LoadStoreDataError             = 13,
68    /// Pif Address Error On Instruction Fetch (Rb-200x And Later)
69    InstrAddrError                 = 14,
70    /// Pif Address Error On Load Or Store (Rb-200x And Later)
71    LoadStoreAddrError             = 15,
72    /// Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)
73    ItlbMiss                       = 16,
74    /// Itlb Multihit (Multiple Itlb Entries Match)
75    ItlbMultiHit                   = 17,
76    /// Ring Privilege Violation On Instruction Fetch
77    InstrRing                      = 18,
78    /// Size Restriction On Ifetch (Not Implemented)
79    Reserved19                     = 19,
80    /// Cache Attribute Does Not Allow Instruction Fetch
81    InstrProhibited                = 20,
82    /// Reserved
83    Reserved21                     = 21,
84    /// Reserved
85    Reserved22                     = 22,
86    /// Reserved
87    Reserved23                     = 23,
88    /// Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)
89    DtlbMiss                       = 24,
90    /// Dtlb Multihit (Multiple Dtlb Entries Match)
91    DtlbMultiHit                   = 25,
92    /// Ring Privilege Violation On Load Or Store
93    LoadStoreRing                  = 26,
94    /// Size Restriction On Load/Store (Not Implemented)
95    Reserved27                     = 27,
96    /// Cache Attribute Does Not Allow Load
97    LoadProhibited                 = 28,
98    /// Cache Attribute Does Not Allow Store
99    StoreProhibited                = 29,
100    /// Reserved
101    Reserved30                     = 30,
102    /// Reserved
103    Reserved31                     = 31,
104    /// Access To Coprocessor 0 When Disabled
105    Cp0Disabled                    = 32,
106    /// Access To Coprocessor 1 When Disabled
107    Cp1Disabled                    = 33,
108    /// Access To Coprocessor 2 When Disabled
109    Cp2Disabled                    = 34,
110    /// Access To Coprocessor 3 When Disabled
111    Cp3Disabled                    = 35,
112    /// Access To Coprocessor 4 When Disabled
113    Cp4Disabled                    = 36,
114    /// Access To Coprocessor 5 When Disabled
115    Cp5Disabled                    = 37,
116    /// Access To Coprocessor 6 When Disabled
117    Cp6Disabled                    = 38,
118    /// Access To Coprocessor 7 When Disabled
119    Cp7Disabled                    = 39,
120
121    None                           = 255,
122}
xtensa_lx_rt/exception.rs

xtensa_lx_rt/
exception.rs
