xtensa_lx/
timer.rs

1//! Xtensa internal timers
2
3use core::arch::asm;
4
5#[inline]
6pub fn get_ccompare0() -> u32 {
7    let x: u32;
8    unsafe { asm!("rsr.ccompare0 {0}", out(reg) x, options(nostack)) };
9    x
10}
11
12#[inline]
13pub fn get_ccompare1() -> u32 {
14    let x: u32;
15    unsafe { asm!("rsr.ccompare1 {0}", out(reg) x, options(nostack)) };
16    x
17}
18
19#[inline]
20pub fn get_ccompare2() -> u32 {
21    let x: u32;
22    unsafe { asm!("rsr.ccompare2 {0}", out(reg) x, options(nostack)) };
23    x
24}
25
26#[inline]
27pub fn get_ccompare3() -> u32 {
28    let x: u32;
29    unsafe { asm!("rsr.ccompare3 {0}", out(reg) x, options(nostack)) };
30    x
31}
32
33#[inline]
34pub fn set_ccompare0(val: u32) {
35    unsafe {
36        asm!("
37        wsr.ccompare0 {0}
38        isync
39        ", in(reg) val, options(nostack))
40    };
41}
42
43#[inline]
44pub fn set_ccompare1(val: u32) {
45    unsafe {
46        asm!("
47        wsr.ccompare1 {0}
48        isync
49        ", in(reg) val, options(nostack))
50    };
51}
52
53#[inline]
54pub fn set_ccompare2(val: u32) {
55    unsafe {
56        asm!("
57        wsr.ccompare2 {0}
58        isync
59        ", in(reg) val, options(nostack))
60    };
61}
62
63#[inline]
64pub fn set_ccompare3(val: u32) {
65    unsafe {
66        asm!("
67        wsr.ccompare3 {0}
68        isync
69        ", in(reg) val, options(nostack))
70    };
71}
72
73/// Get the core cycle count
74#[inline]
75pub fn get_cycle_count() -> u32 {
76    let x: u32;
77    unsafe { asm!("rsr.ccount {0}", out(reg) x, options(nostack)) };
78    x
79}
80
81/// cycle accurate delay using the cycle counter register
82#[inline]
83pub fn delay(clocks: u32) {
84    let start = get_cycle_count();
85    loop {
86        if get_cycle_count().wrapping_sub(start) >= clocks {
87            break;
88        }
89    }
90}
xtensa_lx/timer.rs

xtensa_lx/
timer.rs
