All Errata Descriptions
[System] Leakage current at the VDDA and VDD3P3_RTC pin during shutdown
Description
When a chip is connected to the power supply, but the CHIP_PU pin is held low (meaning that the chip powers off), there will be a leakage current in the µA range at power pins such as VDDA and VDD3P3_RTC.
Workarounds
None.
Solution
Fixed in chip revision v1.0.
[System] Random flash download failure
Description
In download mode, the first stage bootloader in ROM receives serial data from two different input pins. Among the two intput pins, pin 24 DAC_2 (GPIO18) is not pulled up by default. If this pin is not pulled up in PCB design and is left floating, in download mode the first stage bootloader will not function properly (including download applications) due to interference.
Workarounds
This problem can be bypassed in PCB design by pulling up pin 24 DAC_2. The typical value of the pull-up resistor is 10 kΩ. All official development boards by Espressif pull this pin up, while official modules are not.
Solution
Fixed in chip revision v1.0 by pulling pin 24 up by default.
[RTC I2C] The falling edge of RTC_I2C_RESET triggers reset at low temperature
Description
At –40 °C, the chip will be restarted during wake-up.
Workarounds
None.
Solution
Fixed in chip revision v1.0.
[SPI] SPI is stuck after soft restart from auto suspension
Description
After auto suspend is enabled, if caching is requested while Memory SPI is erasing flash, Memory SPI will automatically send a SUSPEND command (0×75). If there is a system reset, and Memory SPI is restarted before sending a RESUME command (0×7A), the state machine of Memory SPI will not be restored. As a result, the system cannot continue operations.
Workarounds
Disable auto suspend function.
Solution
Fixed in chip revision v1.0.
[USB OTG] Abnormal data during AHB bus arbitration by USB OTG
Description
When the USB OTG peripheral and some other competing peripherals (listed below) simultaneously execute a request on the Advanced High-performance Bus (AHB), the AHB may generate incorrect arbitration signals, which results in the USB OTG peripheral reading or writing erroneous data. The competing peripherals include:
I2S
SPI
Workarounds
Avoid AHB bus competition between USB OTG and above peripherals by not using DMA mode of USB OTG, or disabling DMA mode of above peripherals.
Avoid competing with the USB OTG’s AHB bus access. Specifically, set USB OTG’s AHB burst transfer mode to INCR to prevent competition from the other peripherals. In this mode, USB OTG will occupy the AHB bus exclusively until the burst transfer is completed.
Note
Use the INCR burst mode with care, as it requires adjustment to maximum packet size (MPS) for USB OTG endpoints, so that burst time is smaller than the timeout period of the competing peripherals.
Solution
Fixed in chip revision v1.0. With this fix, the AHB bus will correctly arbitrate competing access. ESP-IDF adds USB OTG support starting from v4.4. When the specific conditions listed below are met, ESP-IDF enables the INCR mode workaround, i.e., using the INCR mode to guarantee that the USB OTG’s exclusive access to the AHB. The conditions for ESP-IDF to enable this workaround are as follows:
For chip revision v0.0, ESP-IDF always enables the workaround.
ESP-IDF added support for chip revision v1.0 in ESP-IDF v4.4.6, v5.0.4, v5.1.2, and v5.2. In these and above version, the software automatically detects the chip revision. When chip revision v1.0 or later revisions are detected, ESP-IDF no longer enables the workaround.
In ESP-IDF versions that do not support chip revision v1.0, i.e., v4.4-v4.4.5, v5.0-v5.0.3, v5.1-v5.1.1, ESP-IDF always enables the workaround.
[SAR ADC] Bit 1 of SAR ADC does not flip
Description
Bit 1 of SAR ADC is always 0, and does not change with measured voltage.
Workarounds
None.
Solution
Fixed in chip revision v1.0. The effective resolution of SAR ADC on chip revision v1.0 is changed from 13 bits to 12 bits. That is, bit 0 is not valid, and the valid bits are bit 1 ∼ bit 12 inclusive.
[RTC] RTC Register Read Error After Wake-up from Light-sleep Mode
Description
If an RTC peripheral is turned off in Light-sleep mode, there is a certain probability that after waking up from Light-sleep, the CPU of ESP32-S2 will read the registers in the RTC power domain incorrectly.
Workarounds
Users are suggested not to power down RTC peripherals in Light-sleep mode. There will be no impact on power consumption.
Solution
No fix scheduled.
[Touch Sensor] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined
Description
For ESP32-S2’s touch sensor, the raw data value is undefined for the first two TOUCH_SCAN_DONE_INT interrupts.
Workarounds
Users are suggested to skip the first two TOUCH_SCAN_DONE_INT interrupts, then turn them off and stop using them.
This issue has been bypassed in all versions of ESP-IDF through this method.
This issue has been bypassed in the Touch Element component (touch_element) in ESP-IDF (introduced in ESP-IDF release version v4.3). If you are directly developing on the lower-level touch sensor driver, please follow the implementation provided within the Touch Element component and the recommendations mentioned above to bypass the issue.
Solution
No fix scheduled.
[Touch Sensor] The scan done interrupt RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA occurs twice during a single scan
Description
The touch sensor of ESP32-S2 triggered the scan done interrupt RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA twice during a single scan, occurring when scanning the last two channels.
Workarounds
Users are suggested to register one more interrupt in the RTC driver to filter, checking if the current measuring channel is the last channel. If it is not the last channel, then clear the RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA interrupt directly. If it is, then the current RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA interrupt can be regarded as a valid interrupt. This issue has been bypassed in all versions of ESP-IDF through this method.
Solution
No fix scheduled.