Schematic Checklist
The integrated circuitry of ESP32 requires only 20 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32.
The following figure shows a reference schematic design of ESP32. It can be used as the basis of your schematic design.
ESP32 Reference Schematic
Note that Figure ESP32 Reference Schematic shows the connection for quad 3.3 V external flash/PSRAM. PSRAM’s SCLK and flash can share the clock from SD_CLK or GPIO17.
In cases where quad 1.8 V external flash/PSRAM is used, R9 should be populated.
In cases where ESP32-D0WDR2-V3 with in-package quad 3.3 V PSRAM is used, the external flash can be connected as Figure ESP32 Reference Schematic shows.
In cases where ESP32-U4WDH with in-package quad 3.3 V flash is used, the in-package flash is connected as Figure ESP32 Schematic for Quad 3.3 V In-Package Flash shows.
ESP32 Schematic for Quad 3.3 V In-Package Flash
Any basic ESP32 circuit design may be broken down into the following major building blocks:
The rest of this chapter details the specifics of circuit design for each of these sections.
Power Supply
The general recommendations for power supply design are:
When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA.
It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32 Series Datasheet > Section Power Supply.
Digital Power Supply
ESP32 has pin37 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 1.8 V ~ 3.6 V. It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SDIO can serve as the power supply for the external device at either 1.8 V or 3.3 V (default).
When VDD_SDIO operates at 1.8 V, it is powered by ESP32’s internal LDO. The maximum current this LDO can offer is 40 mA, and the output voltage range is 1.65 V ~ 2.0 V. When the VDD_SDIO outputs 1.8 V, it is recommended that users add a 2 kΩ ground resistor and a 4.7 μF ground capacitor close to VDD_SDIO. See Figure ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin.
When VDD_SDIO operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 6 Ω resistor (internal to the chip), therefore, there will be some voltage drop from VDD3P3_RTC. When the VDD_SDIO outputs 3.3 V, it is recommended that users add a 1 μF filter capacitor close to VDD_SDIO. See Figure ESP32 Schematic for 3.3 V VDD_SDIO Power Supply Pin.
Attention
When using VDD_SDIO as the power supply pin for in-package or off-package 3.3 V flash/PSRAM, the supply voltage should be 3.0 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.
ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin
ESP32 Schematic for 3.3 V VDD_SDIO Power Supply Pin
VDD_SDIO can also be driven by an external power supply as shown in Figure ESP32 Schematic for VDD_SDIO Pin Powered by External Supply.
ESP32 Schematic for VDD_SDIO Pin Powered by External Supply
Analog Power Supply
ESP32’s VDDA and VDD3P3 pins are the analog power supply pins, working at 2.3 V ~ 3.6 V.
For VDD3P3, when ESP32 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 1 μF capacitor(s).
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32 Schematic for Analog Power Supply Pins.
ESP32 Schematic for Analog Power Supply Pins
RTC Power Supply
ESP32’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32 Schematic for RTC Power Supply Pin.
ESP32 Schematic for RTC Power Supply Pin
Chip Power-up and Reset Timing
ESP32’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low.
When ESP32 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused by external interferences, make the CHIP_PU trace as short as possible.
Figure ESP32 Power-up and Reset Timing shows the power-up and reset timing of ESP32.
ESP32 Power-up and Reset Timing
Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements.
Parameter |
Description |
Minimum (µs) |
|---|---|---|
tSTBL |
Time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip |
50 |
tRST |
Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip |
50 |
Attention
CHIP_PU must not be left floating.
To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip.
If the user application has one of the following scenarios:
Slow power rise or fall, such as during battery charging.
Frequent power on/off operations.
Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as:
Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V.
Implementing reset functionality through a button or the main controller.
Flash and PSRAM
ESP32 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off-package RAM is optional.
In-Package Flash and PSRAM
The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM. Please note that the following chip pins can connect at most one flash and one PSRAM. That is to say, when there is only flash in the package, the pin occupied by flash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM, the pin occupied by PSRAM can only connect flash; when there are both flash and PSRAM, the pin occupied cannot connect any more flash or PSRAM.
ESP32-U4WDH |
In-Package Flash (4 MB) |
|---|---|
SD_DATA_1 |
IO0/DI |
GPIO17 |
IO1/DO |
SD_DATA_0 |
IO2/WP# |
SD_CMD |
IO3/HOLD# |
SD_CLK |
CLK |
GPIO16 |
CS# |
GND |
VSS |
VDD_SDIO |
VDD |
ESP32-D0WDR2-V3 |
In-Package PSRAM (2 MB) |
|---|---|
SD_DATA_1 |
SIO0/SI |
SD_DATA_0 |
SIO1/SO |
SD_DATA_3 |
SIO2 |
SD_DATA_2 |
SIO3 |
SD_CLK |
SCLK |
GPIO16 |
CE# |
GND |
VSS |
VDD_SDIO |
VDD |
Off-Package Flash and PSRAM
ESP32 supports up to 16 MB off-package flash and 8 MB off-package RAM. If VDD_SDIO is used to supply power, make sure to select the appropriate off-package flash and RAM according to the power voltage on VDD_SDIO (1.8 V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving current, reduce interference to RF, adjust timing, and better shield from interference.
Clock Source
ESP32 supports two external clock sources:
External Crystal Clock Source (Compulsory)
The ESP32 firmware only supports 40 MHz crystal.
The circuit for the crystal is shown in Figure ESP32 Schematic for External Crystal. Note that the accuracy of the selected crystal should be within ±10 ppm.
ESP32 Schematic for External Crystal
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should be adjusted after an overall test.
The initial values of external capacitors C1 and C2 can be determined according to the formula:
where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below:
Select TX tone mode using the Certification and Test Tool.
Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to obtain the actual frequency offset.
Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance.
When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the external load capacitance needs to be increased.
When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external load capacitance needs to be reduced.
External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different values.
Note
Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable performance within the operating temperature range, etc) may lead to the malfunction of ESP32, resulting in a decrease of the RF performance.
It is recommended that the amplitude of the crystal is greater than 500 mV.
When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps mentioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides of the crystal.
RTC Clock Source (Optional)
ESP32 supports an external 32.768 kHz crystal to act as the RTC clock. The external RTC clock source enhances timing accuracy and consequently decreases average power consumption, without impacting functionality.
Figure ESP32 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.
ESP32 Schematic for 32.768 kHz Crystal
Please note the requirements for the 32.768 kHz crystal:
Equivalent series resistance (ESR) ≤ 70 kΩ.
Load capacitance at both ends should be configured according to the crystal’s specification.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to populate the resistor.
When ESP32-D0WD-V3 connects to an external 32.768 kHz crystal, the parallel resistor must be populated. For other ESP32 series chips, the resistor can be reserved.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
RF
RF Circuit
ESP32’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements:
For the RF traces on the PCB board, 50 Ω impedance control is required.
For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.
The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and a set of LC can be added if space permits.
The RF matching circuit is shown in Figure ESP32 Schematic for RF Matching.
For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.
ESP32 Schematic for RF Matching
RF Tuning
The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly. Follow the instructions below to do RF tuning.
Figure ESP32 RF Tuning Diagram shows the general process of RF tuning.
ESP32 RF Tuning Diagram
The initial value of the parameters in the matching network can be 0 Ω. The recommended value of S11 is 25+j0. The recommended central frequency is 2442 MHz.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD protection devices near the antenna.
Note
If RF function is not required, then the RF pin can be left floating.
UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0, please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX line to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to Hardware Connection). It is recommended to use the default configuration.
SPI
When using the SPI function, to improve EMC performance, add a series resistor (or ferrite bead) and a capacitor to ground on the SPI_CLK trace. If space allows, it is recommended to also add a series resistor and capacitor to ground on other SPI traces. Ensure that the RC/LC components are placed close to the pins of the chip or module.
Strapping Pins
At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal function pins.
All the information about strapping pins is covered in ESP32 Series Datasheet > Section Strapping Pins. In this document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO0 and GPIO2 controls the boot mode. See Table Boot Mode Control.
Boot Mode |
GPIO0 |
GPIO2 |
|---|---|---|
Default Config |
1 |
0 |
SPI Boot |
1 |
Any value |
Joint Download Boot 1 |
0 |
0 |
- 1
Joint Download Boot mode supports the following download methods:
UART Download Boot
SDIO Download Boot
Signals applied to the strapping pins should have specific setup time and hold time. For more information, see Figure Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
Setup and Hold Times for Strapping Pins
Parameter |
Description |
Minimum (ms) |
|---|---|---|
tSU |
Time reserved for the power rails to stabilize before the chip enable pin (CHIP_PU) is pulled high to activate the chip. |
0 |
tH |
Time reserved for the chip to read the strapping pin values after CHIP_PU is already high and before these pins start operating as regular IO pins. |
3 |
Attention
Do not add high-value capacitors at GPIO0, otherwise, the chip may not boot successfully.
GPIO
The pins of ESP32 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configurations, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about IO MUX and GPIO matrix, please refer to ESP32 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available GPIO pins. For details, please refer to ESP32 Series Datasheet > Section Peripheral Pin Configurations.
When using GPIOs, please:
Pay attention to the states of strapping pins during power-up.
Pay attention to the default configurations of the GPIOs after reset. The default configurations can be found in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the high-impedance state or enable the pull-up and pull-down during software initialization to avoid extra power consumption.
Avoid using the pins already occupied by flash/PSRAM.
GPIO |
Pin Name |
Function 0 |
Function 1 |
Function 2 |
Function 3 |
Function 4 |
Function 5 |
Reset |
|---|---|---|---|---|---|---|---|---|
0 |
GPIO0 |
GPIO0 |
CLK_OUT1 |
GPIO0 |
– |
– |
EMAC_TX_CLK |
3 |
1 |
U0TXD |
U0TXD |
CLK_OUT3 |
GPIO1 |
– |
– |
EMAC_RXD2 |
3 |
2 |
GPIO2 |
GPIO2 |
HSPIWP |
GPIO2 |
HS2_DATA0 |
SD_DATA0 |
– |
2 |
3 |
U0RXD |
U0RXD |
CLK_OUT2 |
GPIO3 |
– |
– |
– |
3 |
4 |
GPIO4 |
GPIO4 |
HSPIHD |
GPIO4 |
HS2_DATA1 |
SD_DATA1 |
EMAC_TX_ER |
2 |
5 |
GPIO5 |
GPIO5 |
VSPICS0 |
GPIO5 |
HS1_DATA6 |
– |
EMAC_RX_CLK |
3 |
6 |
SD_CLK |
SD_CLK |
SPICLK |
GPIO6 |
HS1_CLK |
U1CTS |
– |
3 |
7 |
SD_DATA_0 |
SD_DATA0 |
SPIQ |
GPIO7 |
HS1_DATA0 |
U2RTS |
– |
3 |
8 |
SD_DATA_1 |
SD_DATA1 |
SPID |
GPIO8 |
HS1_DATA1 |
U2CTS |
– |
3 |
9 |
SD_DATA_2 |
SD_DATA2 |
SPIHD |
GPIO9 |
HS1_DATA2 |
U1RXD |
– |
3 |
10 |
SD_DATA_3 |
SD_DATA3 |
SPIWP |
GPIO10 |
HS1_DATA3 |
U1TXD |
– |
3 |
11 |
SD_CMD |
SD_CMD |
SPICS0 |
GPIO11 |
HS1_CMD |
U1RTS |
– |
3 |
12 |
MTDI |
MTDI |
HSPIQ |
GPIO12 |
HS2_DATA2 |
SD_DATA2 |
EMAC_TXD3 |
2 |
13 |
MTCK |
MTCK |
HSPID |
GPIO13 |
HS2_DATA3 |
SD_DATA3 |
EMAC_RX_ER |
2 |
14 |
MTMS |
MTMS |
HSPICLK |
GPIO14 |
HS2_CLK |
SD_CLK |
EMAC_TXD2 |
3 |
15 |
MTDO |
MTDO |
HSPICS0 |
GPIO15 |
HS2_CMD |
SD_CMD |
EMAC_RXD3 |
3 |
16 |
GPIO16 |
GPIO16 |
– |
GPIO16 |
HS1_DATA4 |
U2RXD |
EMAC_CLK_OUT |
1 |
17 |
GPIO17 |
GPIO17 |
– |
GPIO17 |
HS1_DATA5 |
U2TXD |
EMAC_CLK_180 |
1 |
18 |
GPIO18 |
GPIO18 |
VSPICLK |
GPIO18 |
HS1_DATA7 |
– |
– |
1 |
19 |
GPIO19 |
GPIO19 |
VSPIQ |
GPIO19 |
U0CTS |
– |
EMAC_TXD0 |
1 |
21 |
GPIO21 |
GPIO21 |
VSPIHD |
GPIO21 |
– |
– |
EMAC_TX_EN |
1 |
22 |
GPIO22 |
GPIO22 |
VSPIWP |
GPIO22 |
U0RTS |
– |
EMAC_TXD1 |
1 |
23 |
GPIO23 |
GPIO23 |
VSPID |
GPIO23 |
HS1_STROBE |
– |
– |
1 |
25 |
GPIO25 |
GPIO25 |
– |
GPIO25 |
– |
– |
EMAC_RXD0 |
0 |
26 |
GPIO26 |
GPIO26 |
– |
GPIO26 |
– |
– |
EMAC_RXD1 |
0 |
27 |
GPIO27 |
GPIO27 |
– |
GPIO27 |
– |
– |
EMAC_RX_DV |
0 |
32 |
32K_XP |
GPIO32 |
– |
GPIO32 |
– |
– |
– |
0 |
33 |
32K_XN |
GPIO33 |
– |
GPIO33 |
– |
– |
– |
0 |
34 |
VDET_1 |
GPIO34 |
– |
GPIO34 |
– |
– |
– |
0 |
35 |
VDET_2 |
GPIO35 |
– |
GPIO35 |
– |
– |
– |
0 |
36 |
SENSOR_VP |
GPIO36 |
– |
GPIO36 |
– |
– |
– |
0 |
37 |
SENSOR_CAPP |
GPIO37 |
– |
GPIO37 |
– |
– |
– |
0 |
38 |
SENSOR_CAPN |
GPIO38 |
– |
GPIO38 |
– |
– |
– |
0 |
39 |
SENSOR_VN |
GPIO39 |
– |
GPIO39 |
– |
– |
– |
0 |
Reset:
0: IE=0 (input disabled)
1: IE=1 (input enabled)
2: IE=1, WPD=1 (input enabled, pull-down resistor)
3: IE=1, WPU=1 (input enabled, pull-up resistor)
ADC
Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
When RTC peripherals (SAR ADC1/SAR ADC2/AMP) is powered on, the inputs of GPIO36 (SENSOR_VP) and GPIO39 (SENSOR_VN) will be pulled down for approximately 80 ns. Therefore, it is recommended to use SENSOR_VP and SENSOR_VN as ADC pins.
If SENSOR_VP and SENSOR_VN are used as GPIOs in the design, while ADC is supported by other pins, then software should disregard the glitch. Optionally, make SENSOR_VP and SENSOR_VN active high pins.
ADC1 is recommended over ADC2 as the latter cannot be used when Wi-Fi function is enabled.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher accuracy, you may implement your own calibration methods.
When ATTEN=0 and the effective measurement range is 100 ~ 950 mV, the total error is ±23 mV.
When ATTEN=1 and the effective measurement range is 100 ~ 1250 mV, the total error is ±30 mV.
When ATTEN=2 and the effective measurement range is 150 ~ 1750 mV, the total error is ±40 mV.
When ATTEN=3 and the effective measurement range is 150 ~ 2450 mV, the total error is ±60 mV.
External Capacitor
Figure ESP32 Schematic for External Capacitor shows the schematic of components connected to pin47 CAP2 and pin48 CAP1.
C5 (10 nF) that connects to CAP1 should be of 10% tolerance and is required for proper operation of ESP32.
RC circuit between CAP1 and CAP2 pins may be omitted under certain conditions. This circuit is used when entering Deep-sleep mode. During this process, to minimize power consumption, the voltage to power ESP32 internals is dropped from 1.1 V to around 0.7 V. The RC circuit is used to minimize the period of the voltage drop. If removed, this process will take longer and the power consumption in Deep-sleep will be higher. If particular application of ESP32 is not using Deep-sleep mode, or power consumption is less critical, then this circuit is not required.
ESP32 Schematic for External Capacitor
SDIO
There are two sets of GPIOs (slot0 and slot1) that can be assigned to SDIO on ESP32, as shown in Table SDIO Pin Configuration. When ESP32 works as an SDIO host or slave, connect GPIOs in slot1 to signal lines.
CMD |
CLK |
DAT0 |
DAT1 |
DAT2 |
DAT3 |
Note |
|
|---|---|---|---|---|---|---|---|
Slot0 |
GPIO11 |
GPIO6 |
GPIO7 |
GPIO8 |
GPIO9 |
GPIO10 |
Used to connect flash by default. Not recommended for other use. |
Slot1 |
GPIO15 |
GPIO14 |
GPIO2 |
GPIO4 |
GPIO12 |
GPIO13 |
Multiplexed with JTAG, touch, EMAC, and strapping functions. |
When connecting GPIOs in slot1 to signal lines, please note:
When ESP32 works as an SDIO host, it is recommended to add pull-up resistors on the used pins. Unused pins can be utilized for other purposes.
When ESP32 works as an SDIO slave, add pull-up resistors on all pins, regardless of whether these pins are used for SDIO or not. Unused pins cannot be used for other purposes.
For more information on SDIO configuration, please refer to API References.
Touch Sensor
When using the touch function, it is recommended to populate a zero-ohm series resistor at the chip side to reduce the coupling noise and interference on the line, and to strengthen the ESD protection. The recommended resistance is from 470 Ω to 2 kΩ, preferably 510 Ω. The specific value depends on the actual test results of the product.
Ethernet MAC
ESP32 provides a media access control (MAC) interface that complies with the IEEE-802.3-2008 standard for Ethernet communication. The ESP32-Ethernet-Kit board only supports the Reduced Media-Independent Interface (RMII). The allocation of the ESP32 pins to the RMII interface is shown in the table below.
Pin Name |
Function 6 |
RMII (int_osc) |
RMII (ext_osc) |
|---|---|---|---|
GPIO0 |
EMAC_TX_CLK |
CLK_OUT(O) |
EXT_OSC_CLK(I) |
GPIO21 |
EMAC_TX_EN |
TX_EN(O) |
TX_EN(O) |
GPIO19 |
EMAC_TXD0 |
TXD[0](O) |
TXD[0](O) |
GPIO22 |
EMAC_TXD1 |
TXD[1](O) |
TXD[1](O) |
GPIO27 |
EMAC_RX_DV |
CRS_DV(I) |
CRS_DV(I) |
GPIO25 |
EMAC_RXD0 |
RXD[0](I) |
RXD[0](I) |
GPIO26 |
EMAC_RXD1 |
RXD[1](I) |
RXD[1](I) |
GPIO16 |
EMAC_CLK_OUT |
CLK_OUT(O) |
– |
GPIO17 |
EMAC_CLK_OUT_180 |
CLK_OUT_180(O) |
– |
Any GPIO |
– |
MDC(O) |
MDC(O) |
Any GPIO |
– |
MDIO(IO) |
MDIO(IO) |
For an Ethernet solution, it is recommended to use GPIO0 as the clock input. Be aware that GPIO0 also acts as a strapping pin and it can be affected by the clock during chip power-up and may enter download mode as a result. Therefore, make sure you have turned off the clock output on the PHY side before powering up the chip. The ESP32-Ethernet-Kit board uses GPIO to control PHY’s reset pin and turn off the clock output. However, not all PHYs support this design, so it is crucial to verify functionality during testing. If this design cannot be implemented, consider alternative methods to ensure that GPIO0 remains unaffected during power-up. For a reference design please see ESP32-Ethernet-Kit User Guide.
If you need to use Wi-Fi and Ethernet simultaneously, do not use the internal APLL clock to generate the RMII clock, as this can lead to clock instability. Instead, use the RMII clock from the PHY side or an external clock source. For further details, please refer to ESP32-Ethernet-Kit User Guide > RMII Clock Selection.