SoC Capabilities
This section lists the macro definitions of the ESP32-C5's SoC hardware capabilities. These macros are commonly used by conditional-compilation directives (e.g., #if
) in ESP-IDF to determine which hardware-dependent features are supported, thus control what portions of code are compiled.
Warning
These macro definitions are currently not considered to be part of the public API, and may be changed in a breaking manner (see ESP-IDF Versions for more details).
API Reference
Header File
This header file can be included with:
#include "soc/soc_caps.h"
Macros
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SOC_UART_SUPPORTED
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SOC_GDMA_SUPPORTED
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SOC_AHB_GDMA_SUPPORTED
-
SOC_GPTIMER_SUPPORTED
-
SOC_ASYNC_MEMCPY_SUPPORTED
-
SOC_SUPPORTS_SECURE_DL_MODE
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SOC_EFUSE_KEY_PURPOSE_FIELD
-
SOC_EFUSE_SUPPORTED
-
SOC_RTC_FAST_MEM_SUPPORTED
-
SOC_RTC_MEM_SUPPORTED
-
SOC_SYSTIMER_SUPPORTED
-
SOC_FLASH_ENC_SUPPORTED
-
SOC_LP_PERIPHERALS_SUPPORTED
-
SOC_SPI_FLASH_SUPPORTED
-
SOC_XTAL_SUPPORT_40M
-
SOC_XTAL_SUPPORT_48M
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SOC_ADC_PERIPH_NUM
< SAR ADC Module
-
SOC_ADC_MAX_CHANNEL_NUM
-
SOC_SHARED_IDCACHE_SUPPORTED
< Digital
< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095
< RTC
< Calibration
< Interrupt
< ADC power control is shared by PWDET
-
SOC_CACHE_FREEZE_SUPPORTED
-
SOC_CPU_CORES_NUM
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SOC_CPU_INTR_NUM
-
SOC_CPU_HAS_FLEXIBLE_INTC
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SOC_INT_CLIC_SUPPORTED
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SOC_INT_HW_NESTED_SUPPORTED
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SOC_BRANCH_PREDICTOR_SUPPORTED
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SOC_CPU_BREAKPOINTS_NUM
-
SOC_CPU_WATCHPOINTS_NUM
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SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
-
SOC_CPU_HAS_PMA
-
SOC_CPU_IDRAM_SPLIT_USING_PMP
-
SOC_DMA_CAN_ACCESS_FLASH
The maximum length of a Digital Signature in bits. Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details DMA can access Flash memory
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SOC_AHB_GDMA_VERSION
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SOC_GDMA_NUM_GROUPS_MAX
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SOC_GDMA_PAIRS_PER_GROUP_MAX
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SOC_GPIO_PORT
-
SOC_GPIO_PIN_COUNT
-
SOC_GPIO_SUPPORT_PIN_HYS_FILTER
-
SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-
SOC_GPIO_VALID_GPIO_MASK
-
SOC_GPIO_VALID_OUTPUT_GPIO_MASK
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SOC_GPIO_IN_RANGE_MAX
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SOC_GPIO_OUT_RANGE_MAX
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SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
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SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
-
SOC_GPIO_SUPPORT_FORCE_HOLD
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SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
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SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
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SOC_GPIO_CLOCKOUT_CHANNEL_NUM
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SOC_RTCIO_PIN_COUNT
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SOC_I2C_NUM
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SOC_HP_I2C_NUM
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SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
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SOC_LEDC_SUPPORT_XTAL_CLOCK
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SOC_LEDC_CHANNEL_NUM
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SOC_MMU_PERIPH_NUM
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SOC_MMU_LINEAR_ADDRESS_REGION_NUM
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SOC_MMU_DI_VADDR_SHARED
D/I vaddr are shared
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SOC_RMT_GROUPS
One RMT group
-
SOC_RMT_TX_CANDIDATES_PER_GROUP
Number of channels that capable of Transmit
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SOC_RMT_RX_CANDIDATES_PER_GROUP
Number of channels that capable of Receive
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SOC_RMT_CHANNELS_PER_GROUP
Total 4 channels
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SOC_RMT_MEM_WORDS_PER_CHANNEL
Each channel owns 48 words memory (1 word = 4 Bytes)
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SOC_RMT_SUPPORT_RX_PINGPONG
Support Ping-Pong mode on RX path
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SOC_RMT_SUPPORT_RX_DEMODULATION
Support signal demodulation on RX path (i.e. remove carrier)
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SOC_RMT_SUPPORT_TX_ASYNC_STOP
Support stop transmission asynchronously
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SOC_RMT_SUPPORT_TX_LOOP_COUNT
Support transmit specified number of cycles in loop mode
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SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
Hardware support of auto-stop in loop mode
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SOC_RMT_SUPPORT_TX_SYNCHRO
Support coordinate a group of TX channels to start simultaneously
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SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
TX carrier can be modulated to data phase only
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SOC_RMT_SUPPORT_XTAL
Support set XTAL clock as the RMT clock source
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SOC_RSA_MAX_BIT_LEN
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SOC_SPI_PERIPH_NUM
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SOC_SPI_PERIPH_CS_NUM(i)
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SOC_SPI_MAX_CS_NUM
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SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
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SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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SOC_SYSTIMER_COUNTER_NUM
-
SOC_SYSTIMER_ALARM_NUM
-
SOC_SYSTIMER_BIT_WIDTH_LO
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SOC_SYSTIMER_BIT_WIDTH_HI
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SOC_SYSTIMER_FIXED_DIVIDER
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SOC_SYSTIMER_SUPPORT_RC_FAST
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SOC_SYSTIMER_INT_LEVEL
-
SOC_SYSTIMER_ALARM_MISS_COMPENSATE
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SOC_TIMER_GROUPS
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SOC_TIMER_GROUP_TIMERS_PER_GROUP
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SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
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SOC_TIMER_GROUP_SUPPORT_XTAL
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SOC_TIMER_GROUP_TOTAL_TIMERS
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SOC_EFUSE_ECDSA_KEY
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SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
-
SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
-
SOC_FLASH_ENCRYPTION_XTS_AES
-
SOC_FLASH_ENCRYPTION_XTS_AES_128
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SOC_UART_NUM
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SOC_UART_HP_NUM
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SOC_UART_LP_NUM
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SOC_UART_FIFO_LEN
The UART hardware FIFO length
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SOC_LP_UART_FIFO_LEN
The LP UART hardware FIFO length
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SOC_UART_BITRATE_MAX
Max bit rate supported by UART
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SOC_UART_SUPPORT_XTAL_CLK
Support XTAL clock as the clock source
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SOC_UART_SUPPORT_WAKEUP_INT
Support UART wakeup interrupt
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SOC_UART_HAS_LP_UART
Support LP UART
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SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
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SOC_PM_SUPPORT_MODEM_PD
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SOC_PM_SUPPORT_XTAL32K_PD
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SOC_PM_SUPPORT_RC32K_PD
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SOC_PM_SUPPORT_RC_FAST_PD
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SOC_PM_SUPPORT_VDDSDIO_PD
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SOC_PM_SUPPORT_TOP_PD
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SOC_PM_SUPPORT_HP_AON_PD
-
SOC_PM_SUPPORT_RTC_PERIPH_PD
-
SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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SOC_MODEM_CLOCK_IS_INDEPENDENT
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SOC_CLK_XTAL32K_SUPPORTED
Support to connect an external low frequency crystal
-
SOC_CLK_OSC_SLOW_SUPPORTED
Support to connect an external oscillator, not a crystal
-
SOC_CLK_RC32K_SUPPORTED
Support an internal 32kHz RC oscillator
-
SOC_RCC_IS_INDEPENDENT
Reset and Clock Control is independent, thanks to the PCR registers