SoC Capabilities

[中文]

This section lists the macro definitions of the ESP32-C5's SoC hardware capabilities. These macros are commonly used by conditional-compilation directives (e.g., #if) in ESP-IDF to determine which hardware-dependent features are supported, thus control what portions of code are compiled.

Warning

These macro definitions are currently not considered to be part of the public API, and may be changed in a breaking manner (see ESP-IDF Versions for more details).

API Reference

Header File

Macros

SOC_UART_SUPPORTED
SOC_GDMA_SUPPORTED
SOC_AHB_GDMA_SUPPORTED
SOC_GPTIMER_SUPPORTED
SOC_ASYNC_MEMCPY_SUPPORTED
SOC_SUPPORTS_SECURE_DL_MODE
SOC_EFUSE_KEY_PURPOSE_FIELD
SOC_EFUSE_SUPPORTED
SOC_RTC_FAST_MEM_SUPPORTED
SOC_RTC_MEM_SUPPORTED
SOC_SYSTIMER_SUPPORTED
SOC_FLASH_ENC_SUPPORTED
SOC_LP_PERIPHERALS_SUPPORTED
SOC_SPI_FLASH_SUPPORTED
SOC_XTAL_SUPPORT_40M
SOC_XTAL_SUPPORT_48M
SOC_ADC_PERIPH_NUM

< SAR ADC Module

SOC_ADC_MAX_CHANNEL_NUM
SOC_SHARED_IDCACHE_SUPPORTED

< Digital

< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095

< RTC

< Calibration

< Interrupt

< ADC power control is shared by PWDET

SOC_CACHE_FREEZE_SUPPORTED
SOC_CPU_CORES_NUM
SOC_CPU_INTR_NUM
SOC_CPU_HAS_FLEXIBLE_INTC
SOC_INT_CLIC_SUPPORTED
SOC_INT_HW_NESTED_SUPPORTED
SOC_BRANCH_PREDICTOR_SUPPORTED
SOC_CPU_BREAKPOINTS_NUM
SOC_CPU_WATCHPOINTS_NUM
SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
SOC_CPU_HAS_PMA
SOC_CPU_IDRAM_SPLIT_USING_PMP
SOC_DMA_CAN_ACCESS_FLASH

The maximum length of a Digital Signature in bits. Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details DMA can access Flash memory

SOC_AHB_GDMA_VERSION
SOC_GDMA_NUM_GROUPS_MAX
SOC_GDMA_PAIRS_PER_GROUP_MAX
SOC_GPIO_PORT
SOC_GPIO_PIN_COUNT
SOC_GPIO_SUPPORT_PIN_HYS_FILTER
SOC_GPIO_SUPPORT_RTC_INDEPENDENT
SOC_GPIO_VALID_GPIO_MASK
SOC_GPIO_VALID_OUTPUT_GPIO_MASK
SOC_GPIO_IN_RANGE_MAX
SOC_GPIO_OUT_RANGE_MAX
SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
SOC_GPIO_SUPPORT_FORCE_HOLD
SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
SOC_GPIO_CLOCKOUT_CHANNEL_NUM
SOC_RTCIO_PIN_COUNT
SOC_I2C_NUM
SOC_HP_I2C_NUM
SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
SOC_LEDC_SUPPORT_XTAL_CLOCK
SOC_LEDC_CHANNEL_NUM
SOC_MMU_PERIPH_NUM
SOC_MMU_LINEAR_ADDRESS_REGION_NUM
SOC_MMU_DI_VADDR_SHARED

D/I vaddr are shared

SOC_RMT_GROUPS

One RMT group

SOC_RMT_TX_CANDIDATES_PER_GROUP

Number of channels that capable of Transmit

SOC_RMT_RX_CANDIDATES_PER_GROUP

Number of channels that capable of Receive

SOC_RMT_CHANNELS_PER_GROUP

Total 4 channels

SOC_RMT_MEM_WORDS_PER_CHANNEL

Each channel owns 48 words memory (1 word = 4 Bytes)

SOC_RMT_SUPPORT_RX_PINGPONG

Support Ping-Pong mode on RX path

SOC_RMT_SUPPORT_RX_DEMODULATION

Support signal demodulation on RX path (i.e. remove carrier)

SOC_RMT_SUPPORT_TX_ASYNC_STOP

Support stop transmission asynchronously

SOC_RMT_SUPPORT_TX_LOOP_COUNT

Support transmit specified number of cycles in loop mode

SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP

Hardware support of auto-stop in loop mode

SOC_RMT_SUPPORT_TX_SYNCHRO

Support coordinate a group of TX channels to start simultaneously

SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY

TX carrier can be modulated to data phase only

SOC_RMT_SUPPORT_XTAL

Support set XTAL clock as the RMT clock source

SOC_RSA_MAX_BIT_LEN
SOC_SPI_PERIPH_NUM
SOC_SPI_PERIPH_CS_NUM(i)
SOC_SPI_MAX_CS_NUM
SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
SOC_SYSTIMER_COUNTER_NUM
SOC_SYSTIMER_ALARM_NUM
SOC_SYSTIMER_BIT_WIDTH_LO
SOC_SYSTIMER_BIT_WIDTH_HI
SOC_SYSTIMER_FIXED_DIVIDER
SOC_SYSTIMER_SUPPORT_RC_FAST
SOC_SYSTIMER_INT_LEVEL
SOC_SYSTIMER_ALARM_MISS_COMPENSATE
SOC_TIMER_GROUPS
SOC_TIMER_GROUP_TIMERS_PER_GROUP
SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
SOC_TIMER_GROUP_SUPPORT_XTAL
SOC_TIMER_GROUP_TOTAL_TIMERS
SOC_EFUSE_ECDSA_KEY
SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
SOC_FLASH_ENCRYPTION_XTS_AES
SOC_FLASH_ENCRYPTION_XTS_AES_128
SOC_UART_NUM
SOC_UART_HP_NUM
SOC_UART_LP_NUM
SOC_UART_FIFO_LEN

The UART hardware FIFO length

SOC_LP_UART_FIFO_LEN

The LP UART hardware FIFO length

SOC_UART_BITRATE_MAX

Max bit rate supported by UART

SOC_UART_SUPPORT_XTAL_CLK

Support XTAL clock as the clock source

SOC_UART_SUPPORT_WAKEUP_INT

Support UART wakeup interrupt

SOC_UART_HAS_LP_UART

Support LP UART

SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
SOC_PM_SUPPORT_MODEM_PD
SOC_PM_SUPPORT_XTAL32K_PD
SOC_PM_SUPPORT_RC32K_PD
SOC_PM_SUPPORT_RC_FAST_PD
SOC_PM_SUPPORT_VDDSDIO_PD
SOC_PM_SUPPORT_TOP_PD
SOC_PM_SUPPORT_HP_AON_PD
SOC_PM_SUPPORT_RTC_PERIPH_PD
SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
SOC_MODEM_CLOCK_IS_INDEPENDENT
SOC_CLK_XTAL32K_SUPPORTED

Support to connect an external low frequency crystal

SOC_CLK_OSC_SLOW_SUPPORTED

Support to connect an external oscillator, not a crystal

SOC_CLK_RC32K_SUPPORTED

Support an internal 32kHz RC oscillator

SOC_RCC_IS_INDEPENDENT

Reset and Clock Control is independent, thanks to the PCR registers