时钟树

[English]

ESP32-P4 的时钟子系统用于从一系列根时钟中提取并分配系统/模块时钟。时钟树驱动程序负责维护系统时钟的基本功能，并管理模块时钟间的复杂关系。

本文档首先介绍了根时钟和模块时钟，随后介绍了可供用户调用的时钟树 API，调用这些 API，可以监测模块时钟的运行状态。

简介

本节列出了 ESP32-P4 支持的根时钟和模块时钟的定义，这些定义通常用于驱动程序配置，有助于为外设选择合适的时钟源。

根时钟

根时钟会产生可靠的时钟信号，经各种门、复用器、分频器或倍频器传递，这些时钟信号最终成为 CPU 内核、Wi-Fi、蓝牙、RTC 及外设等功能模块的时钟源。

ESP32-P4 的根时钟列在 soc_root_clk_t 中：

• 内部 8 MHz RC 振荡器 (RC_FAST)

  此 RC 振荡器可产生约 8.5 MHz 的时钟信号输出，标识为 RC_FAST_CLK。

  在运行时，无法通过校准计算 RC_FAST_CLK 的实际频率，但仍可以将时钟信号引出到 GPIO 管脚，通过示波器或逻辑分析仪获取频率。

• 外部 40 MHz 晶振 (XTAL)

• 内部 136 kHz RC 振荡器 (RC_SLOW)

  此 RC 振荡器产生约 136 kHz 的时钟信号输出，标识为 RC_SLOW_CLK。在运行时，通过校准，可以计算该时钟信号的实际频率。

• 外部 32 kHz 晶振 - 可选 (XTAL32K)

  XTAL32K_CLK 的时钟源可以是连接到 XTAL_32K_P 和 XTAL_32K_N 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHZ 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 XTAL_32K_P 管脚。

  通过校准，可以计算 XTAL32K_CLK 的实际频率。

• 外部慢速时钟 - 可选 (OSC_SLOW)

  将外部电路生成的时钟信号连接到 GPIO0，可作为 RTC_SLOW_CLK 的时钟源。通过校准，可以计算该时钟信号的实际频率。

与晶振产生的信号相比，从 RC 振荡器电路产生的信号通常精度较低，且容易受环境影响。因此，ESP32-P4 为 RTC_SLOW_CLK 提供了几种时钟源选项，可以根据对系统时间精度和对功耗的要求选择。更多详情，请参阅 RTC 定时器时钟源。

模块时钟

ESP32-P4 的可用模块时钟在 soc_module_clk_t 中列出，每个模块时钟都有其唯一 ID。查阅文档中的枚举值，即可获取各模块时钟的详细信息。

使用 API

时钟树驱动程序提供了一个一体化接口，可以获取模块时钟的频率，即 esp_clk_tree_src_get_freq_hz()。通过该函数，你可以在任何时刻，通过提供时钟名称 soc_module_clk_t 和指定返回频率值的精度级别 esp_clk_tree_src_freq_precision_t，获取时钟频率。

API 参考

Header File

• components/soc/esp32p4/include/soc/clk_tree_defs.h

• This header file can be included with:

  #include "soc/clk_tree_defs.h"
  

Macros

SOC_CLK_RC_FAST_FREQ_APPROX

Approximate RC_FAST_CLK frequency in Hz

SOC_CLK_RC_SLOW_FREQ_APPROX

Approximate RC_SLOW_CLK frequency in Hz

SOC_CLK_RC32K_FREQ_APPROX

Approximate RC32K_CLK frequency in Hz

SOC_CLK_XTAL32K_FREQ_APPROX

Approximate XTAL32K_CLK frequency in Hz

SOC_CLK_OSC_SLOW_FREQ_APPROX

Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz

SOC_GPTIMER_CLKS

Array initializer for all supported clock sources of GPTimer.

The following code can be used to iterate all possible clocks:

soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
    soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
    // Test GPTimer with the clock `clk`
}

SOC_RMT_CLKS

Array initializer for all supported clock sources of RMT.

SOC_UART_CLKS

Array initializer for all supported clock sources of UART.

SOC_LP_UART_CLKS

Array initializer for all supported clock sources of LP_UART.

SOC_MCPWM_TIMER_CLKS

Array initializer for all supported clock sources of MCPWM Timer.

SOC_MCPWM_CAPTURE_CLKS

Array initializer for all supported clock sources of MCPWM Capture Timer.

SOC_MCPWM_CARRIER_CLKS

Array initializer for all supported clock sources of MCPWM Carrier.

SOC_I2S_CLKS

Array initializer for all supported clock sources of I2S.

SOC_I2C_CLKS

Array initializer for all supported clock sources of I2C.

SOC_SPI_CLKS

Array initializer for all supported clock sources of SPI.

SOC_PSRAM_CLKS

Array initializer for all supported clock sources of PSRAM.

SOC_FLASH_CLKS

Array initializer for all supported clock sources of FLASH.

SOC_ANA_CMPR_CLKS

Array initializer for all supported clock sources of Analog Comparator.

SOC_MWDT_CLKS

Array initializer for all supported clock sources of MWDT.

SOC_LEDC_CLKS

Array initializer for all supported clock sources of LEDC.

SOC_PARLIO_CLKS

Array initializer for all supported clock sources of PARLIO.

SOC_SDMMC_CLKS

Array initializer for all supported clock sources of SDMMC.

Enumerations

enum soc_root_clk_t

Root clock.

Values:

enumerator SOC_ROOT_CLK_INT_RC_FAST

Internal 17.5MHz RC oscillator

enumerator SOC_ROOT_CLK_INT_RC_SLOW

Internal 136kHz RC oscillator

enumerator SOC_ROOT_CLK_EXT_XTAL

External 40MHz crystal

enumerator SOC_ROOT_CLK_EXT_XTAL32K

External 32kHz crystal

enumerator SOC_ROOT_CLK_INT_RC32K

Internal 32kHz RC oscillator

enumerator SOC_ROOT_CLK_EXT_OSC_SLOW

External slow clock signal at pin1

enum soc_cpu_clk_src_t

CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK.

备注

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_CPU_CLK_SRC_XTAL

Select XTAL_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_PLL

Select (C)PLL_CLK as CPU_CLK source (CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 400MHz)

enumerator SOC_CPU_CLK_SRC_RC_FAST

Select RC_FAST_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_INVALID

Invalid CPU_CLK source

enum soc_rtc_slow_clk_src_t

RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK.

备注

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW

Select RC_SLOW_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_XTAL32K

Select XTAL32K_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_RC32K

Select RC32K_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_OSC_SLOW

Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_INVALID

Invalid RTC_SLOW_CLK source

enum soc_rtc_fast_clk_src_t

RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK.

备注

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_FAST_CLK_SRC_RC_FAST

Select RC_FAST_CLK as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_XTAL

Select XTAL_CLK as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_XTAL_DIV

Alias name for SOC_RTC_FAST_CLK_SRC_XTAL

enumerator SOC_RTC_FAST_CLK_SRC_LP_PLL

Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)

enumerator SOC_RTC_FAST_CLK_SRC_INVALID

Invalid RTC_FAST_CLK source

enum soc_lp_pll_clk_src_t

LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK.

备注

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_LP_PLL_CLK_SRC_RC32K

Select RC32K_CLK as LP_PLL_CLK source

enumerator SOC_LP_PLL_CLK_SRC_XTAL32K

Select XTAL32K_CLK as LP_PLL_CLK source

enumerator SOC_LP_PLL_CLK_SRC_INVALID

Invalid LP_PLL_CLK source

enum soc_module_clk_t

Supported clock sources for modules (CPU, peripherals, RTC, etc.)

备注

enum starts from 1, to save 0 for special purpose

Values:

enumerator SOC_MOD_CLK_CPU

CPU_CLK can be sourced from XTAL, CPLL, or RC_FAST by configuring soc_cpu_clk_src_t

enumerator SOC_MOD_CLK_RTC_FAST

RTC_FAST_CLK can be sourced from XTAL, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t

enumerator SOC_MOD_CLK_RTC_SLOW

RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t

enumerator SOC_MOD_CLK_PLL_F80M

PLL_F80M_CLK is derived from SPLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz

enumerator SOC_MOD_CLK_PLL_F160M

PLL_F160M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz

enumerator SOC_MOD_CLK_PLL_F200M

PLL_F200M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 200MHz

enumerator SOC_MOD_CLK_PLL_F240M

PLL_F240M_CLK is derived from SPLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz

enumerator SOC_MOD_CLK_CPLL

CPLL is from 40MHz XTAL oscillator frequency multipliers, it has a fixed frequency of 400MHz

enumerator SOC_MOD_CLK_SPLL

SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a fixed frequency of 480MHz

enumerator SOC_MOD_CLK_MPLL

MPLL is from 40MHz XTAL oscillator frequency multipliers, it has a fixed frequency of 500MHz

enumerator SOC_MOD_CLK_XTAL32K

XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_RC_FAST

RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_XTAL

XTAL_CLK comes from the external 40MHz crystal

enumerator SOC_MOD_CLK_APLL

Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers

enumerator SOC_MOD_CLK_XTAL_D2

XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals

enumerator SOC_MOD_CLK_LP_PLL

LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz

enumerator SOC_MOD_CLK_INVALID

Indication of the end of the available module clock sources

enum soc_periph_systimer_clk_src_t

Type of SYSTIMER clock source.

Values:

enumerator SYSTIMER_CLK_SRC_XTAL

SYSTIMER source clock is XTAL

enumerator SYSTIMER_CLK_SRC_RC_FAST

SYSTIMER source clock is RC_FAST

enumerator SYSTIMER_CLK_SRC_DEFAULT

SYSTIMER source clock default choice is XTAL

enum soc_periph_gptimer_clk_src_t

Type of GPTimer clock source.

Values:

enumerator GPTIMER_CLK_SRC_PLL_F80M

Select PLL_F80M as the source clock

enumerator GPTIMER_CLK_SRC_RC_FAST

Select RC_FAST as the source clock

enumerator GPTIMER_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator GPTIMER_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_tg_clk_src_legacy_t

Type of Timer Group clock source, reserved for the legacy timer group driver.

Values:

enumerator TIMER_SRC_CLK_PLL_F80M

Timer group clock source is PLL_F80M

enumerator TIMER_SRC_CLK_XTAL

Timer group clock source is XTAL

enumerator TIMER_SRC_CLK_DEFAULT

Timer group clock source default choice is XTAL

enum soc_periph_rmt_clk_src_t

Type of RMT clock source.

Values:

enumerator RMT_CLK_SRC_PLL_F80M

Select PLL_F80M as the source clock

enumerator RMT_CLK_SRC_RC_FAST

Select RC_FAST as the source clock

enumerator RMT_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator RMT_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_rmt_clk_src_legacy_t

Type of RMT clock source, reserved for the legacy RMT driver.

Values:

enumerator RMT_BASECLK_PLL_F80M

RMT source clock is PLL_F80M

enumerator RMT_BASECLK_XTAL

RMT source clock is XTAL

enumerator RMT_BASECLK_DEFAULT

RMT source clock default choice is XTAL

enum soc_periph_uart_clk_src_legacy_t

Type of UART clock source, reserved for the legacy UART driver.

Values:

enumerator UART_SCLK_PLL_F80M

UART source clock is PLL_F80M

enumerator UART_SCLK_RTC

UART source clock is RC_FAST

enumerator UART_SCLK_XTAL

UART source clock is XTAL

enumerator UART_SCLK_DEFAULT

UART source clock default choice is PLL_F80M

enum soc_periph_lp_uart_clk_src_t

Type of LP_UART clock source.

Values:

enumerator LP_UART_SCLK_LP_FAST

LP_UART source clock is LP(RTC)_FAST

enumerator LP_UART_SCLK_XTAL_D2

LP_UART source clock is XTAL_D2

enumerator LP_UART_SCLK_DEFAULT

LP_UART source clock default choice is LP(RTC)_FAST

enum soc_periph_mcpwm_timer_clk_src_t

Type of MCPWM timer clock source.

Values:

enumerator MCPWM_TIMER_CLK_SRC_PLL160M

Select PLL_F160M as the source clock

enumerator MCPWM_TIMER_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator MCPWM_TIMER_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_mcpwm_capture_clk_src_t

Type of MCPWM capture clock source.

Values:

enumerator MCPWM_CAPTURE_CLK_SRC_PLL160M

Select PLL_F160M as the source clock

enumerator MCPWM_CAPTURE_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator MCPWM_CAPTURE_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_mcpwm_carrier_clk_src_t

Type of MCPWM carrier clock source.

Values:

enumerator MCPWM_CARRIER_CLK_SRC_PLL160M

Select PLL_F160M as the source clock

enumerator MCPWM_CARRIER_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator MCPWM_CARRIER_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_i2s_clk_src_t

I2S clock source enum.

Values:

enumerator I2S_CLK_SRC_DEFAULT

Select XTAL as the default source clock

enumerator I2S_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator I2S_CLK_SRC_APLL

Select APLL as the source clock

enumerator I2S_CLK_SRC_EXTERNAL

Select external clock as source clock

enum soc_periph_i2c_clk_src_t

Type of I2C clock source.

Values:

enumerator I2C_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator I2C_CLK_SRC_RC_FAST

Select RC_FAST as the source clock

enumerator I2C_CLK_SRC_DEFAULT

Select XTAL as the default source clock

enum soc_periph_spi_clk_src_t

Type of SPI clock source.

Values:

enumerator SPI_CLK_SRC_XTAL

Select XTAL as SPI source clock

enumerator SPI_CLK_SRC_DEFAULT

Select XTAL as SPI source clock

enum soc_periph_psram_clk_src_t

Type of PSRAM clock source.

Values:

enumerator PSRAM_CLK_SRC_DEFAULT

Select SOC_MOD_CLK_SPLL as PSRAM source clock

enumerator PSRAM_CLK_SRC_XTAL

Select SOC_MOD_CLK_XTAL as PSRAM source clock

enumerator PSRAM_CLK_SRC_CPLL

Select SOC_MOD_CLK_CPLL as PSRAM source clock

enumerator PSRAM_CLK_SRC_SPLL

Select SOC_MOD_CLK_SPLL as PSRAM source clock

enumerator PSRAM_CLK_SRC_MPLL

Select SOC_MOD_CLK_MPLL as PSRAM source clock

enum soc_periph_flash_clk_src_t

Type of FLASH clock source.

Values:

enumerator FLASH_CLK_SRC_DEFAULT

Select SOC_MOD_CLK_SPLL as FLASH source clock

enumerator FLASH_CLK_SRC_XTAL

Select SOC_MOD_CLK_XTAL as FLASH source clock

enumerator FLASH_CLK_SRC_CPLL

Select SOC_MOD_CLK_CPLL as FLASH source clock

enumerator FLASH_CLK_SRC_SPLL

Select SOC_MOD_CLK_SPLL as FLASH source clock

enum soc_periph_ana_cmpr_clk_src_t

Analog Comparator clock source.

Values:

enumerator ANA_CMPR_CLK_SRC_XTAL

Select XTAL clock as the source clock

enumerator ANA_CMPR_CLK_SRC_PLL_F80M

Select PLL_F80M clock as the source clock

enumerator ANA_CMPR_CLK_SRC_DEFAULT

Select PLL_F80M as the default clock choice

enum soc_periph_mwdt_clk_src_t

MWDT clock source.

Values:

enumerator MWDT_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator MWDT_CLK_SRC_PLL_F80M

Select PLL fixed 80 MHz as the source clock

enumerator MWDT_CLK_SRC_RC_FAST

Select RTC fast as the source clock

enumerator MWDT_CLK_SRC_DEFAULT

Select XTAL 40 MHz as the default clock choice

enum soc_periph_ledc_clk_src_legacy_t

Type of LEDC clock source, reserved for the legacy LEDC driver.

Values:

enumerator LEDC_AUTO_CLK

LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer

enumerator LEDC_USE_XTAL_CLK

Select XTAL as the source clock

enumerator LEDC_USE_PLL_DIV_CLK

Select PLL_F80M clock as the source clock

enumerator LEDC_USE_RC_FAST_CLK

Select RC_FAST as the source clock

enum soc_periph_parlio_clk_src_t

PARLIO clock source.

Values:

enumerator PARLIO_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator PARLIO_CLK_SRC_PLL_F160M

Select PLL_F160M as the source clock

enumerator PARLIO_CLK_SRC_RC_FAST

Select RC_FAST as the source clock

enumerator PARLIO_CLK_SRC_EXTERNAL

Select EXTERNAL clock as the source clock

enumerator PARLIO_CLK_SRC_DEFAULT

Select XTAL as the default clock choice

enum soc_periph_sdmmc_clk_src_t

Type of SDMMC clock source.

Values:

enumerator SDMMC_CLK_SRC_DEFAULT

Select PLL_160M as the default choice

enumerator SDMMC_CLK_SRC_PLL160M

Select PLL_160M as the source clock

enumerator SDMMC_CLK_SRC_PLL200M

Select PLL_200M as the source clock

Header File

• components/esp_hw_support/include/esp_clk_tree.h

• This header file can be included with:

  #include "esp_clk_tree.h"
  

Functions

esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value)

Get frequency of module clock source.

参数

• clk_src -- [in] Clock source available to modules, in soc_module_clk_t

• precision -- [in] Degree of precision, one of esp_clk_tree_src_freq_precision_t values This arg only applies to the clock sources that their frequencies can vary: SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256, SOC_MOD_CLK_XTAL32K For other clock sources, this field is ignored.

• freq_value -- [out] Frequency of the clock source, in Hz

返回

• ESP_OK Success

• ESP_ERR_INVALID_ARG Parameter error

• ESP_FAIL Calibration failed

Enumerations

enum esp_clk_tree_src_freq_precision_t

Degree of precision of frequency value to be returned by esp_clk_tree_src_get_freq_hz()

Values:

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID

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