Watchdog

[中文]

ESP Watchdog Timer Classification

Taking ESP32-C3 as an example, as follows:

  • ESP32-C3
    • Digital Watchdog Timer

      • Main System Watchdog Timer (MWDT0 & MWDT1)

      • RTC Watchdog Timer (RWDT)

    • Analog Watchdog Timer

      • Super Watchdog (SWD)

Watchdog Trigger Principle

Taking ESP32-C3 as an example, it has two main system watchdog timers, namely MWDT0 and MWDT1. The digital watchdog will go through multiple stages during operation, and each stage can configure separate timeout time and timeout action. The existing logic is as follows:

The task watchdog uses MWDT0, the interrupt watchdog uses MWDT1, if ESP does not feed the dog in time, causing the watchdog timeout will trigger the watchdog interrupt.

Note

ESP32-C2 only has one timer group, so there is only one main system watchdog MWDT0, which is bound to the interrupt watchdog. At this time, the task watchdog is implemented using esp_timer.

Interrupt Watchdog

Since there is already an Interrupt Watchdog Document in the ESP-IDF Programming Guide, only key points are summarized here.

The purpose of the interrupt watchdog:

  • Ensure that the interrupt service program will not be blocked for a long time

The main reasons for triggering the interrupt watchdog are:

  • Prevented the operation of the low-priority feed dog ISR

    • Disable interrupts

    • Critical area (also disables interrupts)

    • Other ISRs of the same or higher priority will prevent ISRs of the same or lower priority from completing

  • Time-consuming code segments are placed in the ISR

Task Watchdog

Since there is already a Task Watchdog Document in the ESP-IDF Programming Guide, only key points are summarized here.

The purpose of the task watchdog:

  • Used to monitor specific tasks to ensure that tasks are executed within the configured timeout time

The main reasons for triggering the task watchdog are:

  • The task runs for a long time without yielding the CPU

TimerGroup Watchdog

Common LOG:

1. rst:0x8 (TG1WDT_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
2. rst:0x7 (TG0WDT_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)

Trigger conditions:

  • Task interrupts and task scheduling cannot be triggered normally, it can be considered that there is an exception in CPU operation

Possible reasons:

  • CPU instruction fetching is abnormal, at this time suspect whether there is hardware interference in Flash or PSRAM communication, such as abnormal occupation of Flash or PSRAM pins, high frequency interference, etc.

  • Unstable power supply

  • Possible wild pointer problem

RTC Watchdog

Common LOG:

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

Features:

  • In addition to resetting digital peripherals, it also resets the RTC module

  • Can be called in the program

Stages that can trigger the RTC watchdog:

  • Boot stage: This watchdog needs to be enabled at this stage through the CONFIG_BOOTLOADER_WDT_ENABLE option

  • Restart stage

  • Panic Stage

  • Enter the light sleep stage, after entering light sleep, the hardware will automatically turn off the RTC watchdog

Other watchdogs

External hardware watchdog

The user may encounter the following abnormal scenarios:

  • The hardware has unstable power supply

  • Occasionally, the chip hangs without triggering any reset

In this case, it is recommended to connect an external hardware watchdog, which can be fed by periodically flipping the GPIO through the software program, to avoid the situation where the ESP chip is always hanging.