Available on crate feature
unstable
only.Expand description
§Stability
This API is marked as unstable and is only available when the unstable
crate feature is enabled. This comes with no stability guarantees, and could be changed
or removed at any time.
§Reading of eFuses (ESP32-S2)
§Overview
The efuse
module provides functionality for reading eFuse data
from the ESP32-S2
chip, allowing access to various chip-specific
information such as:
- MAC address
- core count
- CPU frequency
- chip type
and more. It is useful for retrieving chip-specific configuration and identification data during runtime.
The Efuse
struct represents the eFuse peripheral and is responsible for
reading various eFuse fields and values.
§Examples
§Read data from the eFuse storage.
let mac_address = Efuse::read_base_mac_address();
println!(
"MAC: {:#X}:{:#X}:{:#X}:{:#X}:{:#X}:{:#X}",
mac_address[0],
mac_address[1],
mac_address[2],
mac_address[3],
mac_address[4],
mac_address[5]
);
println!("MAC address {:02x?}", Efuse::mac_address());
println!("Flash Encryption {:?}", Efuse::flash_encryption());
Structs§
- A struct representing the eFuse functionality of the chip.
Constants§
[]
4 bit of ADC calibration[]
BLK_VERSION_MAJOR[]
BLK_VERSION_MINOR of BLOCK2 {0: “No calib”; 1: “ADC calib V1”; 2: “ADC calib V2”}[]
BLOCK0 efuse version[]
Disables check of blk version major[]
Disables check of wafer version major[]
Disables capability to Remap RAM to ROM address space[]
Set this bit to disable Dcache[]
Disables Dcache when SoC is in Download mode[]
Disables Icache when SoC is in Download mode[]
Disables flash encryption when in download boot modes[]
Set this bit to disable all download boot modes[]
Set this bit to disable the function that forces chip into download mode[]
Set this bit to disable Icache[]
Set this bit to disable Legacy SPI boot mode[DIS_CAN]
Set this bit to disable the TWAI Controller function[]
Set this bit to disable USB OTG function[]
Set this bit to disable use of USB OTG in UART download boot mode[]
Set this bit to enable secure UART download mode (read/write flash only)[]
Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms[]
SPI flash type {0: “4 data lines”; 1: “8 data lines”}[]
Flash version[]
If set; forces ROM code to send an SPI flash resume command during SPI boot[]
Hardware disables JTAG permanently[BLOCK_KEY0]
Key0 or user data[BLOCK_KEY1]
Key1 or user data[BLOCK_KEY2]
Key2 or user data[BLOCK_KEY3]
Key3 or user data[BLOCK_KEY4]
Key4 or user data[BLOCK_KEY5]
Key5 or user data[KEY0_PURPOSE]
Purpose of KEY0[KEY1_PURPOSE]
Purpose of KEY1[KEY2_PURPOSE]
Purpose of KEY2[KEY3_PURPOSE]
Purpose of KEY3[KEY4_PURPOSE]
Purpose of KEY4[KEY5_PURPOSE]
Purpose of KEY5[MAC_FACTORY]
MAC address[]
Optional unique 128-bit ID[]
Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: “VDD3P3_CPU”; 1: “VDD_SPI”}[]
Package version[]
PSRAM version[]
Disable reading from BlOCK4-10[RD_DIS.KEY0]
rd_dis of BLOCK_KEY0[RD_DIS.KEY1]
rd_dis of BLOCK_KEY1[RD_DIS.KEY2]
rd_dis of BLOCK_KEY2[RD_DIS.KEY3]
rd_dis of BLOCK_KEY3[RD_DIS.KEY4]
rd_dis of BLOCK_KEY4[RD_DIS.KEY5]
rd_dis of BLOCK_KEY5[RD_DIS.SYS_DATA_PART2]
rd_dis of BLOCK_SYS_DATA2[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
Set this bit to enable aggressive secure boot key revocation mode[]
Set this bit to enable secure boot[]
Revoke 1st secure boot key[]
Revoke 2nd secure boot key[]
Revoke 3rd secure boot key[]
Secure version (used by ESP-IDF anti-rollback feature)[]
Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral[]
Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: “Disable”; 1: “Enable”; 3: “Disable”; 7: “Enable”}[]
SPI_PAD_configure CLK[]
SPI_PAD_configure CS[]
SPI_PAD_configure D(D0)[]
SPI_PAD_configure D4[]
SPI_PAD_configure D5[]
SPI_PAD_configure D6[]
SPI_PAD_configure D7[]
SPI_PAD_configure DQS[]
SPI_PAD_configure HD(D3)[]
SPI_PAD_configure Q(D1)[]
SPI_PAD_configure WP(D2)[BLOCK_SYS_DATA2]
System data part 2 (reserved)[]
Temperature calibration data[]
Selects the default UART for printing boot messages {0: “UART0”; 1: “UART1”}[]
Set the default UART boot message output mode {0: “Enable”; 1: “Enable when GPIO46 is low at reset”; 2: “Enable when GPIO46 is high at reset”; 3: “Disable”}[]
Set this bit to exchange USB D+ and D- pins[EXT_PHY_ENABLE]
Set this bit to enable external USB PHY[]
If set; forces USB BVALID to 1[BLOCK_USR_DATA]
User data[MAC_CUSTOM CUSTOM_MAC]
Custom MAC[]
Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO[]
If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: “VDD_SPI connects to 1.8 V LDO”; 1: “VDD_SPI connects to VDD3P3_RTC_IO”}[]
If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on[]
WAFER_VERSION_MAJOR[]
WAFER_VERSION_MINOR most significant bit[]
WAFER_VERSION_MINOR least significant bits[]
RTC watchdog timeout threshold; in unit of slow clock cycle {0: “40000”; 1: “80000”; 2: “160000”; 3: “320000”}[]
Disable programming of individual eFuses[]
wr_dis of ADC_CALIB[]
wr_dis of BLOCK1[]
wr_dis of BLK_VERSION_MAJOR[]
wr_dis of BLK_VERSION_MINOR[]
wr_dis of BLOCK0_VERSION[WR_DIS.KEY0]
wr_dis of BLOCK_KEY0[WR_DIS.KEY1]
wr_dis of BLOCK_KEY1[WR_DIS.KEY2]
wr_dis of BLOCK_KEY2[WR_DIS.KEY3]
wr_dis of BLOCK_KEY3[WR_DIS.KEY4]
wr_dis of BLOCK_KEY4[WR_DIS.KEY5]
wr_dis of BLOCK_KEY5[WR_DIS.SYS_DATA_PART2]
wr_dis of BLOCK_SYS_DATA2[WR_DIS.USER_DATA]
wr_dis of BLOCK_USR_DATA[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]
wr_dis of CUSTOM_MAC[]
wr_dis of DIS_BOOT_REMAP[]
wr_dis of DIS_DCACHE[]
wr_dis of DIS_DOWNLOAD_DCACHE[]
wr_dis of DIS_DOWNLOAD_ICACHE[]
wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT[]
wr_dis of DIS_DOWNLOAD_MODE[]
wr_dis of DIS_FORCE_DOWNLOAD[]
wr_dis of DIS_ICACHE[]
wr_dis of DIS_LEGACY_SPI_BOOT[WR_DIS.DIS_CAN]
wr_dis of DIS_TWAI[]
wr_dis of DIS_USB[]
wr_dis of DIS_USB_DOWNLOAD_MODE[]
wr_dis of ENABLE_SECURITY_DOWNLOAD[]
wr_dis of FLASH_TPUW[]
wr_dis of FLASH_TYPE[]
wr_dis of FLASH_VERSION[]
wr_dis of FORCE_SEND_RESUME[]
wr_dis of HARD_DIS_JTAG[WR_DIS.KEY0_PURPOSE]
wr_dis of KEY_PURPOSE_0[WR_DIS.KEY1_PURPOSE]
wr_dis of KEY_PURPOSE_1[WR_DIS.KEY2_PURPOSE]
wr_dis of KEY_PURPOSE_2[WR_DIS.KEY3_PURPOSE]
wr_dis of KEY_PURPOSE_3[WR_DIS.KEY4_PURPOSE]
wr_dis of KEY_PURPOSE_4[WR_DIS.KEY5_PURPOSE]
wr_dis of KEY_PURPOSE_5[WR_DIS.MAC_FACTORY]
wr_dis of MAC[]
wr_dis of OPTIONAL_UNIQUE_ID[]
wr_dis of PIN_POWER_SELECTION[]
wr_dis of PKG_VERSION[]
wr_dis of PSRAM_VERSION[]
wr_dis of RD_DIS[]
wr_dis of RTCCALIB_V1IDX_A10H[]
wr_dis of RTCCALIB_V1IDX_A10L[]
wr_dis of RTCCALIB_V1IDX_A11H[]
wr_dis of RTCCALIB_V1IDX_A11L[]
wr_dis of RTCCALIB_V1IDX_A12H[]
wr_dis of RTCCALIB_V1IDX_A12L[]
wr_dis of RTCCALIB_V1IDX_A13H[]
wr_dis of RTCCALIB_V1IDX_A13L[]
wr_dis of RTCCALIB_V1IDX_A20H[]
wr_dis of RTCCALIB_V1IDX_A20L[]
wr_dis of RTCCALIB_V1IDX_A21H[]
wr_dis of RTCCALIB_V1IDX_A21L[]
wr_dis of RTCCALIB_V1IDX_A22H[]
wr_dis of RTCCALIB_V1IDX_A22L[]
wr_dis of RTCCALIB_V1IDX_A23H[]
wr_dis of RTCCALIB_V1IDX_A23L[]
wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE[]
wr_dis of SECURE_BOOT_EN[]
wr_dis of SECURE_BOOT_KEY_REVOKE0[]
wr_dis of SECURE_BOOT_KEY_REVOKE1[]
wr_dis of SECURE_BOOT_KEY_REVOKE2[]
wr_dis of SECURE_VERSION[]
wr_dis of SOFT_DIS_JTAG[]
wr_dis of SPI_BOOT_CRYPT_CNT[]
wr_dis of SPI_PAD_CONFIG_CLK[]
wr_dis of SPI_PAD_CONFIG_CS[]
wr_dis of SPI_PAD_CONFIG_D[]
wr_dis of SPI_PAD_CONFIG_D4[]
wr_dis of SPI_PAD_CONFIG_D5[]
wr_dis of SPI_PAD_CONFIG_D6[]
wr_dis of SPI_PAD_CONFIG_D7[]
wr_dis of SPI_PAD_CONFIG_DQS[]
wr_dis of SPI_PAD_CONFIG_HD[]
wr_dis of SPI_PAD_CONFIG_Q[]
wr_dis of SPI_PAD_CONFIG_WP[]
wr_dis of BLOCK2[]
wr_dis of TEMP_CALIB[]
wr_dis of UART_PRINT_CHANNEL[]
wr_dis of UART_PRINT_CONTROL[]
wr_dis of USB_EXCHG_PINS[WR_DIS.EXT_PHY_ENABLE]
wr_dis of USB_EXT_PHY_ENABLE[]
wr_dis of USB_FORCE_NOPERSIST[]
wr_dis of VDD_SPI_FORCE[]
wr_dis of VDD_SPI_TIEH[]
wr_dis of VDD_SPI_XPD[]
wr_dis of WAFER_VERSION_MAJOR[]
wr_dis of WAFER_VERSION_MINOR_HI[]
wr_dis of WAFER_VERSION_MINOR_LO[]
wr_dis of WDT_DELAY_SEL