Struct FrameTiming

pub struct FrameTiming {
    pub horizontal_total_width: usize,
    pub horizontal_blank_front_porch: usize,
    pub horizontal_active_width: usize,
    pub vertical_total_height: usize,
    pub vertical_blank_front_porch: usize,
    pub vertical_active_height: usize,
    pub vsync_width: usize,
    pub hsync_width: usize,
    pub hsync_position: usize,
}

Available on crate feature unstable only.

The timing numbers for the driver to follow.

Note: The names of the fields in this struct don’t match what you would typically find in an LCD’s datasheet. Carefully read the doc on each field to understand what to set it to.

Fields

horizontal_total_width: usize

The horizontal total width of a frame (in units of PCLK).

This should be greater than horizontal_blank_front_porch + horizontal_active_width.

Max is 4096 (12 bits).

horizontal_blank_front_porch: usize

The horizontal blank front porch of a frame (in units of PCLK).

This is the number of PCLKs between the start of the line and the start of active data in the line.

Note: This includes hsync_width.

Max is 2048 (11 bits).

horizontal_active_width: usize

The horizontal active width of a frame. i.e. The number of pixels in a line. This is typically the horizontal resolution of the screen.

Max is 4096 (12 bits).

vertical_total_height: usize

The vertical total height of a frame (in units of lines).

This should be greater than vertical_blank_front_porch + vertical_active_height.

Max is 1024 (10 bits).

vertical_blank_front_porch: usize

The vertical blank front porch height of a frame (in units of lines).

This is the number of (blank/invalid) lines before the start of the frame.

Note: This includes vsync_width.

Max is 256 (8 bits).

vertical_active_height: usize

The vertical active height of a frame. i.e. The number of lines in a frame. This is typically the vertical resolution of the screen.

Max is 1024 (10 bits).

vsync_width: usize

It is the width of LCD_VSYNC active pulse in a line (in units of lines).

Max is 128 (7 bits).

hsync_width: usize

The width of LCD_HSYNC active pulse in a line (in units of PCLK).

This should be less than vertical_blank_front_porch, otherwise the hsync pulse will overlap with valid pixel data.

Max is 128 (7 bits).

hsync_position: usize

It is the position of LCD_HSYNC active pulse in a line (in units of PCLK).

This should be less than horizontal_total_width.

Max is 128 (7 bits).

Trait Implementations

impl Clone for FrameTiming

fn clone(&self) -> FrameTiming

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for FrameTiming

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for FrameTiming

fn default() -> FrameTiming

Returns the “default value” for a type.

impl PartialEq for FrameTiming

fn eq(&self, other: &FrameTiming) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for FrameTiming

impl StructuralPartialEq for FrameTiming