Enum CpuPllDivInConfig 

pub enum CpuPllDivInConfig {
    Pll,
    Apll,
}

Available on crate feature unstable only.

The list of clock signals that the CPU_PLL_DIV_IN multiplexer can output.

Variants

Pll

Selects PLL_CLK.

Apll

Selects APLL_CLK.

Trait Implementations

impl Clone for CpuPllDivInConfig

fn clone(&self) -> CpuPllDivInConfig

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CpuPllDivInConfig

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for CpuPllDivInConfig

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given [Hasher].

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given [Hasher].

impl PartialEq for CpuPllDivInConfig

fn eq(&self, other: &CpuPllDivInConfig) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CpuPllDivInConfig

impl Eq for CpuPllDivInConfig

impl StructuralPartialEq for CpuPllDivInConfig