Module ethernet 

Available on crate feature unstable only.

EMAC Ethernet driver for ESP32.

The driver provides blocking and async Ethernet APIs.

Quick start (RMII, external reference clock)

use esp_hal::ethernet::{
    Ethernet,
    EthernetDmaStorage,
    RmiiPinBundle,
    clock::ExternalRefClock,
    phy::generic::GenericPhy,
};

let mut storage: EthernetDmaStorage<10, 10> = EthernetDmaStorage::new();

let mut eth = Ethernet::new(
    peripherals.ETH,
    &mut storage,
    [0x02, 0x00, 0x00, 0x12, 0x34, 0x56],
    GenericPhy::new_auto(),
    RmiiPinBundle {
        clock: ExternalRefClock::new(peripherals.GPIO0), // REF_CLK from PHY
        rxd0: peripherals.GPIO25,
        rxd1: peripherals.GPIO26,
        rx_dv: peripherals.GPIO27,
        txd0: peripherals.GPIO19,
        txd1: peripherals.GPIO22,
        tx_en: peripherals.GPIO21,
        mdc: peripherals.GPIO23,
        mdio: peripherals.GPIO18,
    },
)
.unwrap();
// `eth` has type `Ethernet<'_, Blocking, GenericPhy>`

Modules

clock

EMAC clock configuration for ESP32.

mac

MAC register abstraction for the EMAC driver.

phy

PHY abstraction layer.

Structs

Ethernet

EMAC Ethernet driver.

EthernetDmaStorage

Static backing storage for all DMA descriptor rings and packet buffers.

MiiPinBundle

Wired MII pads (pass to Ethernet::new).

RmiiPinBundle

Wired RMII pads and RMII clock (pass to Ethernet::new).

Enums

Error

Error type returned by Ethernet operations.

Traits

EthernetPinBundle

RMII or MII pad wiring for Ethernet::new.

MiiRxClk

MII RX clock pin

MiiRxDv

MII RX data valid pin

MiiRxd0

MII RXD0 pin

MiiRxd1

MII RXD1 pin

MiiRxd2

MII RXD2 pin

MiiRxd3

MII RXD3 pin

MiiTxClk

MII TX clock pin

MiiTxEn

MII TX enable pin

MiiTxd0

MII TXD0 pin

MiiTxd1

MII TXD1 pin

MiiTxd2

MII TXD2 pin

MiiTxd3

MII TXD3 pin

RmiiClkIn

RMII CLK input pin

RmiiClkOut

RMII CLK output pin

RmiiClockConfig

Sealed trait implemented by all RMII clock configurations.

RmiiCrsDv

RMII CRS/DV pin

RmiiRxd0

RMII RXD0 pin

RmiiRxd1

RMII RXD1 pin

RmiiTxEn

RMII TX enable pin

RmiiTxd0

RMII TXD0 pin

RmiiTxd1

RMII TXD1 pin