esp_wifi/common_adapter/
common_adapter_esp32c2.rs

1use portable_atomic::{AtomicU32, Ordering};
2
3use crate::binary::include::*;
4
5const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4;
6
7static mut SOC_PHY_DIG_REGS_MEM: [u8; SOC_PHY_DIG_REGS_MEM_SIZE] = [0u8; SOC_PHY_DIG_REGS_MEM_SIZE];
8static mut G_IS_PHY_CALIBRATED: bool = false;
9static mut G_PHY_DIGITAL_REGS_MEM: *mut u32 = core::ptr::null_mut();
10static mut S_IS_PHY_REG_STORED: bool = false;
11static PHY_ACCESS_REF: AtomicU32 = AtomicU32::new(0);
12
13pub(crate) fn enable_wifi_power_domain() {
14    // In esp-idf, neither SOC_PM_SUPPORT_MODEM_PD or SOC_PM_SUPPORT_WIFI_PD are
15    // defined, which makes `esp_wifi_bt_power_domain_on` a no-op.
16}
17
18pub(crate) fn phy_mem_init() {
19    unsafe {
20        G_PHY_DIGITAL_REGS_MEM = core::ptr::addr_of_mut!(SOC_PHY_DIG_REGS_MEM).cast();
21    }
22}
23
24pub(crate) unsafe fn bbpll_en_usb() {
25    // nothing for ESP32-C2
26}
27
28pub(crate) unsafe fn phy_enable() {
29    let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst);
30    if count == 0 {
31        critical_section::with(|_| {
32            unsafe {
33                super::phy_enable_clock();
34            }
35
36            if unsafe { !G_IS_PHY_CALIBRATED } {
37                super::phy_calibrate();
38                unsafe { G_IS_PHY_CALIBRATED = true };
39            } else {
40                unsafe {
41                    phy_wakeup_init();
42                }
43                phy_digital_regs_load();
44            }
45
46            #[cfg(feature = "ble")]
47            {
48                unsafe extern "C" {
49                    fn coex_pti_v2();
50                }
51                unsafe {
52                    coex_pti_v2();
53                }
54            }
55
56            trace!("PHY ENABLE");
57        });
58    }
59}
60
61#[allow(unused)]
62pub(crate) unsafe fn phy_disable() {
63    let count = PHY_ACCESS_REF.fetch_sub(1, Ordering::SeqCst);
64    if count == 1 {
65        critical_section::with(|_| {
66            phy_digital_regs_store();
67            unsafe {
68                // Disable PHY and RF.
69                phy_close_rf();
70
71                // Disable PHY temperature sensor
72                phy_xpd_tsens();
73
74                // #if CONFIG_IDF_TARGET_ESP32
75                //         // Update WiFi MAC time before disalbe WiFi/BT common peripheral
76                // clock         phy_update_wifi_mac_time(true,
77                // esp_timer_get_time()); #endif
78
79                // Disable WiFi/BT common peripheral clock. Do not disable clock for hardware
80                // RNG
81                super::phy_disable_clock();
82            }
83            trace!("PHY DISABLE");
84        });
85    }
86}
87
88fn phy_digital_regs_load() {
89    unsafe {
90        if S_IS_PHY_REG_STORED && !G_PHY_DIGITAL_REGS_MEM.is_null() {
91            phy_dig_reg_backup(false, G_PHY_DIGITAL_REGS_MEM);
92        }
93    }
94}
95
96fn phy_digital_regs_store() {
97    unsafe {
98        if !G_PHY_DIGITAL_REGS_MEM.is_null() {
99            phy_dig_reg_backup(true, G_PHY_DIGITAL_REGS_MEM);
100            S_IS_PHY_REG_STORED = true;
101        }
102    }
103}