Errata Summary

Table 4 Errata summary
Category	Descriptions	Affected Revisions
Category	Descriptions	v0.0	v0.1	v0.2
RISC-V CPU	[CPU] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved	Y	Y
Clock	[Clock] Inaccurate Calibration of RC_FAST_CLK Clock	Y
Reset	[Reset] System Reset Triggered by RTC Watchdog Timer Cannot Be Correctly Reported	Y
SPI	[SPI] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read	Y	Y
RMT	[RMT] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode	Y	Y	Y
SAR ADC	[SAR ADC] Data Duplication May Occur When SAR ADC Accessing GDMA	Y	Y
SAR ADC	[SAR ADC] Loss of Precision in Lower Four Bits of SAR ADC	Y	Y
Wi-Fi	[Wi-Fi] ESP32-C6 Cannot Be 802.11mc FTM Initiator	Y	Y