ESP Chip Errata Logo

ESP32-C6 Series SoC Errata

  • Chip Revision Identification
  • Errata Summary
  • All Errata Descriptions
  • Errata Descriptions by Chip Revisions
  • Revision History

Resources and Legal Notices

  • Related Documentation and Resources
  • Disclaimer and Copyright Notice
ESP Chip Errata
  • Errata Summary
  • Download PDF

Errata Summary

[中文]

Table 4 Errata summary

Category

Errata No.

Descriptions

Affected Revisions

v0.0

v0.1

v0.2

RISC-V CPU

CPU-206

[CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved

Y

Y

Clock

CLK-6996

[CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock

Y

CLK-8588

[CLK-8588] 32 kHz Internal Slow RC Oscillator May Fail to Oscillate

Y

Y

Y

Reset

RES-7080

[RES-7080] System Reset Triggered by RTC Watchdog Timer Cannot Be Correctly Reported

Y

SPI

SPI-304

[SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read

Y

Y

RMT

RMT-176

[RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode

Y

Y

Y

SAR ADC

ADC-305

[ADC-305] Data Duplication May Occur When SAR ADC Accessing GDMA

Y

Y

ADC-1477

[ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC

Y

Y

Wi-Fi

WIFI-9686

[WIFI-9686] ESP32-C6 Cannot Be 802.11mc FTM Initiator

Y

Y

Next Previous

Suggestion on this document?

 Provide feedback
Help improve this document?

 Edit on GitHub
Need more information?

 Check ESP forum
 Sales Questions
 Technical Inquiries

  • © Copyright 2024 - 2025, Espressif Systems (Shanghai) Co., Ltd

    Built with Sphinx using a theme based on Read the Docs Sphinx Theme.