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ESP32-H2 Series SoC Errata

  • Chip Revision Identification
  • Errata Summary
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  • Errata Descriptions by Chip Revisions
  • Revision History

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Errata Summary

[δΈ­ζ–‡]

Table 4 Errata summary

Category

Errata No.

Descriptions

Affected Revisions

v0.0

v0.1

v1.2

RISC-V CPU

CPU-206

[CPU-206] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved

Y

Y

Clock

CLK-6996

[CLK-6996] Inaccurate Calibration of RC_FAST_CLK Clock

Y

Y

SAR ADC

ADC-7227

[ADC-7227] Unavailable Channel 4 in SRA ADC1

Y

Y

ADC-1477

[ADC-1477] Loss of Precision in Lower Four Bits of SAR ADC

Y

Y

I2C

I2C-308

[I2C-308] I2C Slave Fails in Multiple-read Under Non-FIFO Mode

Y

Y

SPI

SPI-304

[SPI-304] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read

Y

Y

LEDC

LEDC-253

[LEDC-253] Unable to Reach 100% Duty Cycle at Maximum Duty Resolution

Y

Y

RMT

RMT-176

[RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode

Y

Y

Chip Boot

BOOT-9537

[BOOT-9537] Accidentally Enter USB Download Boot Mode If the Power-up Duration Is Too Long

Y

Y

AES|XTS-AES

AES-11401

[AES-11401] CPA Attack-Related Security Vulnerability

Y

Y

ECC|ECDSA

ECC-11400

[ECC-11400] Timing Attack-Related Security Vulnerability

Y

Y

802.15.4

802.15.4-9538

[802.15.4-9538] TX Power Variation in Certain RF Certification

Y

Y

PCNT

PCNT-249

[PCNT-249] Unable to Trigger Step Interrupts

Y

Y

Y

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