Errata Summary

[中文]

Table 4 Errata summary

Category	Descriptions	Affected Revisions
		v0.0	v0.1
RISC-V CPU	[CPU] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved	Y	Y
Clock	[Clock] Inaccurate Calibration of RC_FAST_CLK Clock	Y	Y
SAR ADC	[SAR ADC] Unavailable Channel 4 in SRA ADC1	Y	Y