All Errata Descriptions
[RTC] RTC Register Read Error After Wake-up from Light-sleep Mode
Description
If an RTC peripheral is turned off in Light-sleep mode, there is a certain probability that after waking up from Light-sleep, the CPU of ESP32-S3 will read the registers in the RTC power domain incorrectly.
Workarounds
Users are suggested not to power down RTC peripherals in Light-sleep mode. There will be no impact on power consumption.
This issue has been bypassed in ESP-IDF v4.4 and above.
Solution
No fix scheduled.
[Analog Power] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1
Description
If the analog power is configured as BIAS_SLEEP = 0 and PD_CUR = 1, the chip will be permanently damaged. This issue might be triggered when ULP and/or touch sensor is used during Light-sleep or Deep-sleep.
Workarounds
Users are suggested to disable such analog power configuration in sleep mode through software.
This issue has been bypassed by disabling the above configuration in ESP-IDF v4.4.2+, v5.0 and above.
Solution
No fix scheduled.
[LCD] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used
Description
When the RGB format is used, if the clock divider is set to 1, i.e., LCD_CAM_LCD_CLK_EQU_SYSCLK = 1:
The pixel clock output (LCD_PCLK) will not be able to be set to falling edge trigger.
When frames are continuously sent in this mode (i.e., LCD_CAM_LCD_NEXT_FRAME_EN = 1), it might occur that the second frame inserts the last data of the previous frame in the first frame.
When the I8080 format is used, if the clock cycle of the LCD core clock (LCD_CLK) before data transmission is less than or equal to 2, it can result in incorrect value of the first data and the subsequent data quantity.
Note
Please refer to the following steps to obtain the clock cycle before data transmission with the I8080 format.
The clock cycle before data transmission depends on the following factors:
VFK cycle length (unit: LCD_PCLK): The clock cycle length during the VFK phase
CMD cycle length (unit: LCD_PCLK): The clock cycle length during the CMD phase
DUMMY cycle length (unit: LCD_PCLK): The clock cycle length during the DUMMY phase
LCD_CAM_LCD_CLK_EQU_SYSCLK: Decides if LCD_PCLK equals LCD_CLK
LCD_CAM_LCD_CLKCNT_N: Decides the division relationship between LCD_PCLK and LCD_CLK
Based on the information above, three variables are defined below:
total_pixels = VFK cycle length + CMD cycle length + DUMMY cycle length
cycle_unit =
1, if LCD_CAM_LCD_CLK_EQU_SYSCLK = 1
LCD_CAM_LCD_CLKCNT_N + 1, if LCD_CAM_LCD_CLK_EQU_SYSCLK = 0
ahead_cycle = total_pixels * cycle_unit
ahead_cycle indicates the clock cycle before data transmission, which, if less than or equal to 2, will cause an error.
Workarounds
Users are suggested to do the followings:
When using the RGB format, avoid configuring LCD_CAM_LCD_CLK_EQU_SYSCLK as 1.
When using the I8080 format:
try to avoid configuring LCD_CAM_LCD_CLK_EQU_SYSCLK as 1.
ensure that ahead_cycle is larger than 2 if LCD_CAM_LCD_CLK_EQU_SYSCLK has to be set as 1.
This issue has been bypassed through the methods described above in ESP-IDF v4.4.5+, v5.0.3+, v5.1 and above.
Solution
No fix scheduled.
[RMT] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode
Description
In ESP32-S3’s RMT module, if the continuous TX mode is enabled, it is expected that the data transmission stops after the data is sent for RMT_TX_LOOP_NUM_CHn rounds, and after that, the signal level in idle state should be controlled by the “level” field of the end-marker.
However, in real situation, after the data transmission stops, the channel’s idle state signal level is not controlled by the “level” field of the end-marker, but by the level in the data wrapped back, which is indeterminate.
Workarounds
Users are suggested to set RMT_IDLE_OUT_EN_CHn to 1 to only use registers to control the idle level.
This issue has been bypassed since the first ESP-IDF version that supports continuous TX mode (v5.0). In these versions of ESP-IDF, it is configured that the idle level can only be controlled by registers.
Solution
No fix scheduled.
[Touch Sensor] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined
Description
For ESP32-S3’s touch sensor, the raw data value is undefined for the first two TOUCH_SCAN_DONE_INT interrupts.
Workarounds
Users are suggested to skip the first two TOUCH_SCAN_DONE_INT interrupts, then turn them off and stop using them.
Solution
No fix scheduled.
[SAR ADC] The Digital Controller (DMA) of SAR ADC2 Cannot Work
Description
The Digital Controller of SAR ADC2, i.e., DIG ADC2 controller, may receive a false sampling enable signal. In such a case, the controller will enter an inoperative state.
Workarounds
It is suggested to use RTC controller to control SAR ADC2.
Solution
No fix scheduled.