ESP Chip Errata Logo

ESP32-S3 Series SoC Errata

  • Chip Revision Identification
  • Errata Summary
  • All Errata Descriptions
  • Errata Descriptions by Chip Revisions
    • v0.0 (8)
    • v0.1 (8)
      • [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1
      • [CACHE-126] Cache Hit Error During Cache Write-Backs
      • [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used
      • [USBOTG-4289] The USB-OTG Download Function Is Unavailable
      • [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode
      • [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode
      • [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work
      • [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined
    • v0.2 (8)
  • Revision History

Resources and Legal Notices

  • Related Documentation and Resources
  • Disclaimer and Copyright Notice
ESP Chip Errata
  • Errata Descriptions by Chip Revisions
  • Chip Revision: v0.1
  • Download PDF

Chip Revision: v0.1

Known Errors

  • [ANALOG-160] Chip Will Be Damaged When BIAS_SLEEP = 0 and PD_CUR = 1
  • [CACHE-126] Cache Hit Error During Cache Write-Backs
  • [LCD-239] The LCD Module Exhibits Unreliable Behavior When Certain Clock Dividers Are Used
  • [USBOTG-4289] The USB-OTG Download Function Is Unavailable
  • [RMT-176] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode
  • [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode
  • [ADC-183] The Digital Controller (DMA) of SAR ADC2 Cannot Work
  • [TOUCH-100] The TOUCH_SCAN_DONE_INT Interrupt Raw Data Value Is Undefined
Next Previous

Suggestion on this document?

 Provide feedback
Help improve this document?

 Edit on GitHub
Need more information?

 Check ESP forum
 Sales Questions
 Technical Inquiries

  • © Copyright 2024 - 2025, Espressif Systems (Shanghai) Co., Ltd

    Built with Sphinx using a theme based on Read the Docs Sphinx Theme.