PCB Layout Design
This chapter introduces the key points of how to design an ESP32-C2 PCB layout using an ESP32-C2 module (see Figure ESP32-C2 Reference PCB Layout) as an example.
ESP32-C2 Reference PCB Layout
General Principles of PCB Layout
It is recommended to use a four-layer PCB design:
Layer 1 (TOP): Signal traces and components.
Layer 2 (GND): No signal traces here to ensure a complete GND plane.
Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces and a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal.
Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on this layer.
A two-layer PCB design can also be used:
Layer 1 (TOP): Signal traces and components.
Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Please make sure there is a complete GND plane for the chip, RF, and crystal.
Positioning a Module on a Base Board
If module-on-board design is adopted, attention should be paid while positioning the module on the base board. The interference of the baseboard on the module’s antenna performance should be minimized.
It is suggested to place the module’s on-board PCB antenna outside the base board, and the feed point of the antenna closest to the board. In the following example figures, positions with mark ✓ are strongly recommended, while positions without a mark are not recommended.
Placement of ESP32-C2 Modules on Base Board (antenna feed point on the left)
If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna area (no copper, routing, or components on it), and place the feed point of the antenna closest to the board. If there is a base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna. Figure Keepout Zone for ESP32-C2 Module’s Antenna on the Base Board shows the suggested clearance for modules whose antenna feed point is on the left.
Keepout Zone for ESP32-C2 Module’s Antenna on the Base Board
When designing an end product, attention should be paid to the interference caused by the housing of the antenna and it is recommended to carry out RF verification. It is necessary to test the throughput and communication signal range of the whole product to ensure the product’s actual RF performance.
Power Supply
Figure ESP32-C2 Power Traces in a Four-layer PCB Design shows the overview of the power traces in a four-layer PCB design.
ESP32-C2 Power Traces in a Four-layer PCB Design
Figure ESP32-C2 Power Traces in a Two-layer PCB Design shows the overview of the power traces in a two-layer PCB design.
ESP32-C2 Power Traces in a Two-layer PCB Design
General Guidelines
Four-layer PCB design is preferred.
The power traces should be routed on the inner third layer whenever possible.
Vias are required for the power traces to go through the layers and get connected to the pins on the top layer. There should be at least two vias if the main power traces need to cross layers. The drill diameter on other power traces should be no smaller than the width of the power traces.
The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground vias.
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as shown in Figure ESP32-C2 Power Traces in a Four-layer PCB Design. This can avoid chip displacement caused by tin leakage and bubbles when soldering the module EPAD to the substrate.
3.3 V Power Layout
The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure ESP32-C2 Power Traces in a Four-layer PCB Design.
The 3.3 V power layout should meet the following guidelines:
The ESD protection diode is placed next to the power port (circled in red in Figure ESP32-C2 Power Traces in a Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the chip, and a 0.1 or 1 µF capacitor could also be used in conjunction. After that, the power traces are divided into several branches using a star-shaped topology, which reduces the coupling between different power pins. Note that all decoupling capacitors should be placed close to the corresponding power pin, and ground vias should be added close to the capacitor’s ground pad to ensure a short return path.
In Figure ESP32-C2 Power Traces in a Four-layer PCB Design, the 10 µF capacitor is shared by the analog power supply VDDA3P3, and the power entrance since the analog power is close to the chip power entrance. If the chip power entrance is not near VDDA3P3, it is recommended to add a 10 µF capacitor to both the chip power entrance and VDDA3P3. Also, reserve two 1 µF capacitors if space permits.
The width of the main power traces should be no less than 20 mil. The width of VDDA3P3 power traces should be no less than 15 mil. The recommended width of other power traces is 10 mil.
Analog Power Layout
Figure ESP32-C2 Analog Power Traces in a Four-layer PCB Design shows the analog power layout in a four-layer PCB design.
ESP32-C2 Analog Power Traces in a Four-layer PCB Design
The analog power layout should meet the following guidelines:
As shown in Figure ESP32-C2 Analog Power Traces in a Four-layer PCB Design, it is recommended to connect the capacitor to ground in the LC filter circuit near VDDA3P3 to the fourth layer through a via, and maintain a keep-out area on other layers. The purpose is to further reduce harmonic interference.
VDDA3P3 analog power supply should be surrounded by ground copper. It is required to add GND isolation between VDDA3P3, power trace and the surrounding GPIO and RF traces, and place vias whenever possible.
Crystal
Figure ESP32-C2 Crystal Layout (without Keep-out Area on Top Layer) shows the layout for the crystal that is connected to the ground through vias but there is no keep-out area on the top layer for ground isolation.
ESP32-C2 Crystal Layout (without Keep-out Area on Top Layer)
The layout of the crystal should follow the guidelines below:
Ensure a complete GND plane for the RF, crystal, and chip.
The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least 2.0 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The clock traces should not intersect with each other.
Components in series to the crystal trace should be placed close to the chip side.
The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the clock trace, but not connected directly to the series components. This is to make sure the ground pad of the capacitor is close to that of the crystal.
Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by grounding copper.
As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interference, for example large inductance component, and ensure that there is a clean large-area ground plane around the crystal.
RF
The RF trace is routed as shown highlighted in pink in Figure ESP32-C2 RF Layout in a Four-layer PCB Design.
ESP32-C2 RF Layout in a Four-layer PCB Design
The RF layout should meet the following guidelines:
A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
ESP32-C2 PCB Stack-up Design
Add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics. It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up so that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to the third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure ESP32-C2 Stub in a Four-layer PCB Design is the stub. Note that a stub is not required for package types above 0201.
ESP32-C2 Stub in a Four-layer PCB Design
The RF trace should have a consistent width and not branch out. It should be as short as possible with dense ground vias around for interference shielding.
The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should be routed at a 135° angle, or with circular arcs if trace bends are required.
The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace whenever possible.
There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins, etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground copper and ground vias.
UART
Figure ESP32-C2 UART Layout shows the UART layout.
ESP32-C2 UART Layout
The UART layout should meet the following guidelines:
The series resistor on the U0TXD trace needs to be placed close to the chip side and away from the crystal.
The U0TXD and U0RXD traces on the top layer should be as short as possible.
The UART trace should be surrounded by ground copper and ground vias stitching.
Typical Layout Problems and Solutions
1. The voltage ripple is not large, but the TX performance of RF is rather poor.
Analysis: The voltage ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be tested when ESP32-C2 is in the normal working mode. The ripple increases when the power gets high in a different mode.
Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32-C2 sends MCS7@11n packets, and <120 mV when ESP32-C2 sends 11 MHz@11b packets.
Solution: Add a 10 μF filter capacitor to the branch of the power trace (the branch powering the chip’s analog power pin). The 10 μF capacitor should be as close to the analog power pin as possible for small and stable voltage ripples.
2. When ESP32-C2 sends data packages, the voltage ripple is small, but RF TX performance is poor.
Analysis: The RF TX performance can be affected not only by voltage ripples, but also by the crystal itself. Poor quality and big frequency offsets of the crystal decrease the RF TX performance. The crystal clock may be corrupted by other interfering signals, such as high-speed output or input signals. In addition, high-frequency signal traces, such as the SDIO traces and UART traces under the crystal, could also result in the malfunction of the crystal. Besides, sensitive components or radiating components, such as inductors and antennas, may also decrease the RF performance.
Solution: This problem is caused by improper layout for the crystal and can be solved by re-layout. Please refer to Section Crystal for details.
3. When ESP32-C2 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor.
Analysis: The disparity between the tested value and the target value may be due to signal reflection caused by the impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance mismatch will affect the working state of the internal PA, making the PA prematurely access the saturated region in an abnormal way. The EVM becomes poor as the signal distortion happens.
Solution: Match the antenna’s impedance with the π-type circuit on the RF trace, so that the impedance of the antenna as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.
4. TX performance is not bad, but the RX sensitivity is low.
Analysis: Good TX performance indicates proper RF impedance matching. Poor RX sensitivity may result from external coupling to the antenna. For instance, the crystal signal harmonics could couple to the antenna. If the TX and RX traces of UART cross over with RF trace, they will affect the RX performance, as well. If there are many high-frequency interference sources on the board, signal integrity should be considered.
Solution: Keep the antenna away from crystals. Do not route high-frequency signal traces close to the RF trace. Please refer to Section RF for details.