Schematic Checklist
The integrated circuitry of ESP32-C2 requires only 15 electrical components (resistors, capacitors, and inductors) and a crystal. The high integration of ESP32-C2 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32-C2.
The following figure shows a reference schematic design of ESP32-C2. It can be used as the basis of your schematic design.
ESP32-C2 Reference Schematic
Important
Starting from chip revision v1.1, the ESP32-C2 firmware supports both 26 MHz and 40 MHz crystals. For ESP32-C2 revision v1.0 and previous chips, please use 26 MHz instead of 40 MHz crystal. For details, you can refer to ESP32-C2 Series SoC Errata (PDF). You can also contact the sales team to check the chip revision.
Any basic ESP32-C2 circuit design may be broken down into the following major building blocks:
The rest of this chapter details the specifics of circuit design for each of these sections.
Power Supply
The general recommendations for power supply design are:
When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA.
It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32-C2 Series Datasheet > Section Power Supply.
Digital Power Supply
ESP32-C2 has pin17 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V. It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
The schematic for the digital power supply pins is shown in Figure ESP32-C2 Schematic for Digital Power Supply Pins.
ESP32-C2 Schematic for Digital Power Supply Pins
Analog Power Supply
ESP32-C2’s VDDA and VDDA3P3 pins are the analog power supply pins, working at 3.0 V ~ 3.6 V.
For VDDA3P3, when ESP32-C2 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 0.1 μF capacitor(s).
It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDDA3P3, then two 10 μF capacitors can be merged into one.
Add a LC circuit on the VDDA3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32-C2 Schematic for Analog Power Supply Pins.
ESP32-C2 Schematic for Analog Power Supply Pins
If a two-layer board design is used, it is recommended to change the CLC filter circuit for VDDA3P3 to a CCL structure, as placing the inductance closer to the chip will yield better performance. Please refer to Figure ESP32-C2 Schematic for Analog Power Supply Pins (Two-layer Board) for details.
ESP32-C2 Schematic for Analog Power Supply Pins (Two-layer Board)
RTC Power Supply
ESP32-C2’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32-C2 Schematic for RTC Power Supply Pin.
ESP32-C2 Schematic for RTC Power Supply Pin
Chip Power-up and Reset Timing
ESP32-C2’s CHIP_EN pin can enable the chip when it is high and reset the chip when it is low.
When ESP32-C2 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_EN is pulled up and the chip is enabled. Therefore, CHIP_EN needs to be asserted high after the 3.3 V rails have been brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused by external interferences, make the CHIP_EN trace as short as possible.
Figure ESP32-C2 Power-up and Reset Timing shows the power-up and reset timing of ESP32-C2.
ESP32-C2 Power-up and Reset Timing
Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements.
Parameter |
Description |
Minimum (µs) |
|---|---|---|
tSTBL |
Time reserved for the power rails to stabilize before the CHIP_EN pin is pulled high to activate the chip |
50 |
tRST |
Time reserved for CHIP_EN to stay below VIL_nRST to reset the chip |
50 |
Attention
CHIP_EN must not be left floating.
To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip.
If the user application has one of the following scenarios:
Slow power rise or fall, such as during battery charging.
Frequent power on/off operations.
Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as:
Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V.
Implementing reset functionality through a button or the main controller.
Flash
ESP32-C2 series of chips have in-package 1 MB, 2 MB or 4 MB flash. The pins for flash are not bonded out.
Clock Source
ESP32-C2 supports two external clock sources:
External Crystal Clock Source (Compulsory)
Important
Starting from chip revision v1.1, the ESP32-C2 firmware supports both 26 MHz and 40 MHz crystals. For ESP32-C2 revision v1.0 and previous chips, please use 26 MHz instead of 40 MHz crystal. For details, you can refer to ESP32-C2 Series SoC Errata (PDF). You can also contact the sales team to check the chip revision.
The circuit for the crystal is shown in Figure ESP32-C2 Schematic for External Crystal. Note that the accuracy of the selected crystal should be within ±10 ppm.
ESP32-C2 Schematic for External Crystal
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should be adjusted after an overall test.
The initial values of external capacitors C1 and C2 can be determined according to the formula:
where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below:
Select TX tone mode using the Certification and Test Tool.
Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to obtain the actual frequency offset.
Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance.
When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the external load capacitance needs to be increased.
When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external load capacitance needs to be reduced.
External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different values.
Note
Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable performance within the operating temperature range, etc) may lead to the malfunction of ESP32-C2, resulting in a decrease of the RF performance.
It is recommended that the amplitude of the crystal is greater than 500 mV.
When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps mentioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides of the crystal.
RTC Clock Source (Optional)
ESP32-C2 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock. The external RTC clock source enhances timing accuracy and consequently decreases average power consumption, without impacting functionality.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
RF
RF Circuit
ESP32-C2’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements:
For the RF traces on the PCB board, 50 Ω impedance control is required.
For the chip matching circuit, it must be placed close to the chip. A CLCCL structure is preferred.
The CLCCL structure forms a bandpass filter, which is mainly used to adjust impedance points, suppress harmonics, and suppress low-frequency noise (especially in applications such as electrical lighting where the effect is significant). If there is no AC-to-DC circuit in the user application, a simpler CLC structure can be considered.
The RF matching circuit is shown in Figure ESP32-C2 Schematic for RF Matching.
For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.
ESP32-C2 Schematic for RF Matching
RF Tuning
The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly. Follow the instructions below to do RF tuning.
Figure ESP32-C2 RF Tuning Diagram shows the general process of RF tuning.
ESP32-C2 RF Tuning Diagram
In the matching circuit, define the port near the chip as Port 1 and the port near the antenna as Port 2. S11 describes the ratio of the signal power reflected back from Port 1 to the input signal power, the transmission performance is best if the matching impedance is conjugate to the chip impedance. S21 is used to describe the transmission loss of signal from Port 1 to Port 2. If S11 is close to the chip conjugate point (30+j0) and S21 is less than -35 dB at 4.8 GHz and 7.2 GHz, the matching circuit can satisfy transmission requirements.
Connect the two ends of the matching circuit to the network analyzer, and test its signal reflection parameter S11 and transmission parameter S21. Adjust the values of the components in the circuit until S11 and S21 meet the requirements. If your PCB design of the chip strictly follows the PCB design stated in Chapter PCB Layout Design, you can refer to the value ranges in Table Recommended Value Ranges for Components to debug the matching circuit.
Reference Designator |
Recommended Value Range |
Serial No. |
|---|---|---|
C11 |
1.2 ~ 1.8 pF |
GRM0335C1H1RXBA01D |
L2 |
2.4 ~ 3.0 nH |
LQP03TN2NXB02D |
C12 |
1.8 ~ 1.2 pF |
GRM0335C1H1RXBA01D |
If the components are in the 0201 SMD package size, please use a stub in the PCB design of the RF matching circuit near the chip. If the antenna input impedance is not 50 ohm, an additional set of RF matching is recommended for antenna tuning.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD protection devices near the antenna.
Note
If RF function is not required, then the RF pin can be left floating.
UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0, please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX line to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to AT Firmware Download). It is recommended to use the default configuration.
Strapping Pins
At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal function pins.
All the information about strapping pins is covered in ESP32-C2 Series Datasheet > Section Strapping Pins. In this document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO8 and GPIO9 controls the boot mode. See Table Boot Mode Control.
Boot Mode |
GPIO8 |
GPIO9 |
|---|---|---|
Default Config |
– (Floating) |
1 (Pull-up) |
SPI Boot (default) |
Any value |
1 |
Joint Download Boot 1 |
1 |
0 |
Invalid combination 2 |
0 |
0 |
- 1
Joint Download Boot mode supports UART Download Boot download method. In addition to SPI Boot and Joint Download Boot modes, ESP32-C2 also supports SPI Download Boot mode. For details, please see ESP32-C2 Technical Reference Manual > Chapter Chip Boot Control.
- 2
This combination triggers unexpected behavior and should be avoided.
Signals applied to the strapping pins should have specific setup time and hold time. For more information, see Figure Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
Setup and Hold Times for Strapping Pins
Parameter |
Description |
Minimum (ms) |
|---|---|---|
tSU |
Time reserved for the power rails to stabilize before the chip enable pin (CHIP_EN) is pulled high to activate the chip. |
0 |
tH |
Time reserved for the chip to read the strapping pin values after CHIP_EN is already high and before these pins start operating as regular IO pins. |
3 |
Attention
Do not add high-value capacitors at GPIO9, otherwise, the chip may not boot successfully.
GPIO
The pins of ESP32-C2 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configurations, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about IO MUX and GPIO matrix, please refer to ESP32-C2 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available GPIO pins. For details, please refer to ESP32-C2 Series Datasheet > Section Peripheral Pin Configurations.
When using GPIOs, please:
Pay attention to the states of strapping pins during power-up.
Pay attention to the default configurations of the GPIOs after reset. The default configurations can be found in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the high-impedance state or enable the pull-up and pull-down during software initialization to avoid extra power consumption.
Some pins will have glitches during power-up. Refer to Table Power-Up Glitches on Pins for details.
Pin Name |
No. |
Function 0 |
Function 1 |
Function 2 |
Reset |
Notes |
|---|---|---|---|---|---|---|
GPIO0 |
4 |
GPIO0 |
GPIO0 |
— |
0 |
R, G |
GPIO1 |
5 |
GPIO1 |
GPIO1 |
— |
0 |
R, G |
GPIO2 |
6 |
GPIO2 |
GPIO2 |
FSPIQ |
1 |
R |
GPIO3 |
8 |
GPIO3 |
GPIO3 |
— |
1 |
R, G |
MTMS |
9 |
MTMS |
GPIO4 |
FSPIHD |
1 |
R |
MTDI |
10 |
MTDI |
GPIO5 |
FSPIWP |
1 |
R, G |
MTCK |
12 |
MTCK |
GPIO6 |
FSPICLK |
1* |
— |
MTDO |
13 |
MTDO |
GPIO7 |
FSPID |
1 |
— |
GPIO8 |
14 |
GPIO8 |
GPIO8 |
— |
1 |
— |
GPIO9 |
15 |
GPIO9 |
GPIO9 |
— |
3 |
— |
GPIO10 |
16 |
GPIO10 |
GPIO10 |
FSPICS0 |
1 |
— |
GPIO18 |
18 |
GPIO18 |
GPIO18 |
— |
0 |
— |
U0RXD |
19 |
U0RXD |
GPIO19 |
— |
3 |
— |
U0TXD |
20 |
U0TXD |
GPIO20 |
— |
4 |
— |
Reset：
The default configuration of each pin after reset:
0 – input disabled, in high impedance state (IE = 0)
1 – input enabled, in high impedance state (IE = 1)
2 – input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
3 – input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
4 – output enabled, pull-up resistor enabled (OE = 1, WPU = 1)
1* – When the value of eFuse bit EFUSE_DIS_PAD_JTAG is
0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
1, input enabled, in high impedance state (IE = 1)
Notes：
R – These pins have analog functions.
G – These pins have glitches during power-up. See details in Power-Up Glitches on Pins.
Pin |
Glitch 3 |
Typical Time (µs) |
|---|---|---|
GPIO0 |
Low-level glitch |
40 |
GPIO1 |
Low-level glitch |
60 |
GPIO3 |
Low-level glitch |
60 |
MTDI |
Low-level glitch |
60 |
- 3
Low-level glitch: the pin is at a low level output status during the time period;
ADC
Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher accuracy, you may implement your own calibration methods.
When ATTEN=0 and the effective measurement range is 0 ~ 950 mV, the total error is ±5 mV.
When ATTEN=3 and the effective measurement range is 0 ~ 2800 mV, the total error is ±10 mV.