PCB Layout Design
This chapter introduces the key points of how to design an ESP32-C5 PCB layout using an ESP32-C5 module (see Figure ESP32-C5 Reference PCB Layout) as an example.
ESP32-C5 Reference PCB Layout
General Principles of PCB Layout for the Chip
It is recommended to use a four-layer PCB design:
Layer 1 (TOP): Signal traces and components.
Layer 2 (GND): No signal traces here to ensure a complete GND plane.
Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces and a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal.
Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on this layer.
Power Supply
Figure ESP32-C5 Power Traces in a Four-layer PCB Design shows the overview of the power traces in a four-layer PCB design.
ESP32-C5 Power Traces in a Four-layer PCB Design
Whenever possible, route the power traces on the inner layers (not the ground layer) and connect them to the chip pins through vias. There should be at least two vias if the main power traces need to cross layers. The drill diameter on other power traces should be no smaller than the width of the power traces.
The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure ESP32-C5 Power Traces in a Four-layer PCB Design. The width of the main power traces should be no less than 35 mil. The width of VDDA6, VDDA7, VDDA1, and VDDA2 at pin1, pin3, pin40, and pin41 power traces should be no less than 20 mil. The recommended width of other power traces is 10 mil. Ensure the power traces are surrounded by ground copper.
The ESD protection diode is placed next to the power port (circled in red in Figure ESP32-C5 Power Traces in a Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the chip. After that, the power traces are divided into several branches using a star-shaped topology, which reduces the coupling between different power pins. Please separate the 2.4 GHz and 5 GHz power traces.
The power supply for pin1, pin3, pin40, and pin41 is RF related, so please place a 10 µF capacitor for each pin.
Add a CLC/LC filter circuit near pins 40 and 41 to suppress high-frequency harmonics. The power trace can be routed at a 45-degree angle to maintain distance from adjacent RF traces. Except for the 10 µF capacitor, it is recommended to use 0201 components. This allows the filter circuit for pins 2 and 3 to be placed closer to the pins, with a GND isolation layer separating them from surrounding RF and GPIO traces, while also maximizing the placement of ground vias. Using 0201 components enables placing a via to the bottom layer at the first capacitor near the chip, while maintaining a keep-out area on other layers, further reducing harmonic interference. See the figure below.
ESP32-C5 Power Traces for Pins 40 and 41
Place appropriate decoupling capacitors at the rest of the power pins. Ground vias should be added close to the capacitor’s ground pad to ensure a short return path.
The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground vias.
The ground pads of the chip and surrounding circuit components should make full contact with the ground copper pour rather than being connected via traces.
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as shown in Figure ESP32-C5 Power Traces in a Four-layer PCB Design. This helps effectively reduce solder leakage issues when soldering the module EPAD to the substrate.
For optimal grounding, connect the EPAD to a large external ground area using wide traces or copper planes. See the figure below.
ESP32-C5 EPAD Design at Chip Bottom
Crystal
Figure ESP32-C5 Crystal Layout (with Keep-out Area on Top Layer) shows a reference PCB layout where the crystal is connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground isolation.
ESP32-C5 Crystal Layout (with Keep-out Area on Top Layer)
If there is sufficient ground on the crystal layer, it is recommended to maintain a keep-out area around the crystal for ground isolation. This helps to reduce the value of parasitic capacitance and suppress temperature conduction, which can otherwise affect the frequency offset. If there is no sufficient ground, do not maintain any keep-out area.
The layout of the crystal should follow the guidelines below:
Ensure a complete GND plane for the RF, crystal, and chip.
The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least 2.4 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The clock traces should not intersect with each other.
Components in series to the crystal trace should be placed close to the chip side.
The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the clock trace, but not connected directly to the series components. This is to make sure the ground pad of the capacitor is close to that of the crystal.
Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by ground copper.
As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interference, for example large inductance component, and ensure that there is a clean large-area ground plane around the crystal.
RF
The RF trace is routed as shown highlighted in pink in Figure ESP32-C5 RF Layout in a Four-layer PCB Design.
ESP32-C5 RF Layout in a Four-layer PCB Design
The RF layout should meet the following guidelines:
A CLC matching circuit should be added to the RF trace. Please use 0201 components and place them close to the pin in a zigzag. In other words, the two capacitors should not be oriented in the same direction to minimize interference.
The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
ESP32-C5 PCB Stack-up Design
In the 5 GHz matching circuit, add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics. It is preferable to keep the stub length 10 mil, and determine the stub width according to the PCB stack-up so that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to the third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure ESP32-C5 Stub in a Four-layer PCB Design is the stub. Note that a stub is not required for package types above 0201.
ESP32-C5 Stub in a Four-layer PCB Design
It is recommended to keep all layers clear under the IPEX antenna connector. See the figure below.
ESP32-C5 IPEX Layout
For PCB antennas, make sure to validate them through both simulation and real-world testing on a development board. It is recommended to include an additional CLC matching circuit for antenna tuning. Place this circuit as close to the antenna as possible.
The RF trace should have a consistent width and not branch out. It should be as short as possible with dense ground vias around for interference shielding.
The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should be routed at a 135° angle, or with circular arcs if trace bends are required.
The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace whenever possible.
There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins, etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground copper and ground vias.
Flash and PSRAM
The layout for flash should follow the guidelines below:
Place the zero-ohm resistors in series on the SPI lines close to the chip.
Route the SPI traces on the inner layer (e.g., the third layer) whenever possible, and add ground copper and ground vias around the clock and data traces of SPI separately.
If the flash and PSRAM are located far from the chip, it is recommended to place appropriate decoupling capacitors both at VDD_SPI and near the flash and PSRAM.
Figure ESP32-C5 Quad SPI Flash Layout shows the quad SPI flash layout.
ESP32-C5 Quad SPI Flash Layout
UART
Figure ESP32-C5 UART Layout shows the UART layout.
ESP32-C5 UART Layout
The UART layout should meet the following guidelines:
The series resistor on the U0TXD trace needs to be placed close to the chip side and away from the crystal.
The U0TXD and U0RXD traces on the top layer should be as short as possible.
The UART trace should be surrounded by ground copper and ground vias stitching.
General Principles of PCB Layout for Modules (Positioning a Module on a Base Board)
If module-on-board design is adopted, attention should be paid while positioning the module on the base board. The interference of the baseboard on the module’s antenna performance should be minimized.
It is suggested to place the module’s on-board PCB antenna outside the base board, and the GND point of the antenna closest to the board. In the following example figures, positions with mark ✓ are strongly recommended, while positions without a mark are not recommended.
Placement of ESP32-C5 Modules on Base Board (antenna GND point on the right)
If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna area (no copper, routing, or components on it), and place the GND point of the antenna closest to the board. If there is a base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna. Figure Keepout Zone for ESP32-C5 Module’s Antenna on the Base Board shows the suggested clearance for modules whose antenna GND point is on the right.
Keepout Zone for ESP32-C5 Module’s Antenna on the Base Board
When designing an end product, attention should be paid to the interference caused by the housing of the antenna and it is recommended to carry out RF verification. It is necessary to test the throughput and communication signal range of the whole product to ensure the product’s actual RF performance.
USB
The USB layout should meet the following guidelines:
Place the RC circuit on the USB traces close to the chip side.
Use differential pairs and route them in parallel at equal lengths.
Make sure there is a complete reference ground plane and surround the USB traces with ground copper.
SDIO
The SDIO layout should follow the guidelines below:
Minimize parasitic capacitance of SDIO traces as they involve high-speed signals.
The trace lengths for SDIO_CMD and SDIO_DATA0 ~ SDIO_DATA3 should be within ± 3 mil of the SDIO_CLK trace length. Use serpentine routing if necessary.
It is recommended to surround the SDIO_CLK trace with ground copper. Keep the total trace length from SDIO GPIOs to the master SDIO interface as short as possible, ideally within 2000 mil, and no more than 2500 mil.
Ensure that SDIO traces do not cross layers.
Note
This peripheral is supported by the chip revision v1.0, but not by v0.1.
Typical Layout Problems and Solutions
When ESP32-C5 sends data packages, the voltage ripple is small, but RF TX performance is poor.
Analysis: The RF TX performance can be affected not only by voltage ripples, but also by the crystal itself. Poor quality and big frequency offsets of the crystal decrease the RF TX performance. The crystal clock may be corrupted by other interfering signals, such as high-speed output or input signals. In addition, high-frequency signal traces, such as the SDIO traces and UART traces under the crystal, could also result in the malfunction of the crystal. Besides, sensitive components or radiating components, such as inductors and antennas, may also decrease the RF performance.
Solution: This problem is caused by improper layout for the crystal and can be solved by re-layout. Please refer to Section Crystal for details.
When ESP32-C5 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor.
Analysis: The disparity between the tested value and the target value may be due to signal reflection caused by the impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance mismatch will affect the working state of the internal PA, making the PA prematurely access the saturated region in an abnormal way. The EVM becomes poor as the signal distortion happens.
Solution: Match the antenna’s impedance with the π-type circuit on the RF trace, so that the impedance of the antenna as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.
TX performance is not bad, but the RX sensitivity is low.
Analysis: Good TX performance indicates proper RF impedance matching. Poor RX sensitivity may result from external coupling to the antenna. For instance, the crystal signal harmonics could couple to the antenna. If the TX and RX traces of UART cross over with RF trace, they will affect the RX performance, as well. If there are many high-frequency interference sources on the board, signal integrity should be considered.
Solution: Keep the antenna away from crystals. Do not route high-frequency signal traces close to the RF trace. Please refer to Section RF for details.