SoC Capabilities
This section lists the macro definitions of the ESP32-C2's SoC hardware capabilities. These macros are commonly used by conditional-compilation directives (e.g., #if
) in ESP-IDF to determine which hardware-dependent features are supported, thus control what portions of code are compiled.
Warning
These macro definitions are currently not considered to be part of the public API, and may be changed in a breaking manner (see ESP-IDF Versions for more details).
API Reference
Header File
This header file can be included with:
#include "soc/soc_caps.h"
Macros
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SOC_ADC_SUPPORTED
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SOC_DEDICATED_GPIO_SUPPORTED
-
SOC_UART_SUPPORTED
-
SOC_GDMA_SUPPORTED
-
SOC_AHB_GDMA_SUPPORTED
-
SOC_GPTIMER_SUPPORTED
-
SOC_PHY_SUPPORTED
-
SOC_BT_SUPPORTED
-
SOC_WIFI_SUPPORTED
-
SOC_ASYNC_MEMCPY_SUPPORTED
-
SOC_SUPPORTS_SECURE_DL_MODE
-
SOC_EFUSE_KEY_PURPOSE_FIELD
-
SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
-
SOC_EFUSE_SUPPORTED
-
SOC_TEMP_SENSOR_SUPPORTED
-
SOC_LEDC_SUPPORTED
-
SOC_I2C_SUPPORTED
-
SOC_GPSPI_SUPPORTED
-
SOC_SHA_SUPPORTED
-
SOC_ECC_SUPPORTED
-
SOC_FLASH_ENC_SUPPORTED
-
SOC_SECURE_BOOT_SUPPORTED
-
SOC_SYSTIMER_SUPPORTED
-
SOC_BOD_SUPPORTED
-
SOC_CLK_TREE_SUPPORTED
-
SOC_ASSIST_DEBUG_SUPPORTED
-
SOC_WDT_SUPPORTED
-
SOC_SPI_FLASH_SUPPORTED
-
SOC_RNG_SUPPORTED
-
SOC_LIGHT_SLEEP_SUPPORTED
-
SOC_DEEP_SLEEP_SUPPORTED
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SOC_LP_PERIPH_SHARE_INTERRUPT
-
SOC_PM_SUPPORTED
-
SOC_XTAL_SUPPORT_26M
-
SOC_XTAL_SUPPORT_40M
-
SOC_ADC_DIG_CTRL_SUPPORTED
< SAR ADC Module
-
SOC_ADC_DIG_IIR_FILTER_SUPPORTED
-
SOC_ADC_MONITOR_SUPPORTED
-
SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)
-
SOC_ADC_PERIPH_NUM
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SOC_ADC_CHANNEL_NUM(PERIPH_NUM)
-
SOC_ADC_MAX_CHANNEL_NUM
-
SOC_ADC_ATTEN_NUM
Digital
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SOC_ADC_DIGI_CONTROLLER_NUM
-
SOC_ADC_PATT_LEN_MAX
One pattern table, each contains 8 items. Each item takes 1 byte
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SOC_ADC_DIGI_MIN_BITWIDTH
-
SOC_ADC_DIGI_MAX_BITWIDTH
-
SOC_ADC_DIGI_IIR_FILTER_NUM
-
SOC_ADC_DIGI_MONITOR_NUM
F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095
-
SOC_ADC_SAMPLE_FREQ_THRES_HIGH
-
SOC_ADC_SAMPLE_FREQ_THRES_LOW
RTC
-
SOC_ADC_RTC_MIN_BITWIDTH
-
SOC_ADC_RTC_MAX_BITWIDTH
Calibration
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SOC_ADC_CALIBRATION_V1_SUPPORTED
support HW offset calibration version 1
-
SOC_ADC_SELF_HW_CALI_SUPPORTED
support HW offset self calibration ADC power control is shared by PWDET, TempSensor
-
SOC_ADC_SHARED_POWER
-
SOC_BROWNOUT_RESET_SUPPORTED
-
SOC_SHARED_IDCACHE_SUPPORTED
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SOC_CPU_CORES_NUM
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SOC_CPU_INTR_NUM
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SOC_CPU_HAS_FLEXIBLE_INTC
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SOC_CPU_HAS_CSR_PC
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SOC_CPU_BREAKPOINTS_NUM
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SOC_CPU_WATCHPOINTS_NUM
-
SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
-
SOC_CPU_IDRAM_SPLIT_USING_PMP
-
SOC_ECC_SUPPORT_POINT_VERIFY_QUIRK
-
SOC_AHB_GDMA_VERSION
-
SOC_GDMA_NUM_GROUPS_MAX
-
SOC_GDMA_PAIRS_PER_GROUP_MAX
-
SOC_GPIO_PORT
-
SOC_GPIO_PIN_COUNT
-
SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
-
SOC_GPIO_FILTER_CLK_SUPPORT_APB
-
SOC_GPIO_SUPPORT_FORCE_HOLD
-
SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
-
SOC_GPIO_VALID_GPIO_MASK
-
SOC_GPIO_VALID_OUTPUT_GPIO_MASK
-
SOC_GPIO_IN_RANGE_MAX
-
SOC_GPIO_OUT_RANGE_MAX
-
SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
-
SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
-
SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
-
SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
-
SOC_GPIO_CLOCKOUT_CHANNEL_NUM
-
SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-
SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
8 outward channels on each CPU core
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SOC_DEDIC_GPIO_IN_CHANNELS_NUM
8 inward channels on each CPU core
-
SOC_DEDIC_PERIPH_ALWAYS_ENABLE
The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled
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SOC_I2C_NUM
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SOC_HP_I2C_NUM
-
SOC_I2C_FIFO_LEN
I2C hardware FIFO depth
-
SOC_I2C_CMD_REG_NUM
Number of I2C command registers
-
SOC_I2C_SUPPORT_HW_CLR_BUS
-
SOC_I2C_SUPPORT_XTAL
-
SOC_I2C_SUPPORT_RTC
-
SOC_I2C_SUPPORT_10BIT_ADDR
-
SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-
SOC_LEDC_SUPPORT_XTAL_CLOCK
-
SOC_LEDC_TIMER_NUM
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SOC_LEDC_CHANNEL_NUM
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SOC_LEDC_TIMER_BIT_WIDTH
-
SOC_LEDC_SUPPORT_FADE_STOP
-
SOC_MMU_PAGE_SIZE_CONFIGURABLE
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SOC_MMU_LINEAR_ADDRESS_REGION_NUM
-
SOC_MMU_PERIPH_NUM
-
SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
-
SOC_MPU_MIN_REGION_SIZE
-
SOC_MPU_REGIONS_MAX_NUM
-
SOC_MPU_REGION_RO_SUPPORTED
-
SOC_MPU_REGION_WO_SUPPORTED
-
SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
-
SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
-
SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN
-
SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE
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SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE
-
SOC_RTCIO_PIN_COUNT
-
SOC_SHA_SUPPORT_RESUME
-
SOC_SHA_SUPPORT_SHA1
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SOC_SHA_SUPPORT_SHA224
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SOC_SHA_SUPPORT_SHA256
-
SOC_SPI_PERIPH_NUM
-
SOC_SPI_PERIPH_CS_NUM(i)
-
SOC_SPI_MAX_CS_NUM
-
SOC_SPI_MAXIMUM_BUFFER_SIZE
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SOC_SPI_SUPPORT_DDRCLK
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SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
-
SOC_SPI_SUPPORT_CD_SIG
-
SOC_SPI_SUPPORT_CONTINUOUS_TRANS
-
SOC_SPI_SUPPORT_SLAVE_HD_VER2
-
SOC_SPI_SUPPORT_CLK_XTAL
-
SOC_SPI_SUPPORT_CLK_PLL_F40M
-
SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
-
SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
-
SOC_SPI_SCT_SUPPORTED
-
SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM)
-
SOC_SPI_SCT_REG_NUM
-
SOC_SPI_SCT_BUFFER_NUM_MAX
-
SOC_SPI_SCT_CONF_BITLEN_MAX
-
SOC_MEMSPI_IS_INDEPENDENT
-
SOC_SPI_MAX_PRE_DIVIDER
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SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
-
SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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SOC_SPI_MEM_SUPPORT_AUTO_RESUME
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SOC_SPI_MEM_SUPPORT_IDLE_INTR
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SOC_SPI_MEM_SUPPORT_SW_SUSPEND
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SOC_SPI_MEM_SUPPORT_CHECK_SUS
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SOC_SPI_MEM_SUPPORT_WRAP
-
SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED
-
SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED
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SOC_SYSTIMER_COUNTER_NUM
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SOC_SYSTIMER_ALARM_NUM
-
SOC_SYSTIMER_BIT_WIDTH_LO
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SOC_SYSTIMER_BIT_WIDTH_HI
-
SOC_SYSTIMER_FIXED_DIVIDER
-
SOC_SYSTIMER_INT_LEVEL
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SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-
SOC_TIMER_GROUPS
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SOC_TIMER_GROUP_TIMERS_PER_GROUP
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SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-
SOC_TIMER_GROUP_SUPPORT_XTAL
-
SOC_TIMER_GROUP_TOTAL_TIMERS
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SOC_MWDT_SUPPORT_XTAL
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SOC_EFUSE_DIS_DOWNLOAD_ICACHE
-
SOC_EFUSE_DIS_PAD_JTAG
-
SOC_EFUSE_DIS_DIRECT_BOOT
-
SOC_SECURE_BOOT_V2_ECC
-
SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
-
SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
-
SOC_FLASH_ENCRYPTION_XTS_AES
-
SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS
-
SOC_FLASH_ENCRYPTION_XTS_AES_128
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SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
-
SOC_UART_NUM
-
SOC_UART_HP_NUM
-
SOC_UART_FIFO_LEN
The UART hardware FIFO length
-
SOC_UART_BITRATE_MAX
Max bit rate supported by UART
-
SOC_UART_SUPPORT_WAKEUP_INT
Support UART wakeup interrupt
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SOC_UART_SUPPORT_PLL_F40M_CLK
Support APB as the clock source
-
SOC_UART_SUPPORT_RTC_CLK
Support RTC clock as the clock source
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SOC_UART_SUPPORT_XTAL_CLK
Support XTAL clock as the clock source
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SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-
SOC_SUPPORT_COEXISTENCE
-
SOC_COEX_HW_PTI
-
SOC_EXTERNAL_COEX_ADVANCE
HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS
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SOC_EXTERNAL_COEX_LEADER_TX_LINE
EXTERNAL COEXISTENCE TX LINE CAPS
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SOC_PHY_DIG_REGS_MEM_SIZE
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SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
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SOC_PM_SUPPORT_WIFI_WAKEUP
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SOC_PM_SUPPORT_BT_WAKEUP
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SOC_PM_SUPPORT_RC_FAST_PD
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SOC_PM_SUPPORT_VDDSDIO_PD
-
SOC_CLK_RC_FAST_D256_SUPPORTED
-
SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
-
SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
-
SOC_CLK_OSC_SLOW_SUPPORTED
ESP32C2 only supports to connect an external oscillator, not a crystal
-
SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
Support XTAL_D2 clock as the LP_FAST clock source
-
SOC_WIFI_HW_TSF
Support hardware TSF
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SOC_WIFI_FTM_SUPPORT
Support FTM
-
SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW
Support delta early time for rf phy on/off
-
SOC_WIFI_PHY_NEEDS_USB_WORKAROUND
SoC has WiFi and USB PHYs interference, needs a workaround
-
SOC_BLE_SUPPORTED
Support Bluetooth Low Energy hardware
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SOC_BLE_MESH_SUPPORTED
Support BLE MESH
-
SOC_ESP_NIMBLE_CONTROLLER
Support BLE EMBEDDED controller V1
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SOC_BLE_50_SUPPORTED
Support Bluetooth 5.0
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SOC_BLE_DEVICE_PRIVACY_SUPPORTED
Support BLE device privacy mode
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SOC_BLUFI_SUPPORTED
Support BLUFI
-
SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED
Support For BLE Periodic Adv Enhancements
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SOC_PHY_IMPROVE_RX_11B
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SOC_PHY_COMBO_MODULE
Support Wi-Fi and BLE