Clock Tree
The clock subsystem of ESP32-S3 is used to source and distribute system/module clocks from a range of root clocks. The clock tree driver maintains the basic functionality of the system clock and the intricate relationship among module clocks.
This document starts with the introduction to root and module clocks. Then it covers the clock tree APIs that can be called to monitor the status of the module clocks at runtime.
Introduction
This section lists definitions of ESP32-S3's supported root clocks and module clocks. These definitions are commonly used in the driver configuration, to help select a proper source clock for the peripheral.
Root Clocks
Root clocks generate reliable clock signals. These clock signals then pass through various gates, muxes, dividers, or multipliers to become the clock sources for every functional module: the CPU core(s), Wi-Fi, Bluetooth, the RTC, and the peripherals.
ESP32-S3's root clocks are listed in soc_root_clk_t
:
Internal 17.5 MHz RC Oscillator (RC_FAST)
This RC oscillator generates a about 17.5 MHz clock signal output as the
RC_FAST_CLK
.The about 17.5 MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a
RC_FAST_D256_CLK
.The exact frequency of
RC_FAST_CLK
can be computed in runtime through calibration on theRC_FAST_D256_CLK
.External 40 MHz Crystal (XTAL)
Internal 136 kHz RC Oscillator (RC_SLOW)
This RC oscillator generates a about 136kHz clock signal output as the
RC_SLOW_CLK
. The exact frequency of this clock can be computed in runtime through calibration.
External 32 kHz Crystal - optional (XTAL32K)
The clock source for this
XTAL32K_CLK
can be either a 32 kHz crystal connecting to theXTAL_32K_P
andXTAL_32K_N
pins or a 32 kHz clock signal generated by an external circuit. The external signal must be connected to theXTAL_32K_P
pin.
XTAL32K_CLK
can also be calibrated to get its exact frequency.
Typically, the frequency of the signal generated from an RC oscillator circuit is less accurate and more sensitive to the environment compared to the signal generated from a crystal. ESP32-S3 provides several clock source options for the RTC_SLOW_CLK
, and it is possible to make the choice based on the requirements for system time accuracy and power consumption. For more details, please refer to RTC Timer Clock Sources.
Module Clocks
ESP32-S3's available module clocks are listed in soc_module_clk_t
. Each module clock has a unique ID. You can get more information on each clock by checking the documented enum value.
API Usage
The clock tree driver provides an all-in-one API to get the frequency of the module clocks, esp_clk_tree_src_get_freq_hz()
. This function allows you to obtain the clock frequency at any time by providing the clock name soc_module_clk_t
and specifying the desired precision level for the returned frequency value esp_clk_tree_src_freq_precision_t
.
API Reference
Header File
This header file can be included with:
#include "soc/clk_tree_defs.h"
Macros
-
SOC_CLK_RC_FAST_FREQ_APPROX
Approximate RC_FAST_CLK frequency in Hz
-
SOC_CLK_RC_SLOW_FREQ_APPROX
Approximate RC_SLOW_CLK frequency in Hz
-
SOC_CLK_RC_FAST_D256_FREQ_APPROX
Approximate RC_FAST_D256_CLK frequency in Hz
-
SOC_CLK_XTAL32K_FREQ_APPROX
Approximate XTAL32K_CLK frequency in Hz
-
SOC_GPTIMER_CLKS
Array initializer for all supported clock sources of GPTimer.
The following code can be used to iterate all possible clocks:
soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; // Test GPTimer with the clock `clk` }
-
SOC_LCD_CLKS
Array initializer for all supported clock sources of LCD.
-
SOC_RMT_CLKS
Array initializer for all supported clock sources of RMT.
-
SOC_TEMP_SENSOR_CLKS
Array initializer for all supported clock sources of Temperature Sensor.
-
SOC_UART_CLKS
Array initializer for all supported clock sources of UART.
-
SOC_MCPWM_TIMER_CLKS
Array initializer for all supported clock sources of MCPWM Timer.
-
SOC_MCPWM_CAPTURE_CLKS
Array initializer for all supported clock sources of MCPWM Capture Timer.
-
SOC_MCPWM_CARRIER_CLKS
Array initializer for all supported clock sources of MCPWM Carrier.
-
SOC_I2S_CLKS
Array initializer for all supported clock sources of I2S.
-
SOC_I2C_CLKS
Array initializer for all supported clock sources of I2C.
-
SOC_SPI_CLKS
Array initializer for all supported clock sources of SPI.
-
SOC_SDM_CLKS
Array initializer for all supported clock sources of SDM.
-
SOC_GLITCH_FILTER_CLKS
Array initializer for all supported clock sources of Glitch Filter.
-
SOC_TWAI_CLKS
Array initializer for all supported clock sources of TWAI.
-
SOC_ADC_DIGI_CLKS
Array initializer for all supported clock sources of ADC digital controller.
-
SOC_ADC_RTC_CLKS
Array initializer for all supported clock sources of ADC RTC controller.
-
SOC_MWDT_CLKS
Array initializer for all supported clock sources of MWDT.
-
SOC_LEDC_CLKS
Array initializer for all supported clock sources of LEDC.
-
SOC_SDMMC_CLKS
Array initializer for all supported clock sources of SDMMC.
Enumerations
-
enum soc_root_clk_t
Root clock.
Values:
-
enumerator SOC_ROOT_CLK_INT_RC_FAST
Internal 17.5MHz RC oscillator
-
enumerator SOC_ROOT_CLK_INT_RC_SLOW
Internal 136kHz RC oscillator
-
enumerator SOC_ROOT_CLK_EXT_XTAL
External 40MHz crystal
-
enumerator SOC_ROOT_CLK_EXT_XTAL32K
External 32kHz crystal/clock signal
-
enumerator SOC_ROOT_CLK_INT_RC_FAST
-
enum soc_cpu_clk_src_t
CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK.
Note
Enum values are matched with the register field values on purpose
Values:
-
enumerator SOC_CPU_CLK_SRC_XTAL
Select XTAL_CLK as CPU_CLK source
-
enumerator SOC_CPU_CLK_SRC_PLL
Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz)
-
enumerator SOC_CPU_CLK_SRC_RC_FAST
Select RC_FAST_CLK as CPU_CLK source
-
enumerator SOC_CPU_CLK_SRC_INVALID
Invalid CPU_CLK source
-
enumerator SOC_CPU_CLK_SRC_XTAL
-
enum soc_rtc_slow_clk_src_t
RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK.
Note
Enum values are matched with the register field values on purpose
Values:
-
enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW
Select RC_SLOW_CLK as RTC_SLOW_CLK source
-
enumerator SOC_RTC_SLOW_CLK_SRC_XTAL32K
Select XTAL32K_CLK as RTC_SLOW_CLK source
-
enumerator SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256
Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source
-
enumerator SOC_RTC_SLOW_CLK_SRC_INVALID
Invalid RTC_SLOW_CLK source
-
enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW
-
enum soc_rtc_fast_clk_src_t
RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK.
Note
Enum values are matched with the register field values on purpose
Values:
-
enumerator SOC_RTC_FAST_CLK_SRC_XTAL_D2
Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source
-
enumerator SOC_RTC_FAST_CLK_SRC_XTAL_DIV
Alias name for
SOC_RTC_FAST_CLK_SRC_XTAL_D2
-
enumerator SOC_RTC_FAST_CLK_SRC_RC_FAST
Select RC_FAST_CLK as RTC_FAST_CLK source
-
enumerator SOC_RTC_FAST_CLK_SRC_INVALID
Invalid RTC_FAST_CLK source
-
enumerator SOC_RTC_FAST_CLK_SRC_XTAL_D2
-
enum soc_module_clk_t
Supported clock sources for modules (CPU, peripherals, RTC, etc.)
Note
enum starts from 1, to save 0 for special purpose
Values:
-
enumerator SOC_MOD_CLK_CPU
CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t
-
enumerator SOC_MOD_CLK_RTC_FAST
RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t
-
enumerator SOC_MOD_CLK_RTC_SLOW
RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t
-
enumerator SOC_MOD_CLK_APB
APB_CLK is highly dependent on the CPU_CLK source
-
enumerator SOC_MOD_CLK_PLL_F80M
PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz
-
enumerator SOC_MOD_CLK_PLL_F160M
PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz
-
enumerator SOC_MOD_CLK_PLL_D2
PLL_D2_CLK is derived from PLL, it has a fixed divider of 2
-
enumerator SOC_MOD_CLK_XTAL32K
XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals
-
enumerator SOC_MOD_CLK_RC_FAST
RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals
-
enumerator SOC_MOD_CLK_RC_FAST_D256
RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals
-
enumerator SOC_MOD_CLK_XTAL
XTAL_CLK comes from the external 40MHz crystal
-
enumerator SOC_MOD_CLK_TEMP_SENSOR
TEMP_SENSOR_CLK comes directly from the internal 20MHz rc oscillator
-
enumerator SOC_MOD_CLK_INVALID
Indication of the end of the available module clock sources
-
enumerator SOC_MOD_CLK_CPU
-
enum soc_periph_systimer_clk_src_t
Type of SYSTIMER clock source.
Values:
-
enumerator SYSTIMER_CLK_SRC_XTAL
SYSTIMER source clock is XTAL
-
enumerator SYSTIMER_CLK_SRC_DEFAULT
SYSTIMER source clock default choice is XTAL
-
enumerator SYSTIMER_CLK_SRC_XTAL
-
enum soc_periph_gptimer_clk_src_t
Type of GPTimer clock source.
Values:
-
enumerator GPTIMER_CLK_SRC_APB
Select APB as the source clock
-
enumerator GPTIMER_CLK_SRC_XTAL
Select XTAL as the source clock
-
enumerator GPTIMER_CLK_SRC_DEFAULT
Select APB as the default choice
-
enumerator GPTIMER_CLK_SRC_APB
-
enum soc_periph_tg_clk_src_legacy_t
Type of Timer Group clock source, reserved for the legacy timer group driver.
Values:
-
enumerator TIMER_SRC_CLK_APB
Timer group source clock is APB
-
enumerator TIMER_SRC_CLK_XTAL
Timer group source clock is XTAL
-
enumerator TIMER_SRC_CLK_DEFAULT
Timer group source clock default choice is APB
-
enumerator TIMER_SRC_CLK_APB
-
enum soc_periph_lcd_clk_src_t
Type of LCD clock source.
Values:
-
enumerator LCD_CLK_SRC_PLL160M
Select PLL_F160M as the source clock
-
enumerator LCD_CLK_SRC_PLL240M
Select PLL_D2 as the source clock
-
enumerator LCD_CLK_SRC_XTAL
Select XTAL as the source clock
-
enumerator LCD_CLK_SRC_DEFAULT
Select PLL_F160M as the default choice
-
enumerator LCD_CLK_SRC_PLL160M
-
enum soc_periph_rmt_clk_src_t
Type of RMT clock source.
Values:
-
enumerator RMT_CLK_SRC_APB
Select APB as the source clock
-
enumerator RMT_CLK_SRC_RC_FAST
Select RC_FAST as the source clock
-
enumerator RMT_CLK_SRC_XTAL
Select XTAL as the source clock
-
enumerator RMT_CLK_SRC_DEFAULT
Select APB as the default choice
-
enumerator RMT_CLK_SRC_APB
-
enum soc_periph_rmt_clk_src_legacy_t
Type of RMT clock source, reserved for the legacy RMT driver.
Values:
-
enumerator RMT_BASECLK_APB
RMT source clock is APB
-
enumerator RMT_BASECLK_XTAL
RMT source clock is XTAL
-
enumerator RMT_BASECLK_DEFAULT
RMT source clock default choice is APB
-
enumerator RMT_BASECLK_APB
-
enum soc_periph_temperature_sensor_clk_src_t
Type of Temp Sensor clock source.
Values:
-
enumerator TEMPERATURE_SENSOR_CLK_SRC_RC_FAST
Select RC_FAST as the source clock
-
enumerator TEMPERATURE_SENSOR_CLK_SRC_DEFAULT
Select RC_FAST as the default choice
-
enumerator TEMPERATURE_SENSOR_CLK_SRC_RC_FAST
-
enum soc_periph_uart_clk_src_legacy_t
Type of UART clock source, reserved for the legacy UART driver.
Values:
-
enumerator UART_SCLK_APB
UART source clock is APB CLK
-
enumerator UART_SCLK_RTC
UART source clock is RC_FAST
-
enumerator UART_SCLK_XTAL
UART source clock is XTAL
-
enumerator UART_SCLK_DEFAULT
UART source clock default choice is APB
-
enumerator UART_SCLK_APB
-
enum soc_periph_mcpwm_timer_clk_src_t
Type of MCPWM timer clock source.
Values:
-
enumerator MCPWM_TIMER_CLK_SRC_PLL160M
Select PLL_F160M as the source clock
-
enumerator MCPWM_TIMER_CLK_SRC_DEFAULT
Select PLL_F160M as the default clock choice
-
enumerator MCPWM_TIMER_CLK_SRC_PLL160M
-
enum soc_periph_mcpwm_capture_clk_src_t
Type of MCPWM capture clock source.
Values:
-
enumerator MCPWM_CAPTURE_CLK_SRC_APB
Select APB as the source clock
-
enumerator MCPWM_CAPTURE_CLK_SRC_DEFAULT
Select APB as the default clock choice
-
enumerator MCPWM_CAPTURE_CLK_SRC_APB
-
enum soc_periph_mcpwm_carrier_clk_src_t
Type of MCPWM carrier clock source.
Values:
-
enumerator MCPWM_CARRIER_CLK_SRC_PLL160M
Select PLL_F160M as the source clock
-
enumerator MCPWM_CARRIER_CLK_SRC_DEFAULT
Select PLL_F160M as the default clock choice
-
enumerator MCPWM_CARRIER_CLK_SRC_PLL160M
-
enum soc_periph_i2s_clk_src_t
I2S clock source enum.
Values:
-
enumerator I2S_CLK_SRC_DEFAULT
Select PLL_F160M as the default source clock
-
enumerator I2S_CLK_SRC_PLL_160M
Select PLL_F160M as the source clock
-
enumerator I2S_CLK_SRC_XTAL
Select XTAL as the source clock
-
enumerator I2S_CLK_SRC_EXTERNAL
Select external clock as source clock
-
enumerator I2S_CLK_SRC_DEFAULT
-
enum soc_periph_i2c_clk_src_t
Type of I2C clock source.
Values:
-
enumerator I2C_CLK_SRC_XTAL
-
enumerator I2C_CLK_SRC_RC_FAST
-
enumerator I2C_CLK_SRC_DEFAULT
-
enumerator I2C_CLK_SRC_XTAL
-
enum soc_periph_spi_clk_src_t
Type of SPI clock source.
Values:
-
enumerator SPI_CLK_SRC_DEFAULT
Select APB as SPI source clock
-
enumerator SPI_CLK_SRC_APB
Select APB as SPI source clock
-
enumerator SPI_CLK_SRC_XTAL
Select XTAL as SPI source clock
-
enumerator SPI_CLK_SRC_DEFAULT
-
enum soc_periph_sdm_clk_src_t
Sigma Delta Modulator clock source.
Values:
-
enumerator SDM_CLK_SRC_APB
Select APB as the source clock
-
enumerator SDM_CLK_SRC_DEFAULT
Select APB as the default clock choice
-
enumerator SDM_CLK_SRC_APB
-
enum soc_periph_glitch_filter_clk_src_t
Glitch filter clock source.
Values:
-
enumerator GLITCH_FILTER_CLK_SRC_APB
Select APB clock as the source clock
-
enumerator GLITCH_FILTER_CLK_SRC_DEFAULT
Select APB clock as the default clock choice
-
enumerator GLITCH_FILTER_CLK_SRC_APB
-
enum soc_periph_twai_clk_src_t
TWAI clock source.
Values:
-
enumerator TWAI_CLK_SRC_APB
Select APB as the source clock
-
enumerator TWAI_CLK_SRC_DEFAULT
Select APB as the default clock choice
-
enumerator TWAI_CLK_SRC_APB
-
enum soc_periph_adc_digi_clk_src_t
ADC digital controller clock source.
Values:
-
enumerator ADC_DIGI_CLK_SRC_APB
Select APB as the source clock
-
enumerator ADC_DIGI_CLK_SRC_PLL_F240M
Select PLL_D2 (default value PLL_F240M) as the source clock
-
enumerator ADC_DIGI_CLK_SRC_DEFAULT
Select APB as the default clock choice
-
enumerator ADC_DIGI_CLK_SRC_APB
-
enum soc_periph_adc_rtc_clk_src_t
ADC RTC controller clock source.
Values:
-
enumerator ADC_RTC_CLK_SRC_RC_FAST
Select RC_FAST as the source clock
-
enumerator ADC_RTC_CLK_SRC_DEFAULT
Select RC_FAST as the default clock choice
-
enumerator ADC_RTC_CLK_SRC_RC_FAST
-
enum soc_periph_mwdt_clk_src_t
MWDT clock source.
Values:
-
enumerator MWDT_CLK_SRC_APB
Select APB as the source clock
-
enumerator MWDT_CLK_SRC_DEFAULT
Select APB as the default clock choice
-
enumerator MWDT_CLK_SRC_APB
-
enum soc_periph_ledc_clk_src_legacy_t
Type of LEDC clock source, reserved for the legacy LEDC driver.
Values:
-
enumerator LEDC_AUTO_CLK
LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer
-
enumerator LEDC_USE_APB_CLK
Select APB as the source clock
-
enumerator LEDC_USE_RC_FAST_CLK
Select RC_FAST as the source clock
-
enumerator LEDC_USE_XTAL_CLK
Select XTAL as the source clock
-
enumerator LEDC_USE_RTC8M_CLK
Alias of 'LEDC_USE_RC_FAST_CLK'
-
enumerator LEDC_AUTO_CLK
-
enum soc_periph_sdmmc_clk_src_t
Type of SDMMC clock source.
Values:
-
enumerator SDMMC_CLK_SRC_DEFAULT
Select PLL_160M as the default choice
-
enumerator SDMMC_CLK_SRC_PLL160M
Select PLL_160M as the source clock
-
enumerator SDMMC_CLK_SRC_XTAL
Select XTAL as the source clock
-
enumerator SDMMC_CLK_SRC_DEFAULT
-
enum soc_clkout_sig_id_t
Values:
-
enumerator CLKOUT_SIG_PLL
PLL_CLK is the output of crystal oscillator frequency multiplier
-
enumerator CLKOUT_SIG_RC_SLOW
RC slow clock, depends on the RTC_CLK_SRC configuration
-
enumerator CLKOUT_SIG_XTAL
Main crystal oscillator clock
-
enumerator CLKOUT_SIG_PLL_F80M
From PLL, usually be 80MHz
-
enumerator CLKOUT_SIG_RC_FAST
RC fast clock, about 17.5MHz
-
enumerator CLKOUT_SIG_INVALID
-
enumerator CLKOUT_SIG_PLL
Header File
This header file can be included with:
#include "esp_clk_tree.h"
Functions
-
esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value)
Get frequency of module clock source.
- Parameters
clk_src -- [in] Clock source available to modules, in soc_module_clk_t
precision -- [in] Degree of precision, one of esp_clk_tree_src_freq_precision_t values This arg only applies to the clock sources that their frequencies can vary: SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256, SOC_MOD_CLK_XTAL32K For other clock sources, this field is ignored.
freq_value -- [out] Frequency of the clock source, in Hz
- Returns
ESP_OK Success
ESP_ERR_INVALID_ARG Parameter error
ESP_FAIL Calibration failed
Enumerations
-
enum esp_clk_tree_src_freq_precision_t
Degree of precision of frequency value to be returned by esp_clk_tree_src_get_freq_hz()
Values:
-
enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED
-
enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX
-
enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT
-
enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID
-
enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED