ESP32 Series SoC Errata
[中文]
Date
Version
Release Notes
2024-07-29
v2.8
Added Section [Clock] ESP32 cannot be used as the PHY clock source if Wi-Fi and Ethernet are used at the same time
2023-09-19
v2.7
Added Sections [RTC] RTC Register Read Error After Wake-up from Light-sleep Mode and [CPU] When a CPU is interrupted while accessing five specific FIFO registers, subsequent CPU accesses will get halted
Updated Sections [GPIO] Within the same group of GPIO pins, edge interrupts cannot be used together with other interrupts and [UART] UART fifo_cnt does not indicate the data length in FIFO correctly
2023-02-02
v2.6
Removed hall sensor from Section [GPIO] When certain RTC peripherals are powered on, the inputs of GPIO36 and GPIO39 will be pulled down for approximately 80 ns according to PCN
2022-11-23
v2.5
Added register GPIO_OUT_W1TS_REG in Section [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost
2022-10-13
v2.4
Added chip revision v3.1 and v1.1
Added Sections [TWAI] When the RX FIFO overruns with 64 or more messages, the RX FIFO becomes unrecoverable and [ULP] ULP coprocessor and touch sensors can not be used during Deep-sleep when RTC_PERIPH power domain is up
Renamed this document as “ESP32 Series SoC Errata”
2020-09-25
v2.3
Updated Section [CPU] There are limitations to the CPU access to 0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF address spaces and provided more information about UART FIFO read operation
2020-06-08
v2.2
Added Sections [UART] UART fifo_cnt does not indicate the data length in FIFO correctly and [CPU] CPU has limitations when accessing peripherals in chips
2020-05-14
v2.1
Added a note of fix in Section [Reset] Due to the flash start-up time, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deepsleep
2020-05-08
v2.0
Added Sections [Watchdog] ESP32 chip may have a live lock under certain conditions that will cause interrupt watchdog issue and [CPU] There are limitations to the CPU access to 0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF address spaces
Added a note in Section [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost
Updated the address ranges of space A and B in Section [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur and fixed a typo
2020-03-16
v1.9
Added chip revision 3 in Table Chip Revision Identification by Chip Marking
Added note of fixes in sections [CPU] When the CPU accesses external SRAM in a certain sequence, read and write errors may occur and [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur
Added Sections [TWAI] A negative phase error where |e| > SJW(N) will cause the remaining transmitted bits to be left shifted and [GPIO] Within the same group of GPIO pins, edge interrupts cannot be used together with other interrupts
Added documentation feedback link
2018-12
v1.8
Added Section “ESP32 TWAI Errata”
2018-05
v1.7
Added Section [LEDC] When the LEDC is in decremental fade mode, a duty overflow error may occur
v1.6
Overall update
2018-02
v1.5
Added Section [GPIO] When certain RTC peripherals are powered on, the inputs of GPIO36 and GPIO39 will be pulled down for approximately 80 ns
v1.4
Corrected typos in the register names in Section [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost
2017-06
v1.3
Added Sections [CPU] When the CPU accesses external SRAM in a certain sequence, read and write errors may occur and [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur
2017-04
v1.2
Changed the description of Section [Reset] A spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deep-sleep
Added Section [Reset] Due to the flash start-up time, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deepsleep
2016-12
v1.1
Modified the MEMW command in Section [CPU] When the CPU accesses external SRAM through cache, under certain conditions read and write errors occur
2016-11
v1.0
First release