ESP32 Series SoC Errata
Resources and Legal Notices
[中文]
Date
Version
Release Notes
2025-10-11
v3.0
Update errata titles capitalization and errata numbering
2025-01-03
v2.9
Updated Section [ULP-3.19] ULP Coprocessor And Touch Sensors Can Not Be Used In Deep-sleep Mode If RTC_PERIPH Power Domain Is Powered Up
2024-07-29
v2.8
Added Section [CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time
2023-09-19
v2.7
Added Sections [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode and [CPU-3.21] When a CPU Is Interrupted While Accessing Five Specific Fifo Registers, Subsequent CPU Accesses Will Get Halted
Updated Sections [GPIO-3.14] Within the Same Group of GPIO Pins, Edge Interrupts Cannot Be Used Together With Other Interrupts and [UART-3.17] UART fifo_cnt Does Not Indicate the Data Length In Fifo Correctly
2023-02-02
v2.6
Removed hall sensor from Section [GPIO-3.11] When Certain Rtc Peripherals Are Powered on, the Inputs of GPIO36 and GPIO39 Will Be Pulled Down for Approximately 80 ns according to PCN
2022-11-23
v2.5
Added register GPIO_OUT_W1TS_REG in Section [CPU-3.3] When the CPU Accesses Peripherals and Writes a Single Address Repeatedly, Some Writes May Be Lost
2022-10-13
v2.4
Added chip revision v3.1 and v1.1
Added Sections [TWAI-3.13.11] When the RX Fifo Overruns With 64 or More Messages, the RX Fifo Becomes Unrecoverable and [ULP-3.19] ULP Coprocessor And Touch Sensors Can Not Be Used In Deep-sleep Mode If RTC_PERIPH Power Domain Is Powered Up
Renamed this document as “ESP32 Series SoC Errata”
2020-09-25
v2.3
Updated Section [CPU-3.16] There Are Limitations to the CPU Access to 0x3ff0_0000 ~ 0x3ff1_efff and 0x3ff4_0000 ~ 0x3ff7_ffff Address Spaces and provided more information about UART FIFO read operation
2020-06-08
v2.2
Added Sections [UART-3.17] UART fifo_cnt Does Not Indicate the Data Length In Fifo Correctly and [CPU-3.18] CPU Has Limitations When Accessing Peripherals in Chips
2020-05-14
v2.1
Added a note of fix in Section [RES-3.8] Due to the Flash Start-up Time, a Spurious Watchdog Reset Occurs When ESP32 Is Powered up or Wakes up From Deepsleep
2020-05-08
v2.0
Added Sections [WDT-3.15] {idf_target_name} Chip May Have A Live Lock Under Certain Conditions That Will Cause Interrupt Watchdog Issue and [CPU-3.16] There Are Limitations to the CPU Access to 0x3ff0_0000 ~ 0x3ff1_efff and 0x3ff4_0000 ~ 0x3ff7_ffff Address Spaces
Added a note in Section [CPU-3.3] When the CPU Accesses Peripherals and Writes a Single Address Repeatedly, Some Writes May Be Lost
Updated the address ranges of space A and B in Section [CPU-3.10] When Each CPU Reads Certain Different Address Spaces Simultaneously, a Read Error May Occur and fixed a typo
2020-03-16
v1.9
Added chip revision 3 in Table Chip Revision Identification by Chip Marking
Added note of fixes in sections [CPU-3.9] When the CPU Accesses External Sram in a Certain Sequence, Read and Write Errors May Occur and [CPU-3.10] When Each CPU Reads Certain Different Address Spaces Simultaneously, a Read Error May Occur
Added Sections [TWAI-3.13.10] A Negative Phase Error Where |e| > SJW (N) Will Cause the Remaining Transmitted Bits to Be Left Shifted and [GPIO-3.14] Within the Same Group of GPIO Pins, Edge Interrupts Cannot Be Used Together With Other Interrupts
Added documentation feedback link
2018-12
v1.8
Added Section “ESP32 TWAI Errata”
2018-05
v1.7
Added Section [LEDC-3.12] When the LEDC Is in Decremental Fade Mode, a Duty Overflow Error May Occur
v1.6
Overall update
2018-02
v1.5
Added Section [GPIO-3.11] When Certain Rtc Peripherals Are Powered on, the Inputs of GPIO36 and GPIO39 Will Be Pulled Down for Approximately 80 ns
v1.4
Corrected typos in the register names in Section [CPU-3.3] When the CPU Accesses Peripherals and Writes a Single Address Repeatedly, Some Writes May Be Lost
2017-06
v1.3
Added Sections [CPU-3.9] When the CPU Accesses External Sram in a Certain Sequence, Read and Write Errors May Occur and [CPU-3.10] When Each CPU Reads Certain Different Address Spaces Simultaneously, a Read Error May Occur
2017-04
v1.2
Changed the description of Section [RES-3.1] A Spurious Watchdog Reset Occurs When ESP32 Is Powered up or Wakes up From Deep-sleep
Added Section [RES-3.8] Due to the Flash Start-up Time, a Spurious Watchdog Reset Occurs When ESP32 Is Powered up or Wakes up From Deepsleep
2016-12
v1.1
Modified the MEMW command in Section [CPU-3.2] When the CPU Accesses External Sram Through Cache, Under Certain Conditions Read and Write Errors Occur
2016-11
v1.0
First release