[CPU] CPU has limitations when accessing peripherals in chips
Description
As described in [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost, [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur, [CPU] There are limitations to the CPU access to 0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF address spaces, CPU has limitations when accessing peripherals in chips of different revisions using 0x3FF0_0000 ~ 0x3FF1_EFFF, 0x3FF4_0000 ~ 0x3FF7_FFFF, and 0x6000_0000 ~ 0x6003_FFFF.
Address space (Bus) |
Register type |
Operation |
Chip Revision |
||||
|---|---|---|---|---|---|---|---|
v0.0 |
v1.0 |
v1.1 |
v3.0 |
v3.1 |
|||
0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF (DPORT) |
Non- FIFO |
Write |
Yes |
Yes |
|||
Read |
No (refer to [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur) |
Yes |
|||||
FIFO |
Write |
No (refer to [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost) |
Yes |
||||
Read |
Yes |
Yes |
|||||
0x6000_0000 ~ 0x6003_FFFF (AHB) |
Non- FIFO |
Write |
Yes |
||||
Read |
Yes |
||||||
FIFO |
Write |
Yes |
|||||
Read |
No (No such feature, unpredictable results) |
||||||
Note
Yes: operation is executed correctly
No: operation fails