Errata Summary

[中文]

Table 4 Errata summary

Category

Descriptions

Affected Revisions

v0.0

v1.0

v1.1

v3.0

v3.1

CPU

[CPU-3.5] The CPU Crashes When the Clock Frequency Switches

Y

[CPU-3.18] CPU Has Limitations When Accessing Peripherals in Chips

Y

Y

Y

Y

Y

[CPU-3.16] There Are Limitations to the CPU Access to 0x3ff0_0000 ~ 0x3ff1_efff and 0x3ff4_0000 ~ 0x3ff7_ffff Address Spaces

Y

Y

Y

Y

Y

[CPU-3.9] When the CPU Accesses External Sram in a Certain Sequence, Read and Write Errors May Occur

Y

Y

[CPU-3.2] When the CPU Accesses External Sram Through Cache, Under Certain Conditions Read and Write Errors Occur

Y

[CPU-3.10] When Each CPU Reads Certain Different Address Spaces Simultaneously, a Read Error May Occur

Y

Y

Y

[CPU-3.21] When a CPU Is Interrupted While Accessing Five Specific Fifo Registers, Subsequent CPU Accesses Will Get Halted

Y

Y

Y

Y

Y

[CPU-3.3] When the CPU Accesses Peripherals and Writes a Single Address Repeatedly, Some Writes May Be Lost

Y

ULP

[ULP-3.19] ULP Coprocessor And Touch Sensors Can Not Be Used In Deep-sleep Mode If RTC_PERIPH Power Domain Is Powered Up

Y

Y

Y

Y

Y

GPIO

[GPIO-3.6] For Pads With Both GPIO and RTC_GPIO Functionality, the GPIO Pull-up and Pull-down Configuration Register Fields Are Nonfunctional

Y

Y

Y

Y

Y

[GPIO-3.14] Within the Same Group of GPIO Pins, Edge Interrupts Cannot Be Used Together With Other Interrupts

Y

Y

Y

Y

Y

[GPIO-3.11] When Certain Rtc Peripherals Are Powered on, the Inputs of GPIO36 and GPIO39 Will Be Pulled Down for Approximately 80 ns

Y

Y

Y

Y

Y

Reset

[RES-3.4] The Brown-out Reset (BOR) Function Does Not Work

Y

[RES-3.1] A Spurious Watchdog Reset Occurs When ESP32 Is Powered up or Wakes up From Deep-sleep

Y

[RES-3.8] Due to the Flash Start-up Time, a Spurious Watchdog Reset Occurs When ESP32 Is Powered up or Wakes up From Deepsleep

Y

Y

Y
Table 5 Errata summary

Category

Descriptions

Affected Revisions

v0.0

v1.0

v1.1

v3.0

v3.1

Clock

[CLK-3.7] Audio Pll Frequency Range Is Limited

Y

[CLK-3.22] ESP32 Cannot Be Used as the PHY Clock Source If Wi-fi and Ethernet Are Used at the Same Time

Y

Y

Y

Y

Y

RTC

[RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode

Y

Y

Y

Y

Y

Watchdog

[WDT-3.15] {idf_target_name} Chip May Have A Live Lock Under Certain Conditions That Will Cause Interrupt Watchdog Issue

Y

Y

UART

[UART-3.17] UART fifo_cnt Does Not Indicate the Data Length In Fifo Correctly

Y

Y

Y

Y

Y

TWAI

[TWAI-3.13.6] After Losing Arbitration, a Dominant Bit on the 3rd Bit of Intermission Is Not Interpreted as an SOF

Y

Y

Y

Y

Y

[TWAI-3.13.3] Message Transmitted After Bus-off Recovery Is Erroneous

Y

Y

Y

Y

Y

[TWAI-3.13.7] When the 8th Bit of the Error Delimiter Is Dominant, the Error Passive State Is Not Entered

Y

Y

Y

Y

Y

[TWAI-3.13.2] Error Status Bit Is Not Frozen During Bus-off Recovery

Y

Y

Y

Y

Y

[TWAI-3.13.5] Receiving an Erroneous Data Frame Can Cause the Data Bytes of the Next Received Data Frame to Be Invalid

Y

Y

Y

Y

Y

[TWAI-3.13.10] A Negative Phase Error Where |e| > SJW (N) Will Cause the Remaining Transmitted Bits to Be Left Shifted

Y

Y

Y

Y

Y

[TWAI-3.13.1] Receive Error Counter (REC) Is Allowed to Change Whilst in Reset Mode or Bus-off Recovery

Y

Y

Y

Y

Y

[TWAI-3.13.11] When the RX Fifo Overruns With 64 or More Messages, the RX Fifo Becomes Unrecoverable

Y

Y

Y

Y

Y

[TWAI-3.13.8] Suspend Transmission Is Included Even After Losing Arbitration

Y

Y

Y

Y

Y

[TWAI-3.13.9] When a Stuff Error Occurs During Arbitration Whilst Being Transmitter, Any Errors in the Subsequent Error/Overload Frame Will Not Increase the TEC

Y

Y

Y

Y

Y

[TWAI-3.13.4] Reading the Interrupt Register May Lead to a Transmit Interrupt Being Lost

Y

Y

Y

Y

Y

LEDC

[LEDC-3.12] When the LEDC Is in Decremental Fade Mode, a Duty Overflow Error May Occur

Y

Y

Y

Y

Y