Clock |
[Clock] Audio PLL frequency range is limited |
Y |
|
|
|
|
[Clock] ESP32 cannot be used as the PHY clock source if Wi-Fi and Ethernet are used at the same time |
Y |
Y |
Y |
Y |
Y |
RTC |
[RTC] RTC Register Read Error After Wake-up from Light-sleep Mode |
Y |
Y |
Y |
Y |
Y |
Watchdog |
[Watchdog] ESP32 chip may have a live lock under certain conditions that will cause interrupt watchdog issue |
|
|
|
Y |
Y |
UART |
[UART] UART fifo_cnt does not indicate the data length in FIFO correctly |
Y |
Y |
Y |
Y |
Y |
TWAI |
[TWAI] After losing arbitration, a dominant bit on the 3rd bit of intermission is not interpreted as an SOF |
Y |
Y |
Y |
Y |
Y |
[TWAI] Message transmitted after bus-off recovery is erroneous |
Y |
Y |
Y |
Y |
Y |
[TWAI] When the 8th bit of the error delimiter is dominant, the error passive state is not entered |
Y |
Y |
Y |
Y |
Y |
[TWAI] Error status bit is not frozen during bus-off recovery |
Y |
Y |
Y |
Y |
Y |
[TWAI] Receiving an erroneous data frame can cause the data bytes of the next received data frame to be invalid |
Y |
Y |
Y |
Y |
Y |
[TWAI] A negative phase error where |e| > SJW(N) will cause the remaining transmitted bits to be left shifted |
Y |
Y |
Y |
Y |
Y |
[TWAI] Receive Error Counter (REC) is allowed to change whilst in reset mode or bus-off recovery |
Y |
Y |
Y |
Y |
Y |
[TWAI] When the RX FIFO overruns with 64 or more messages, the RX FIFO becomes unrecoverable |
Y |
Y |
Y |
Y |
Y |
[TWAI] Suspend transmission is included even after losing arbitration |
Y |
Y |
Y |
Y |
Y |
[TWAI] When a stuff error occurs during arbitration whilst being transmitter, any errors in the subsequent error/overload frame will not increase the TEC |
Y |
Y |
Y |
Y |
Y |
[TWAI] Reading the interrupt register may lead to a transmit interrupt being lost |
Y |
Y |
Y |
Y |
Y |
LEDC |
[LEDC] When the LEDC is in decremental fade mode, a duty overflow error may occur |
Y |
Y |
Y |
Y |
Y |