Errata Summary

[中文]

Table 4 Errata summary

Category

Descriptions

Affected Revisions

v0.0

v1.0

v1.1

v3.0

v3.1

CPU

[CPU] The CPU crashes when the clock frequency switches

Y

[CPU] CPU has limitations when accessing peripherals in chips

Y

Y

Y

Y

Y

[CPU] There are limitations to the CPU access to 0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF address spaces

Y

Y

Y

Y

Y

[CPU] When the CPU accesses external SRAM in a certain sequence, read and write errors may occur

Y

Y

[CPU] When the CPU accesses external SRAM through cache, under certain conditions read and write errors occur

Y

[CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur

Y

Y

Y

[CPU] When a CPU is interrupted while accessing five specific FIFO registers, subsequent CPU accesses will get halted

Y

Y

Y

Y

Y

[CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost

Y

ULP

[ULP] ULP coprocessor and touch sensors can not be used in Deep-sleep mode if RTC_PERIPH power domain is powered up

Y

Y

Y

Y

Y

GPIO

[GPIO] For pads with both GPIO and RTC_GPIO functionality, the GPIO pull-up and pull-down configuration register fields are nonfunctional

Y

Y

Y

Y

Y

[GPIO] Within the same group of GPIO pins, edge interrupts cannot be used together with other interrupts

Y

Y

Y

Y

Y

[GPIO] When certain RTC peripherals are powered on, the inputs of GPIO36 and GPIO39 will be pulled down for approximately 80 ns

Y

Y

Y

Y

Y

Reset

[Reset] The Brown-out Reset (BOR) function does not work

Y

[Reset] A spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deep-sleep

Y

[Reset] Due to the flash start-up time, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deepsleep

Y

Y

Y
Table 5 Errata summary

Category

Descriptions

Affected Revisions

v0.0

v1.0

v1.1

v3.0

v3.1

Clock

[Clock] Audio PLL frequency range is limited

Y

[Clock] ESP32 cannot be used as the PHY clock source if Wi-Fi and Ethernet are used at the same time

Y

Y

Y

Y

Y

RTC

[RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode

Y

Y

Y

Y

Y

Watchdog

[Watchdog] ESP32 chip may have a live lock under certain conditions that will cause interrupt watchdog issue

Y

Y

UART

[UART] UART fifo_cnt does not indicate the data length in FIFO correctly

Y

Y

Y

Y

Y

TWAI

[TWAI] After losing arbitration, a dominant bit on the 3rd bit of intermission is not interpreted as an SOF

Y

Y

Y

Y

Y

[TWAI] Message transmitted after bus-off recovery is erroneous

Y

Y

Y

Y

Y

[TWAI] When the 8th bit of the error delimiter is dominant, the error passive state is not entered

Y

Y

Y

Y

Y

[TWAI] Error status bit is not frozen during bus-off recovery

Y

Y

Y

Y

Y

[TWAI] Receiving an erroneous data frame can cause the data bytes of the next received data frame to be invalid

Y

Y

Y

Y

Y

[TWAI] A negative phase error where |e| > SJW(N) will cause the remaining transmitted bits to be left shifted

Y

Y

Y

Y

Y

[TWAI] Receive Error Counter (REC) is allowed to change whilst in reset mode or bus-off recovery

Y

Y

Y

Y

Y

[TWAI] When the RX FIFO overruns with 64 or more messages, the RX FIFO becomes unrecoverable

Y

Y

Y

Y

Y

[TWAI] Suspend transmission is included even after losing arbitration

Y

Y

Y

Y

Y

[TWAI] When a stuff error occurs during arbitration whilst being transmitter, any errors in the subsequent error/overload frame will not increase the TEC

Y

Y

Y

Y

Y

[TWAI] Reading the interrupt register may lead to a transmit interrupt being lost

Y

Y

Y

Y

Y

LEDC

[LEDC] When the LEDC is in decremental fade mode, a duty overflow error may occur

Y

Y

Y

Y

Y