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ESP32-H2 Series SoC Errata

  • Chip Revision Identification
  • Errata Summary
  • All Errata Descriptions
  • Errata Descriptions by Chip Revisions
    • v0.0 (3)
    • v0.1 (3)
      • [SAR ADC] Unavailable Channel 4 in SRA ADC1
      • [Clock] Inaccurate Calibration of RC_FAST_CLK Clock
      • [CPU] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved
  • Revision History
  • Related Documentation and Resources
ESP Chip Errata
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  • Errata Descriptions by Chip Revisions »
  • Chip Revision: v0.1
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Chip Revision: v0.1

Known Errors

  • [SAR ADC] Unavailable Channel 4 in SRA ADC1
  • [Clock] Inaccurate Calibration of RC_FAST_CLK Clock
  • [CPU] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved
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