Schematic Checklist
The integrated circuitry of ESP32-S3 requires only 20 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32-S3 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32-S3.
The following figure shows a reference schematic design of ESP32-S3. It can be used as the basis of your schematic design.
ESP32-S3 Reference Schematic
Note that Figure ESP32-S3 Reference Schematic shows the connection for 3.3 V, quad, off-package SPI flash/PSRAM.
In cases where 1.8 V or 3.3 V, octal, in-package or off-package SPI flash/PSRAM is used, GPIO33 ~ GPIO37 are occupied and cannot be used for other functions.
If an in-package SPI flash/PSRAM is utilized, where VDD_SPI is set at either 1.8 V or 3.3 V, GPIO45 will no longer have any impact. In these scenarios, the presence of R1 is optional. However, in all other cases, refer to Table IO Pad Status After Chip Initialization in the USB-OTG Download Boot Mode to determine whether R1 should be populated or not.
The connection for 1.8 V, octal, off-package flash/PSRAM is as shown in Figure ESP32-S3 Schematic for Off-Package 1.8 V Octal Flash/PSRAM.
When only in-package flash/PSRAM is used, there is no need to populate the resistor on the SPI traces or to care the SPI traces.
ESP32-S3 Schematic for Off-Package 1.8 V Octal Flash/PSRAM
Any basic ESP32-S3 circuit design may be broken down into the following major building blocks:
The rest of this chapter details the specifics of circuit design for each of these sections.
Power Supply
The general recommendations for power supply design are:
When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is no less than 500 mA.
It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32-S3 Series Datasheet > Section Power Supply.
Digital Power Supply
ESP32-S3 has pin46 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V. It is recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SPI can serve as the power supply for the external device at either 1.8 V or 3.3 V (default). It is recommended to add extra 0.1 μF and 1 μF decoupling capacitors close to VDD_SPI.
When VDD_SPI operates at 1.8 V, it is powered by ESP32-S3’s internal LDO. The typical current this LDO can offer is 40 mA.
When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 14 Ω resistor, therefore, there will be some voltage drop from VDD3P3_RTC.
Attention
When using VDD_SPI as the power supply pin for in-package or off-package 3.3 V flash/PSRAM, the supply voltage should be 3.0 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.
Depending on the value of EFUSE_VDD_SPI_FORCE, the VDD_SPI voltage can be controlled in two ways, as Table VDD_SPI Voltage Control shows.
EFUSE_VDD_SPI_FORCE |
GPIO45 |
EFUSE_VDD_SPI_FORCE |
Voltage |
VDD_SPI Power Source |
|---|---|---|---|---|
0 |
0 |
Ignored |
3.3 V |
VDD3P3_RTC via RSPI (default) |
0 |
1 |
Ignored |
1.8 V |
Flash Voltage Regulator |
1 |
Ignored |
0 |
1.8 V |
Flash Voltage Regulator |
1 |
Ignored |
1 |
3.3 V |
VDD3P3_RTC via RSPI |
VDD_SPI can also be driven by an external power supply.
The schematic for the digital power supply pins is shown in Figure ESP32-S3 Schematic for Digital Power Supply Pins.
ESP32-S3 Schematic for Digital Power Supply Pins
Analog Power Supply
ESP32-S3’s VDDA and VDD3P3 pins are the analog power supply pins, working at 3.0 V ~ 3.6 V.
For VDD3P3, when ESP32-S3 is transmitting signals, there may be a sudden increase in the current draw, causing power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work in conjunction with the 1 μF capacitor(s).
It is suggested to add an extra 10 μF capacitor at the power entrance. If the power entrance is close to VDD3P3, then two 10 μF capacitors can be merged into one.
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32-S3 Schematic for Analog Power Supply Pins.
ESP32-S3 Schematic for Analog Power Supply Pins
RTC Power Supply
ESP32-S3’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32-S3 Schematic for RTC Power Supply Pin.
ESP32-S3 Schematic for RTC Power Supply Pin
Chip Power-up and Reset Timing
ESP32-S3’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low.
When ESP32-S3 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused by external interferences, make the CHIP_PU trace as short as possible.
Figure ESP32-S3 Power-up and Reset Timing shows the power-up and reset timing of ESP32-S3.
ESP32-S3 Power-up and Reset Timing
Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements.
Parameter |
Description |
Minimum (µs) |
|---|---|---|
tSTBL |
Time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip |
50 |
tRST |
Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip |
50 |
Attention
CHIP_PU must not be left floating.
To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific parameters should be adjusted based on the characteristics of the actual power supply and the power-up and reset timing of the chip.
If the user application has one of the following scenarios:
Slow power rise or fall, such as during battery charging.
Frequent power on/off operations.
Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being unable to boot correctly. In this case, additional designs need to be added, such as:
Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0 V.
Implementing reset functionality through a button or the main controller.
Flash and PSRAM
ESP32-S3 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off-package RAM is optional.
In-Package Flash and PSRAM
The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM. Please note that the following chip pins can connect at most one flash and one PSRAM. That is to say, when there is only flash in the package, the pin occupied by flash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM, the pin occupied by PSRAM can only connect flash; when there are both flash and PSRAM, the pin occupied cannot connect any more flash or PSRAM.
ESP32-S3FN8/ESP32-S3FH4R2 |
In-Package Flash (Quad SPI) |
|---|---|
SPICLK |
CLK |
SPICS0 |
CS# |
SPID |
DI |
SPIQ |
DO |
SPIWP |
WP# |
SPIHD |
HOLD# |
ESP32-S3R2/ESP32-S3FH4R2 |
In-Package PSRAM (2 MB, Quad SPI) |
|---|---|
SPICLK |
CLK |
SPICS1 |
CE# |
SPID |
SI/SIO0 |
SPIQ |
SO/SIO1 |
SPIWP |
SIO2 |
SPIHD |
SIO3 |
ESP32-S3R8/ESP32-S3R8V |
In-Package PSRAM (8 MB, Octal SPI) |
|---|---|
SPICLK |
CLK |
SPICS1 |
CE# |
SPID |
DQ0 |
SPIQ |
DQ1 |
SPIWP |
DQ2 |
SPIHD |
DQ3 |
GPIO33 |
DQ4 |
GPIO34 |
DQ5 |
GPIO35 |
DQ6 |
GPIO36 |
DQ7 |
GPIO37 |
DQS/DM |
Off-Package Flash and PSRAM
ESP32-S3 supports up to 1 GB off-package flash and 1 GB off-package RAM. If VDD_SPI is used to supply power, make sure to select the appropriate off-package flash and RAM according to the power voltage on VDD_SPI (1.8 V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving current, reduce interference to RF, adjust timing, and better shield from interference.
Clock Source
ESP32-S3 supports two external clock sources:
External Crystal Clock Source (Compulsory)
The ESP32-S3 firmware only supports 40 MHz crystal.
The circuit for the crystal is shown in Figure ESP32-S3 Schematic for External Crystal. Note that the accuracy of the selected crystal should be within ±10 ppm.
ESP32-S3 Schematic for External Crystal
Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should be adjusted after an overall test.
The initial values of external capacitors C1 and C4 can be determined according to the formula:
where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the PCB’s stray capacitance. The values of C1 and C4 need to be further adjusted after an overall test as below:
Select TX tone mode using the Certification and Test Tool.
Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to obtain the actual frequency offset.
Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance.
When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the external load capacitance needs to be increased.
When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external load capacitance needs to be reduced.
External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different values.
Note
Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable performance within the operating temperature range, etc) may lead to the malfunction of ESP32-S3, resulting in a decrease of the RF performance.
It is recommended that the amplitude of the crystal is greater than 500 mV.
When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps mentioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides of the crystal.
RTC Clock Source (Optional)
ESP32-S3 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock. The external RTC clock source enhances timing accuracy and consequently decreases average power consumption, without impacting functionality.
Figure ESP32-S3 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.
ESP32-S3 Schematic for 32.768 kHz Crystal
Please note the requirements for the 32.768 kHz crystal:
Equivalent series resistance (ESR) ≤ 70 kΩ.
Load capacitance at both ends should be configured according to the crystal’s specification.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to populate the resistor.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
The external signal can be input to the XTAL’s P end through a DC blocking capacitor (about 20 pF). The XTAL’s N end can be floating. Figure ESP32-S3 Schematic for External Oscillator shows the schematic of the external signal.
ESP32-S3 Schematic for External Oscillator
The signal should meet the following requirements:
External signal
Amplitude (Vpp, unit: V)
Sine wave or square wave
0.6 < Vpp < VDD
RF
RF Circuit
ESP32-S3’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements:
For the RF traces on the PCB board, 50 Ω impedance control is required.
For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.
The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and a set of LC can be added if space permits.
The RF matching circuit is shown in Figure ESP32-S3 Schematic for RF Matching.
For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.
ESP32-S3 Schematic for RF Matching
RF Tuning
The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly. Follow the instructions below to do RF tuning.
Figure ESP32-S3 RF Tuning Diagram shows the general process of RF tuning.
ESP32-S3 RF Tuning Diagram
In the matching circuit, define the port near the chip as Port 1 and the port near the antenna as Port 2. S11 describes the ratio of the signal power reflected back from Port 1 to the input signal power, the transmission performance is best if the matching impedance is conjugate to the chip impedance. S21 is used to describe the transmission loss of signal from Port 1 to Port 2. If S11 is close to the chip conjugate point (35+j0) and S21 is less than -35 dB at 4.8 GHz and 7.2 GHz, the matching circuit can satisfy transmission requirements.
Connect the two ends of the matching circuit to the network analyzer, and test its signal reflection parameter S11 and transmission parameter S21. Adjust the values of the components in the circuit until S11 and S21 meet the requirements. If your PCB design of the chip strictly follows the PCB design stated in Chapter PCB Layout Design, you can refer to the value ranges in Table Recommended Value Ranges for Components to debug the matching circuit.
Reference Designator |
Recommended Value Range |
Serial No. |
|---|---|---|
C11 |
1.2 ~ 1.8 pF |
GRM0335C1H1RXBA01D |
L2 |
2.4 ~ 3.0 nH |
LQP03TN2NXB02D |
C12 |
1.8 ~ 1.2 pF |
GRM0335C1H1RXBA01D |
If the components are in the 0201 SMD package size, please use a stub in the PCB design of the RF matching circuit near the chip. If the antenna input impedance is not 50 ohm, an additional set of RF matching is recommended for antenna tuning.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD protection devices near the antenna.
Note
If RF function is not required, then the RF pin can be left floating.
UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0, please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX line to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to AT Firmware Download). It is recommended to use the default configuration.
Strapping Pins
At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal function pins.
All the information about strapping pins is covered in ESP32-S3 Series Datasheet > Section Strapping Pins. In this document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO0 and GPIO46 controls the boot mode. See Table Boot Mode Control.
Boot Mode |
GPIO0 |
GPIO46 |
|---|---|---|
Default Config |
1 (Pull-up) |
0 (Pull-down) |
SPI Boot (default) |
1 |
Any value |
Joint Download Boot 1 |
0 |
0 |
Invalid combination 2 |
0 |
1 |
- 1
Joint Download Boot mode supports the following download methods:
USB Download Boot:
USB-Serial-JTAG Download Boot
USB-OTG Download Boot
UART Download Boot
- 2
This combination triggers unexpected behavior and should be avoided.
Signals applied to the strapping pins should have specific setup time and hold time. For more information, see Figure Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
Setup and Hold Times for Strapping Pins
Parameter |
Description |
Minimum (ms) |
|---|---|---|
tSU |
Time reserved for the power rails to stabilize before the chip enable pin (CHIP_PU) is pulled high to activate the chip. |
0 |
tH |
Time reserved for the chip to read the strapping pin values after CHIP_PU is already high and before these pins start operating as regular IO pins. |
3 |
Attention
Do not add high-value capacitors at GPIO0, otherwise, the chip may not boot successfully.
GPIO
The pins of ESP32-S3 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configurations, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about IO MUX and GPIO matrix, please refer to ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available GPIO pins. For details, please refer to ESP32-S3 Series Datasheet > Section Peripheral Pin Configurations.
When using GPIOs, please:
Pay attention to the states of strapping pins during power-up.
Pay attention to the default configurations of the GPIOs after reset. The default configurations can be found in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the high-impedance state or enable the pull-up and pull-down during software initialization to avoid extra power consumption.
Avoid using the pins already occupied by flash/PSRAM.
Some pins will have glitches during power-up. Refer to Table Power-Up Glitches on Pins for details.
When USB-OTG Download Boot mode is enabled, some pins will have level output. Refer to Table IO Pad Status After Chip Initialization in the USB-OTG Download Boot Mode for details.
SPICLK_N, SPICLK_P, and GPIO33 ~ GPIO37 work in the same power domain, so if octal 1.8 V flash/PSRAM is used, then SPICLK_P and SPICLK_N also work in the 1.8 V power domain.
Only GPIOs in the VDD3P3_RTC power domain can be controlled in Deep-sleep mode.
No. |
Name |
Type |
Power |
At Reset |
After Reset |
IO MUX |
RTC |
Analog |
|---|---|---|---|---|---|---|---|---|
1 |
LNA_IN |
Analog |
||||||
2 |
VDD3P3 |
Power |
||||||
3 |
VDD3P3 |
Power |
||||||
4 |
CHIP_PU |
Analog |
VDD3P3_RTC |
|||||
5 |
GPIO0 |
IO |
VDD3P3_RTC |
IE, WPU |
IE, WPU |
IO MUX |
RTC |
|
6 |
GPIO1 |
IO |
VDD3P3_RTC |
IE |
IE |
IO MUX |
RTC |
Analog |
7 |
GPIO2 |
IO |
VDD3P3_RTC |
IE |
IE |
IO MUX |
RTC |
Analog |
8 |
GPIO3 |
IO |
VDD3P3_RTC |
IE |
IE |
IO MUX |
RTC |
Analog |
9 |
GPIO4 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
10 |
GPIO5 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
11 |
GPIO6 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
12 |
GPIO7 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
13 |
GPIO8 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
14 |
GPIO9 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
15 |
GPIO10 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
16 |
GPIO11 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
17 |
GPIO12 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
18 |
GPIO13 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
19 |
GPIO14 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
20 |
VDD3P3_RTC |
Power |
||||||
21 |
XTAL_32K_P |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
22 |
XTAL_32K_N |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
23 |
GPIO17 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
24 |
GPIO18 |
IO |
VDD3P3_RTC |
IE |
IO MUX |
RTC |
Analog |
|
25 |
GPIO19 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
Analog |
||
26 |
GPIO20 |
IO |
VDD3P3_RTC |
USB_PU |
USB_PU |
IO MUX |
RTC |
Analog |
27 |
GPIO21 |
IO |
VDD3P3_RTC |
IO MUX |
RTC |
|||
28 |
SPICS1 |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
29 |
VDD_SPI |
Power |
||||||
30 |
SPIHD |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
31 |
SPIWP |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
32 |
SPICS0 |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
33 |
SPICLK |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
34 |
SPIQ |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
35 |
SPID |
IO |
VDD_SPI |
IE, WPU |
IE, WPU |
IO MUX |
||
36 |
SPICLK_N |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IE |
IO MUX |
||
37 |
SPICLK_P |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IE |
IO MUX |
||
38 |
GPIO33 |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IO MUX |
|||
39 |
GPIO34 |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IO MUX |
|||
40 |
GPIO35 |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IO MUX |
|||
41 |
GPIO36 |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IO MUX |
|||
42 |
GPIO37 |
IO |
VDD_SPI / VDD3P3_CPU |
IE |
IO MUX |
|||
43 |
GPIO38 |
IO |
VDD3P3_CPU |
IE |
IO MUX |
|||
44 |
MTCK |
IO |
VDD3P3_CPU |
IE |
IO MUX |
|||
45 |
MTDO |
IO |
VDD3P3_CPU |
IE |
IO MUX |
|||
46 |
VDD3P3_CPU |
Power |
||||||
47 |
MTDI |
IO |
VDD3P3_CPU |
IE |
IO MUX |
|||
48 |
MTMS |
IO |
VDD3P3_CPU |
IE |
IO MUX |
|||
49 |
U0TXD |
IO |
VDD3P3_CPU |
IE, WPU |
IE, WPU |
IO MUX |
||
50 |
U0RXD |
IO |
VDD3P3_CPU |
IE, WPU |
IE, WPU |
IO MUX |
||
51 |
GPIO45 |
IO |
VDD3P3_CPU |
IE, WPD |
IE, WPD |
IO MUX |
||
52 |
GPIO46 |
IO |
VDD3P3_CPU |
IE, WPD |
IE, WPD |
IO MUX |
||
53 |
XTAL_N |
Analog |
||||||
54 |
XTAL_P |
Analog |
||||||
55 |
VDDA |
Power |
||||||
56 |
VDDA |
Power |
||||||
57 |
GND |
Power |
IE – input enabled
WPU – internal weak pull-up resistor enabled
WPD – internal weak pull-down resistor enabled
USB_PU – USB pull-up resistor enabled
By default, the USB function is enabled for USB pins (i.e., GPIO19 and GPIO20), and the pin pull-up is decided by the USB pull-up resistor. The USB pull-up resistor is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up value is controlled by USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-S3 Technical Reference Manual > Chapter USB Serial/JTAG Controller.
When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_FUN_WPU/WPD)
Pin |
Glitch 3 |
Typical Time (µs) |
|---|---|---|
GPIO1 |
Low-level glitch |
60 |
GPIO2 |
Low-level glitch |
60 |
GPIO3 |
Low-level glitch |
60 |
GPIO4 |
Low-level glitch |
60 |
GPIO5 |
Low-level glitch |
60 |
GPIO6 |
Low-level glitch |
60 |
GPIO7 |
Low-level glitch |
60 |
GPIO8 |
Low-level glitch |
60 |
GPIO9 |
Low-level glitch |
60 |
GPIO10 |
Low-level glitch |
60 |
GPIO11 |
Low-level glitch |
60 |
GPIO12 |
Low-level glitch |
60 |
GPIO13 |
Low-level glitch |
60 |
GPIO14 |
Low-level glitch |
60 |
XTAL_32K_P |
Low-level glitch |
60 |
XTAL_32K_N |
Low-level glitch |
60 |
GPIO17 |
Low-level glitch |
60 |
GPIO18 |
Low-level/High-level glitch |
60 |
GPIO19 |
Low-level glitch/High-level glitch 4 |
60 |
GPIO20 |
Pull-down glitch/High-level glitch 4 |
60 |
- 3
Low-level glitch: the pin is at a low level output status during the time period;
High-level glitch: the pin is at a high level output status during the time period;
Pull-down glitch: the pin is at an internal weak pulled-down status during the time period;
Pull-up glitch: the pin is at an internal weak pulled-up status during the time period.
- 4(1,2)
GPIO19 and GPIO20 pins both have two high-level glitches during chip power-up, each lasting for about 60 µs. The total duration for the glitches and the delay are 3.2 ms and 2 ms respectively for GPIO19 and GPIO20.
ADC
Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
ADC1 is recommended for use.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher accuracy, you may implement your own calibration methods.
When ATTEN=0 and the effective measurement range is 0 ~ 850 mV, the total error is ±5 mV.
When ATTEN=1 and the effective measurement range is 0 ~ 1100 mV, esp32c6=, the total error is ±6 mV.
When ATTEN=2 and the effective measurement range is 0 ~ 1600 mV, the total error is ±10 mV.
When ATTEN=3 and the effective measurement range is 0 ~ 2900 mV, the total error is ±50 mV.
SDIO
ESP32-S3 only has one SD/MMC Host controller, which cannot be used as a slave device.
The SDIO interface can be configured to any free GPIO by software. Please add pull-up resistors to the SDIO GPIO pins, and it is recommended to reserve a series resistor on each trace.
USB
ESP32-S3 has a full-speed USB On-The-Go (OTG) peripheral with integrated transceivers. The USB peripheral is compliant with the USB 2.0 specification.
ESP32-S3 integrates a USB Serial/JTAG controller that supports USB 2.0 full-speed device.
GPIO19 and GPIO20 can be used as D- and D + of USB respectively. It is recommended to populate zero-ohm series resistors between the mentioned pins and the USB connector. Also, reserve a footprint for a capacitor to ground on each trace. Note that both components should be placed close to the chip.
Note that USB_D+ will have level output, so please add a pull-up resistor to determine the initial high-level output voltage.
ESP32-S3 also supports download functions and log message printing via USB. For details please refer to Section Download Guidelines.
When USB-OTG Download Boot mode is enabled, the chip initializes the IO pad connected to the external PHY in ROM when starts up. The status of each IO pad after initialization is as follows.
IO Pad |
Input/Output Mode |
Level Status |
|---|---|---|
VP (MTMS) |
INPUT |
– |
VM (MTDI) |
INPUT |
– |
RCV (GPIO21) |
INPUT |
– |
OEN (MTDO) |
OUTPUT |
HIGH |
VPO (MTCK) |
OUTPUT |
LOW |
VMO(GPIO38) |
OUTPUT |
LOW |
If the USB-OTG Download Boot mode is not needed, it is suggested to disable the USB-OTG Download Boot mode by setting the eFuse bit EFUSE_DIS_USB_OTG_DOWNLOAD_MODE to avoid IO pad state change.
Touch Sensor
When using the touch function, it is recommended to populate a zero-ohm series resistor at the chip side to reduce the coupling noise and interference on the line, and to strengthen the ESD protection. The recommended resistance is from 470 Ω to 2 kΩ, preferably 510 Ω. The specific value depends on the actual test results of the product.
The ESP32-S3 touch sensor has a waterproof design and digital filtering function. Note that only GPIO14 (TOUCH14) can drive the shield electrode.