SoC 功能
此文档介绍了 ESP32-P4 SoC 硬件功能的宏定义。ESP-IDF 中的条件编译指令通常使用这些宏来确定哪些依赖于硬件的功能受到支持,从而控制需编译的代码内容。
备注
目前,这些宏定义不属于公共 API,未来可能发生重大更改。如需了解详情,请前往 ESP-IDF 版本简介。
API 参考
Header File
This header file can be included with:
#include "soc/soc_caps.h"
Macros
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SOC_ANA_CMPR_SUPPORTED
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SOC_UART_SUPPORTED
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SOC_GDMA_SUPPORTED
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SOC_AHB_GDMA_SUPPORTED
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SOC_AXI_GDMA_SUPPORTED
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SOC_GPTIMER_SUPPORTED
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SOC_PCNT_SUPPORTED
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SOC_MCPWM_SUPPORTED
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SOC_ETM_SUPPORTED
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SOC_PARLIO_SUPPORTED
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SOC_ASYNC_MEMCPY_SUPPORTED
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SOC_SUPPORTS_SECURE_DL_MODE
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SOC_EFUSE_KEY_PURPOSE_FIELD
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SOC_EFUSE_SUPPORTED
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SOC_RTC_FAST_MEM_SUPPORTED
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SOC_RTC_MEM_SUPPORTED
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SOC_RMT_SUPPORTED
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SOC_I2S_SUPPORTED
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SOC_GPSPI_SUPPORTED
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SOC_LEDC_SUPPORTED
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SOC_I2C_SUPPORTED
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SOC_SYSTIMER_SUPPORTED
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SOC_MPI_SUPPORTED
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SOC_HMAC_SUPPORTED
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SOC_DIG_SIGN_SUPPORTED
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SOC_ECC_SUPPORTED
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SOC_ECC_EXTENDED_MODES_SUPPORTED
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SOC_ECDSA_SUPPORTED
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SOC_FLASH_ENC_SUPPORTED
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SOC_SECURE_BOOT_SUPPORTED
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SOC_LP_GPIO_MATRIX_SUPPORTED
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SOC_LP_PERIPHERALS_SUPPORTED
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SOC_SPIRAM_SUPPORTED
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SOC_PSRAM_DMA_CAPABLE
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SOC_SDMMC_HOST_SUPPORTED
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SOC_WDT_SUPPORTED
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SOC_SPI_FLASH_SUPPORTED
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SOC_XTAL_SUPPORT_40M
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SOC_AES_SUPPORT_DMA
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SOC_AES_GDMA
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SOC_AES_SUPPORT_AES_128
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SOC_AES_SUPPORT_AES_256
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SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)
< SAR ADC Module
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SOC_ADC_PERIPH_NUM
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SOC_ADC_CHANNEL_NUM(PERIPH_NUM)
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SOC_ADC_MAX_CHANNEL_NUM
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SOC_ADC_ATTEN_NUM
Digital
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SOC_ADC_DIGI_CONTROLLER_NUM
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SOC_ADC_PATT_LEN_MAX
Two pattern tables, each contains 4 items. Each item takes 1 byte
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SOC_ADC_DIGI_MAX_BITWIDTH
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SOC_ADC_DIGI_MIN_BITWIDTH
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SOC_ADC_DIGI_IIR_FILTER_NUM
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SOC_ADC_DIGI_MONITOR_NUM
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SOC_ADC_DIGI_RESULT_BYTES
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SOC_ADC_DIGI_DATA_BYTES_PER_CONV
F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095
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SOC_ADC_SAMPLE_FREQ_THRES_HIGH
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SOC_ADC_SAMPLE_FREQ_THRES_LOW
RTC
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SOC_ADC_RTC_MIN_BITWIDTH
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SOC_ADC_RTC_MAX_BITWIDTH
Calibration
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SOC_ADC_CALIBRATION_V1_SUPPORTED
support HW offset calibration version 1
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SOC_APB_BACKUP_DMA
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SOC_BROWNOUT_RESET_SUPPORTED
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SOC_SHARED_IDCACHE_SUPPORTED
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SOC_CACHE_WRITEBACK_SUPPORTED
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SOC_CACHE_FREEZE_SUPPORTED
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SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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SOC_CPU_CORES_NUM
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SOC_CPU_INTR_NUM
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SOC_CPU_HAS_FLEXIBLE_INTC
-
SOC_INT_PLIC_SUPPORTED
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SOC_INT_CLIC_SUPPORTED
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SOC_INT_HW_NESTED_SUPPORTED
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SOC_BRANCH_PREDICTOR_SUPPORTED
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SOC_CPU_HAS_FPU
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SOC_CPU_HAS_FPU_EXT_ILL_BUG
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SOC_CPU_COPROC_NUM
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SOC_HP_CPU_HAS_MULTIPLE_CORES
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SOC_CPU_BREAKPOINTS_NUM
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SOC_CPU_WATCHPOINTS_NUM
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SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
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SOC_CPU_HAS_PMA
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SOC_CPU_IDRAM_SPLIT_USING_PMP
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SOC_DS_SIGNATURE_MAX_BIT_LEN
The maximum length of a Digital Signature in bits.
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SOC_DS_KEY_PARAM_MD_IV_LENGTH
Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes.
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SOC_DS_KEY_CHECK_MAX_WAIT_US
Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details
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SOC_AHB_GDMA_VERSION
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SOC_GDMA_SUPPORT_CRC
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SOC_GDMA_NUM_GROUPS_MAX
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SOC_GDMA_PAIRS_PER_GROUP_MAX
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SOC_AXI_GDMA_SUPPORT_PSRAM
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SOC_ETM_GROUPS
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SOC_ETM_CHANNELS_PER_GROUP
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SOC_GPIO_PORT
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SOC_GPIO_PIN_COUNT
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SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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SOC_GPIO_SUPPORT_ETM
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SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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SOC_GPIO_VALID_GPIO_MASK
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SOC_GPIO_VALID_OUTPUT_GPIO_MASK
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SOC_GPIO_IN_RANGE_MAX
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SOC_GPIO_OUT_RANGE_MAX
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SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
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SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
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SOC_GPIO_SUPPORT_FORCE_HOLD
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SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
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SOC_RTCIO_PIN_COUNT
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SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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SOC_RTCIO_HOLD_SUPPORTED
-
SOC_RTCIO_WAKE_SUPPORTED
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SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
8 outward channels on each CPU core
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SOC_DEDIC_GPIO_IN_CHANNELS_NUM
8 inward channels on each CPU core
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SOC_DEDIC_PERIPH_ALWAYS_ENABLE
The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled
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SOC_ANA_CMPR_NUM
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SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE
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SOC_ANA_CMPR_SUPPORT_ETM
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SOC_I2C_NUM
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SOC_I2C_FIFO_LEN
I2C hardware FIFO depth
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SOC_I2C_CMD_REG_NUM
Number of I2C command registers
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SOC_I2C_SUPPORT_SLAVE
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SOC_I2C_SUPPORT_HW_FSM_RST
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SOC_I2C_SUPPORT_HW_CLR_BUS
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SOC_I2C_SUPPORT_XTAL
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SOC_I2C_SUPPORT_RTC
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SOC_I2C_SUPPORT_10BIT_ADDR
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SOC_I2C_SLAVE_SUPPORT_BROADCAST
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SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
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SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
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SOC_I2S_NUM
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SOC_I2S_HW_VERSION_2
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SOC_I2S_SUPPORTS_XTAL
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SOC_I2S_SUPPORTS_APLL
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SOC_I2S_SUPPORTS_PCM
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SOC_I2S_SUPPORTS_PDM
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SOC_I2S_SUPPORTS_PDM_TX
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SOC_I2S_SUPPORTS_PDM_RX
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SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
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SOC_I2S_SUPPORTS_TX_SYNC_CNT
-
SOC_I2S_SUPPORTS_TDM
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SOC_I2S_PDM_MAX_TX_LINES
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SOC_I2S_PDM_MAX_RX_LINES
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SOC_I2S_TDM_FULL_DATA_WIDTH
No limitation to data bit width when using multiple slots
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SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
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SOC_LEDC_SUPPORT_XTAL_CLOCK
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SOC_LEDC_CHANNEL_NUM
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SOC_LEDC_TIMER_BIT_WIDTH
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SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
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SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
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SOC_LEDC_SUPPORT_FADE_STOP
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SOC_LEDC_FADE_PARAMS_BIT_WIDTH
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SOC_MMU_PAGE_SIZE_CONFIGURABLE
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SOC_MMU_PERIPH_NUM
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SOC_MMU_LINEAR_ADDRESS_REGION_NUM
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SOC_MMU_DI_VADDR_SHARED
D/I vaddr are shared
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SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
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SOC_MPU_MIN_REGION_SIZE
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SOC_MPU_REGIONS_MAX_NUM
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SOC_MPU_REGION_RO_SUPPORTED
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SOC_MPU_REGION_WO_SUPPORTED
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SOC_PCNT_GROUPS
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SOC_PCNT_UNITS_PER_GROUP
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SOC_PCNT_CHANNELS_PER_UNIT
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SOC_PCNT_THRES_POINT_PER_UNIT
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SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
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SOC_PCNT_SUPPORT_CLEAR_SIGNAL
Support clear signal input
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SOC_RMT_GROUPS
One RMT group
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SOC_RMT_TX_CANDIDATES_PER_GROUP
Number of channels that capable of Transmit in each group
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SOC_RMT_RX_CANDIDATES_PER_GROUP
Number of channels that capable of Receive in each group
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SOC_RMT_CHANNELS_PER_GROUP
Total 8 channels
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SOC_RMT_MEM_WORDS_PER_CHANNEL
Each channel owns 48 words memory (1 word = 4 Bytes)
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SOC_RMT_SUPPORT_RX_PINGPONG
Support Ping-Pong mode on RX path
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SOC_RMT_SUPPORT_RX_DEMODULATION
Support signal demodulation on RX path (i.e. remove carrier)
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SOC_RMT_SUPPORT_TX_ASYNC_STOP
Support stop transmission asynchronously
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SOC_RMT_SUPPORT_TX_LOOP_COUNT
Support transmit specified number of cycles in loop mode
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SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
Hardware support of auto-stop in loop mode
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SOC_RMT_SUPPORT_TX_SYNCHRO
Support coordinate a group of TX channels to start simultaneously
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SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
TX carrier can be modulated to data phase only
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SOC_RMT_SUPPORT_XTAL
Support set XTAL clock as the RMT clock source
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SOC_RMT_SUPPORT_DMA
RMT peripheral can connect to DMA channel
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SOC_MCPWM_GROUPS
2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
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SOC_MCPWM_TIMERS_PER_GROUP
The number of timers that each group has.
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SOC_MCPWM_OPERATORS_PER_GROUP
The number of operators that each group has.
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SOC_MCPWM_COMPARATORS_PER_OPERATOR
The number of comparators that each operator has.
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SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
The number of event comparators that each operator has.
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SOC_MCPWM_GENERATORS_PER_OPERATOR
The number of generators that each operator has.
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SOC_MCPWM_TRIGGERS_PER_OPERATOR
The number of triggers that each operator has.
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SOC_MCPWM_GPIO_FAULTS_PER_GROUP
The number of fault signal detectors that each group has.
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SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
The number of capture timers that each group has.
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SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
The number of capture channels that each capture timer has.
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SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
The number of GPIO synchros that each group has.
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SOC_MCPWM_SWSYNC_CAN_PROPAGATE
Software sync event can be routed to its output.
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SOC_MCPWM_SUPPORT_ETM
Support ETM (Event Task Matrix)
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SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
Support event comparator (based on ETM)
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SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
Capture timer shares clock with other PWM timers.
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SOC_PARLIO_GROUPS
Number of parallel IO peripherals
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SOC_PARLIO_TX_UNITS_PER_GROUP
number of TX units in each group
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SOC_PARLIO_RX_UNITS_PER_GROUP
number of RX units in each group
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SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
Number of data lines of the TX unit
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SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
Number of data lines of the RX unit
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SOC_PARLIO_TX_SIZE_BY_DMA
Transaction length is controlled by DMA instead of indicated by register
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SOC_MPI_MEM_BLOCKS_NUM
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SOC_MPI_OPERATIONS_NUM
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SOC_RSA_MAX_BIT_LEN
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SOC_SDMMC_USE_IOMUX
Card detect, write protect, interrupt use GPIO Matrix on all chips. Slot 0 clock/cmd/data pins use IOMUX Slot 1 clock/cmd/data pins use GPIO Matrix
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SOC_SDMMC_USE_GPIO_MATRIX
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SOC_SDMMC_NUM_SLOTS
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SOC_SDMMC_DELAY_PHASE_NUM
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SOC_SHA_DMA_MAX_BUFFER_SIZE
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SOC_SHA_SUPPORT_DMA
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SOC_SHA_SUPPORT_RESUME
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SOC_SHA_GDMA
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SOC_SHA_SUPPORT_SHA1
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SOC_SHA_SUPPORT_SHA224
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SOC_SHA_SUPPORT_SHA256
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SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
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SOC_ECDSA_USES_MPI
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SOC_SDM_GROUPS
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SOC_SDM_CHANNELS_PER_GROUP
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SOC_SDM_CLK_SUPPORT_PLL_F80M
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SOC_SDM_CLK_SUPPORT_XTAL
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SOC_SPI_PERIPH_NUM
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SOC_SPI_PERIPH_CS_NUM(i)
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SOC_SPI_MAX_CS_NUM
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SOC_SPI_MAXIMUM_BUFFER_SIZE
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SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
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SOC_SPI_SUPPORT_DDRCLK
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SOC_SPI_SUPPORT_CD_SIG
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SOC_SPI_SUPPORT_OCT
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SOC_SPI_SUPPORT_CLK_XTAL
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SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
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SOC_MEMSPI_IS_INDEPENDENT
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SOC_SPI_MAX_PRE_DIVIDER
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SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
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SOC_SPI_MEM_SUPPORT_AUTO_RESUME
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SOC_SPI_MEM_SUPPORT_IDLE_INTR
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SOC_SPI_MEM_SUPPORT_SW_SUSPEND
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SOC_SPI_MEM_SUPPORT_CHECK_SUS
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SOC_SPI_MEM_SUPPORT_WRAP
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SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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SOC_SYSTIMER_COUNTER_NUM
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SOC_SYSTIMER_ALARM_NUM
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SOC_SYSTIMER_BIT_WIDTH_LO
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SOC_SYSTIMER_BIT_WIDTH_HI
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SOC_SYSTIMER_FIXED_DIVIDER
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SOC_SYSTIMER_SUPPORT_RC_FAST
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SOC_SYSTIMER_INT_LEVEL
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SOC_SYSTIMER_ALARM_MISS_COMPENSATE
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SOC_LP_TIMER_BIT_WIDTH_LO
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SOC_LP_TIMER_BIT_WIDTH_HI
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SOC_TIMER_GROUPS
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SOC_TIMER_GROUP_TIMERS_PER_GROUP
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SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
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SOC_TIMER_GROUP_SUPPORT_XTAL
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SOC_TIMER_GROUP_SUPPORT_RC_FAST
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SOC_TIMER_GROUP_TOTAL_TIMERS
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SOC_TIMER_SUPPORT_ETM
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SOC_MWDT_SUPPORT_XTAL
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SOC_TWAI_CONTROLLER_NUM
-
SOC_TWAI_CLK_SUPPORT_XTAL
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SOC_TWAI_BRP_MIN
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SOC_TWAI_BRP_MAX
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SOC_TWAI_SUPPORTS_RX_STATUS
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SOC_EFUSE_DIS_DOWNLOAD_ICACHE
-
SOC_EFUSE_DIS_PAD_JTAG
-
SOC_EFUSE_DIS_USB_JTAG
-
SOC_EFUSE_DIS_DIRECT_BOOT
-
SOC_EFUSE_SOFT_DIS_JTAG
-
SOC_SECURE_BOOT_V2_RSA
-
SOC_SECURE_BOOT_V2_ECC
-
SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
-
SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
-
SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
-
SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
-
SOC_FLASH_ENCRYPTION_XTS_AES
-
SOC_FLASH_ENCRYPTION_XTS_AES_128
-
SOC_UART_NUM
-
SOC_UART_HP_NUM
-
SOC_UART_LP_NUM
-
SOC_UART_FIFO_LEN
The UART hardware FIFO length
-
SOC_LP_UART_FIFO_LEN
The LP UART hardware FIFO length
-
SOC_UART_BITRATE_MAX
Max bit rate supported by UART
-
SOC_UART_SUPPORT_PLL_F80M_CLK
Support PLL_F80M as the clock source
-
SOC_UART_SUPPORT_RTC_CLK
Support RTC clock as the clock source
-
SOC_UART_SUPPORT_XTAL_CLK
Support XTAL clock as the clock source
-
SOC_UART_SUPPORT_WAKEUP_INT
Support UART wakeup interrupt
-
SOC_UART_HAS_LP_UART
Support LP UART
-
SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-
SOC_COEX_HW_PTI
-
SOC_PHY_DIG_REGS_MEM_SIZE
-
SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
-
SOC_PM_SUPPORT_WIFI_WAKEUP
-
SOC_PM_SUPPORT_CPU_PD
-
SOC_PM_SUPPORT_MODEM_PD
-
SOC_PM_SUPPORT_XTAL32K_PD
-
SOC_PM_SUPPORT_RC32K_PD
-
SOC_PM_SUPPORT_RC_FAST_PD
-
SOC_PM_SUPPORT_VDDSDIO_PD
-
SOC_PM_SUPPORT_TOP_PD
-
SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
Supports CRC only the stub code in RTC memory
-
SOC_PM_CPU_RETENTION_BY_SW
-
SOC_PM_PAU_LINK_NUM
-
SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
-
SOC_MODEM_CLOCK_IS_INDEPENDENT
-
SOC_CLK_APLL_SUPPORTED
Support Audio PLL
-
SOC_CLK_XTAL32K_SUPPORTED
Support to connect an external low frequency crystal
-
SOC_CLK_OSC_SLOW_SUPPORTED
Support to connect an external oscillator, not a crystal
-
SOC_CLK_RC32K_SUPPORTED
Support an internal 32kHz RC oscillator
-
SOC_PERIPH_CLK_CTRL_SHARED
Peripheral clock control (e.g. set clock source) is shared between various peripherals
-
SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
-
SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
-
SOC_MEM_TCM_SUPPORTED