Summary of Issues Related to MIPI-DSI Interface Screen

[中文]

This document mainly summarizes the common problems in the development process of the MIPI DSI interface screen and provides corresponding solutions.

Related Documents

MIPI-DSI Interface Driver API Reference

Related Examples

MIPI-DSI Interface Screen Driver Example

Timing Parameter Calculation

Method of calculating lane_bit_rate_mbps

1. Calculate the original data rate

   Pixel Clock formula:

   pixel_clock = (horizontal resolution + HBP + HFP + HSPW) × (vertical resolution + VBP + VFP + VSPW) × refresh rate
   

   Raw Data Rate formula:

   raw_data_rate = pixel_clock × bits_per_pixel
   

2. Consider DSI protocol overhead

   • 8b/10b encoding: increase by 25% (×1.25)

   • Packet header + ECC: reserve about 10~15% (here take 15%, ×1.15)

   In summary:

   protocol_data_rate = raw_data_rate × 1.25 × 1.15
   

3. Divide evenly by the number of data channels:

   lane_bit_rate = protocol_data_rate ÷ num_data_lanes
   

4. Reserve 20% bandwidth margin:

   final_bit_rate = lane_bit_rate × 1.2
   

• Note, on the ESP32-P4 platform, the maximum lane_bit_rate_mbps ≤ 1.5 Gbps, and the minimum is recommended to be ≥ 480 Mbps.

Example Calculation

• Resolution: 800 × 1280 (HSPW=4, HBP=20, HFP=20; VSPW=4, VBP=20, VFP=20)

• Refresh rate: 60 Hz

• Color depth: 24 bpp

• Number of data channels: 2

Specific steps:

1. Pixel Clock:

   pixel_clock = (800+20+20+4) × (1280+20+20+4) × 60
               = 62.4 MHz
   

2. Raw Data Rate:

   raw_data_rate = 62.4 MHz × 24 = 1497.6 Mbps
   

3. Protocol overhead adjustment:

   protocol_data_rate = 1497.6 × 1.25 × 1.15 = 2153.55 Mbps
   

4. Single channel rate:

   lane_bit_rate = 2153.55 ÷ 2 ≈ 1076.78 Mbps
   

5. Reserve 20% margin:

   final_bit_rate = 1076.78 × 1.2 ≈ 1292 Mbps
   

Therefore, lane_bit_rate_mbps ≈ 1.3 Gbps.

About the Screen Selection Trouble Brought by the Number of MIPI-DSI Data Channels

The ESP32-P4 supports up to MIPI-DSI 2 lane. Although most screens on the market are primarily 4 lane, most panels can be made compatible with 2 lane through register configuration, so there is no need to be overly restricted when choosing a type. At the same time, you can refer to the list of screens that support MIPI-DSI in the LCD driver IC.

• Please note, the ESP32-P4 only supports Video mode for video stream output and does not support Command mode. This should be taken into consideration when customers choose a screen.