SoC Capabilities

This section lists definitions of the ESP32-S2’s SoC hardware capabilities. These definitions are commonly used in IDF to control which hardware dependent features are supported and thus compiled into the binary.

Note

These defines are currently not considered to be part of the public API, and may be changed at any time.

API Reference

Macros

SOC_ADC_SUPPORTED
SOC_DAC_SUPPORTED
SOC_TWAI_SUPPORTED
SOC_CP_DMA_SUPPORTED
SOC_DEDICATED_GPIO_SUPPORTED
SOC_SUPPORTS_SECURE_DL_MODE
SOC_RISCV_COPROC_SUPPORTED
SOC_USB_OTG_SUPPORTED
SOC_PCNT_SUPPORTED
SOC_WIFI_SUPPORTED
SOC_ULP_SUPPORTED
SOC_CCOMP_TIMER_SUPPORTED
SOC_ASYNC_MEMCPY_SUPPORTED
SOC_EFUSE_KEY_PURPOSE_FIELD
SOC_TEMP_SENSOR_SUPPORTED
SOC_CACHE_SUPPORT_WRAP
SOC_RTC_FAST_MEM_SUPPORTED
SOC_RTC_SLOW_MEM_SUPPORTED
SOC_PSRAM_DMA_CAPABLE
SOC_XT_WDT_SUPPORTED
SOC_I2S_SUPPORTED
SOC_RMT_SUPPORTED
SOC_SIGMADELTA_SUPPORTED
SOC_SUPPORT_COEXISTENCE
SOC_AES_SUPPORTED
SOC_MPI_SUPPORTED
SOC_SHA_SUPPORTED
SOC_HMAC_SUPPORTED
SOC_DIG_SIGN_SUPPORTED
SOC_FLASH_ENC_SUPPORTED
SOC_SECURE_BOOT_SUPPORTED
SOC_ADC_RTC_CTRL_SUPPORTED

< SAR ADC Module

SOC_ADC_DIG_CTRL_SUPPORTED
SOC_ADC_ARBITER_SUPPORTED
SOC_ADC_FILTER_SUPPORTED
SOC_ADC_MONITOR_SUPPORTED
SOC_ADC_PERIPH_NUM
SOC_ADC_CHANNEL_NUM(PERIPH_NUM)
SOC_ADC_MAX_CHANNEL_NUM
SOC_ADC_ATTEN_NUM

Digital

SOC_ADC_DIGI_CONTROLLER_NUM
SOC_ADC_PATT_LEN_MAX

Two pattern table, each contains 16 items. Each item takes 1 byte

SOC_ADC_DIGI_MAX_BITWIDTH

F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095

SOC_ADC_SAMPLE_FREQ_THRES_HIGH
SOC_ADC_SAMPLE_FREQ_THRES_LOW

RTC

SOC_ADC_RTC_MIN_BITWIDTH
SOC_ADC_RTC_MAX_BITWIDTH
SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256

Calibration

SOC_ADC_CALIBRATION_V1_SUPPORTED

support HW offset calibration version 1

SOC_BROWNOUT_RESET_SUPPORTED
SOC_CP_DMA_MAX_BUFFER_SIZE

Maximum size of the buffer that can be attached to descriptor

SOC_CPU_CORES_NUM
SOC_CPU_INTR_NUM
SOC_CPU_BREAKPOINTS_NUM
SOC_CPU_WATCHPOINTS_NUM
SOC_CPU_WATCHPOINT_SIZE
SOC_DAC_PERIPH_NUM
SOC_DAC_RESOLUTION
SOC_GPIO_PORT
SOC_GPIO_PIN_COUNT
SOC_GPIO_SUPPORT_RTC_INDEPENDENT
SOC_GPIO_SUPPORT_FORCE_HOLD
SOC_GPIO_VALID_GPIO_MASK
SOC_GPIO_VALID_OUTPUT_GPIO_MASK
SOC_GPIO_SUPPORT_SLP_SWITCH
SOC_DEDIC_GPIO_OUT_CHANNELS_NUM

8 outward channels on each CPU core

SOC_DEDIC_GPIO_IN_CHANNELS_NUM

8 inward channels on each CPU core

SOC_DEDIC_GPIO_ALLOW_REG_ACCESS

Allow access dedicated GPIO channel by register

SOC_DEDIC_GPIO_HAS_INTERRUPT

Dedicated GPIO has its own interrupt source

SOC_DEDIC_GPIO_OUT_AUTO_ENABLE

Dedicated GPIO output attribution is enabled automatically

SOC_I2C_NUM
SOC_I2C_FIFO_LEN

I2C hardware FIFO depth

SOC_I2C_SUPPORT_SLAVE
SOC_I2C_SUPPORT_HW_CLR_BUS
SOC_I2C_SUPPORT_REF_TICK
SOC_I2C_SUPPORT_APB
SOC_CLK_APLL_SUPPORTED
SOC_APLL_MULTIPLIER_OUT_MIN_HZ
SOC_APLL_MULTIPLIER_OUT_MAX_HZ
SOC_APLL_MIN_HZ
SOC_APLL_MAX_HZ
SOC_I2S_NUM
SOC_I2S_HW_VERSION_1
SOC_I2S_SUPPORTS_APLL
SOC_I2S_SUPPORTS_DMA_EQUAL
SOC_I2S_SUPPORTS_LCD_CAMERA
SOC_I2S_APLL_MIN_FREQ
SOC_I2S_APLL_MAX_FREQ
SOC_I2S_APLL_MIN_RATE
SOC_I2S_LCD_I80_VARIANT
SOC_LCD_I80_SUPPORTED

Intel 8080 LCD is supported

SOC_LCD_I80_BUSES

Only I2S0 has LCD mode

SOC_LCD_I80_BUS_WIDTH

Intel 8080 bus width

SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
SOC_LEDC_SUPPORT_APB_CLOCK
SOC_LEDC_SUPPORT_REF_TICK
SOC_LEDC_SUPPORT_XTAL_CLOCK
SOC_LEDC_CHANNEL_NUM
SOC_LEDC_TIMER_BIT_WIDE_NUM
SOC_LEDC_SUPPORT_FADE_STOP
SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
SOC_MPU_MIN_REGION_SIZE
SOC_MPU_REGIONS_MAX_NUM
SOC_MPU_REGION_RO_SUPPORTED
SOC_MPU_REGION_WO_SUPPORTED
SOC_PCNT_GROUPS
SOC_PCNT_UNITS_PER_GROUP
SOC_PCNT_CHANNELS_PER_UNIT
SOC_PCNT_THRES_POINT_PER_UNIT
SOC_RMT_GROUPS

One RMT group

SOC_RMT_TX_CANDIDATES_PER_GROUP

Number of channels that capable of Transmit in each group

SOC_RMT_RX_CANDIDATES_PER_GROUP

Number of channels that capable of Receive in each group

SOC_RMT_CHANNELS_PER_GROUP

Total 4 channels

SOC_RMT_MEM_WORDS_PER_CHANNEL

Each channel owns 64 words memory (1 word = 4 Bytes)

SOC_RMT_SUPPORT_RX_DEMODULATION

Support signal demodulation on RX path (i.e. remove carrier)

SOC_RMT_SUPPORT_TX_ASYNC_STOP

Support stop transmission asynchronously

SOC_RMT_SUPPORT_TX_LOOP_COUNT

Support transmiting specified number of cycles in loop mode

SOC_RMT_SUPPORT_TX_SYNCHRO

Support coordinate a group of TX channels to start simultaneously

SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY

TX carrier can be modulated to data phase only

SOC_RMT_SUPPORT_REF_TICK

Support set REF_TICK as the RMT clock source

SOC_RMT_SUPPORT_APB

Support set APB as the RMT clock source

SOC_RMT_CHANNEL_CLK_INDEPENDENT

Can select different source clock for each channel

SOC_RTCIO_PIN_COUNT
SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
SOC_RTCIO_HOLD_SUPPORTED
SOC_RTCIO_WAKE_SUPPORTED
SOC_SIGMADELTA_NUM
SOC_SIGMADELTA_CHANNEL_NUM
SOC_SPI_HD_BOTH_INOUT_SUPPORTED
SOC_SPI_PERIPH_NUM
SOC_SPI_DMA_CHAN_NUM
SOC_SPI_PERIPH_CS_NUM(i)
SOC_SPI_MAXIMUM_BUFFER_SIZE
SOC_SPI_MAX_PRE_DIVIDER
SOC_SPI_SUPPORT_DDRCLK
SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
SOC_SPI_SUPPORT_CD_SIG
SOC_SPI_SUPPORT_CONTINUOUS_TRANS
SOC_SPI_SUPPORT_SLAVE_HD_VER2

The SPI Slave half duplex mode has been updated greatly in ESP32-S2.

SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
SOC_MEMSPI_IS_INDEPENDENT
SOC_SPI_SUPPORT_OCT
SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
SOC_SYSTIMER_COUNTER_NUM
SOC_SYSTIMER_ALARM_NUM
SOC_SYSTIMER_BIT_WIDTH_LO
SOC_SYSTIMER_BIT_WIDTH_HI
SOC_SYSTIMER_SUPPORTED
SOC_TIMER_GROUPS
SOC_TIMER_GROUP_TIMERS_PER_GROUP
SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
SOC_TIMER_GROUP_SUPPORT_XTAL
SOC_TIMER_GROUP_SUPPORT_APB
SOC_TIMER_GROUP_TOTAL_TIMERS
SOC_TOUCH_VERSION_2

Hardware version of touch sensor

SOC_TOUCH_SENSOR_NUM

15 Touch channels

SOC_TOUCH_PROXIMITY_CHANNEL_NUM
SOC_TOUCH_PAD_THRESHOLD_MAX

If set touch threshold max value, The touch sensor can’t be in touched status

SOC_TOUCH_PAD_MEASURE_WAIT_MAX

The timer frequency is 8Mhz, the max value is 0xff

SOC_TWAI_BRP_MIN
SOC_TWAI_BRP_MAX
SOC_TWAI_SUPPORTS_RX_STATUS
SOC_UART_NUM
SOC_UART_SUPPORT_WAKEUP_INT

Support UART wakeup interrupt

SOC_UART_SUPPORT_REF_TICK

Support REF_TICK as the clock source

SOC_UART_FIFO_LEN

The UART hardware FIFO length

SOC_UART_BITRATE_MAX

Max bit rate supported by UART

SOC_SPIRAM_SUPPORTED
SOC_USB_PERIPH_NUM
SOC_SHA_DMA_MAX_BUFFER_SIZE
SOC_SHA_SUPPORT_DMA
SOC_SHA_SUPPORT_RESUME
SOC_SHA_CRYPTO_DMA
SOC_SHA_SUPPORT_SHA1
SOC_SHA_SUPPORT_SHA224
SOC_SHA_SUPPORT_SHA256
SOC_SHA_SUPPORT_SHA384
SOC_SHA_SUPPORT_SHA512
SOC_SHA_SUPPORT_SHA512_224
SOC_SHA_SUPPORT_SHA512_256
SOC_SHA_SUPPORT_SHA512_T
SOC_RSA_MAX_BIT_LEN
SOC_AES_SUPPORT_DMA
SOC_AES_SUPPORT_GCM
SOC_SECURE_BOOT_V2_RSA
SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
SOC_FLASH_ENCRYPTION_XTS_AES
SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS
SOC_FLASH_ENCRYPTION_XTS_AES_128
SOC_FLASH_ENCRYPTION_XTS_AES_256
SOC_AES_CRYPTO_DMA
SOC_AES_SUPPORT_AES_128
SOC_AES_SUPPORT_AES_192
SOC_AES_SUPPORT_AES_256
SOC_PHY_DIG_REGS_MEM_SIZE
SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
SOC_SPI_MEM_SUPPORT_SW_SUSPEND
SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
SOC_PM_SUPPORT_EXT_WAKEUP
SOC_PM_SUPPORT_WIFI_WAKEUP
SOC_PM_SUPPORT_WIFI_PD
SOC_PM_SUPPORT_RTC_PERIPH_PD
SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP

Supports waking up from touch pad trigger

SOC_PM_SUPPORT_RTC_FAST_MEM_PD
SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
SOC_COEX_HW_PTI
SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
SOC_WIFI_HW_TSF

Support hardware TSF

SOC_WIFI_FTM_SUPPORT

FTM Support

SOC_WIFI_GCMP_SUPPORT

GCMP Support(GCMP128 and GCMP256)