Programming ULP FSM Coprocessor Using C Macros (Legacy)

In addition to the existing binutils port for the ESP32 ULP coprocessor, it is possible to generate programs for the ULP FSM coprocessor by embedding assembly-like macros into an ESP32 application. Here is an example how this can be done:

const ulp_insn_t program[] = {
    I_MOVI(R3, 16),         // R3 <- 16
    I_LD(R0, R3, 0),        // R0 <- RTC_SLOW_MEM[R3 + 0]
    I_LD(R1, R3, 1),        // R1 <- RTC_SLOW_MEM[R3 + 1]
    I_ADDR(R2, R0, R1),     // R2 <- R0 + R1
    I_ST(R2, R3, 2),        // R2 -> RTC_SLOW_MEM[R2 + 2]
    I_HALT()
};
size_t load_addr = 0;
size_t size = sizeof(program)/sizeof(ulp_insn_t);
ulp_process_macros_and_load(load_addr, program, &size);
ulp_run(load_addr);

The program array is an array of ulp_insn_t, i.e., ULP coprocessor instructions. Each I_XXX preprocessor define translates into a single 32-bit instruction. Arguments of these preprocessor defines can be register numbers (R0 — R3) and literal constants. See the API reference section at the end of this guide for descriptions of instructions and arguments they take.

Note

Because some of the instruction macros expand to inline function calls, defining such array in global scope will cause the compiler to produce an "initializer element is not constant" error. To fix this error, move the definition of instructions array into local scope.

Note

Load, store and move instructions use addresses expressed in 32-bit words. Address 0 corresponds to the first word of RTC_SLOW_MEM. This is different to how address arguments are handled in assembly code of the same instructions. See the section Note About Addressing for more details for reference.

To generate branch instructions, special M_ preprocessor defines are used. M_LABEL define can be used to define a branch target. Label identifier is a 16-bit integer. M_Bxxx defines can be used to generate branch instructions with target set to a particular label.

Implementation note: these M_ preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ulp_process_macros_and_load function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the extra ulp_insn_t token which contains the label number.

Here is an example of using labels and branches:

const ulp_insn_t program[] = {
    I_MOVI(R0, 34),         // R0 <- 34
    M_LABEL(1),             // label_1
    I_MOVI(R1, 32),         // R1 <- 32
    I_LD(R1, R1, 0),        // R1 <- RTC_SLOW_MEM[R1]
    I_MOVI(R2, 33),         // R2 <- 33
    I_LD(R2, R2, 0),        // R2 <- RTC_SLOW_MEM[R2]
    I_SUBR(R3, R1, R2),     // R3 <- R1 - R2
    I_ST(R3, R0, 0),        // R3 -> RTC_SLOW_MEM[R0 + 0]
    I_ADDI(R0, R0, 1),      // R0++
    M_BL(1, 64),            // if (R0 < 64) goto label_1
    I_HALT(),
};
RTC_SLOW_MEM[32] = 42;
RTC_SLOW_MEM[33] = 18;
size_t load_addr = 0;
size_t size = sizeof(program)/sizeof(ulp_insn_t);
ulp_process_macros_and_load(load_addr, program, &size);
ulp_run(load_addr);

API Reference

Header File

components/ulp/ulp_fsm/include/esp32/ulp.h
This header file can be included with:
#include "ulp.h"
This header file is a part of the API provided by the ulp component. To declare that your component depends on ulp, add the following to your CMakeLists.txt:
REQUIRES ulp
or
PRIV_REQUIRES ulp

Functions

static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)

Map SoC peripheral register to periph_sel field of RD_REG and WR_REG instructions.

Parameters: reg -- peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals.
Returns: periph_sel value for the peripheral to which this register belongs.

Unions

union ulp_insn

#include <ulp.h>

Instruction format structure.

All ULP instructions are 32 bit long. This union contains field layouts used by all of the supported instructions. This union also includes a special "macro" instruction layout. This is not a real instruction which can be executed by the CPU. It acts as a token which is removed from the program by the ulp_process_macros_and_load function.

These structures are not intended to be used directly. Preprocessor definitions provided below fill the fields of these structure with the right arguments.

Public Members

uint32_t cycles

Number of cycles to sleep

TBD, cycles used for measurement

uint32_t unused: Unused

uint32_t opcode

Opcode (OPCODE_DELAY)

Opcode (OPCODE_ST)

Opcode (OPCODE_LD)

Opcode (OPCODE_HALT)

Opcode (OPCODE_BRANCH)

Opcode (OPCODE_ALU)

Opcode (OPCODE_WR_REG)

Opcode (OPCODE_RD_REG)

Opcode (OPCODE_ADC)

Opcode (OPCODE_TSENS)

Opcode (OPCODE_I2C)

Opcode (OPCODE_END)

Opcode (OPCODE_MACRO)

struct ulp_insn::[anonymous] delay: Format of DELAY instruction

uint32_t dreg

Register which contains data to store

Register where the data should be loaded to

Register which contains target PC, expressed in words (used if .reg == 1)

Destination register

Register where to store ADC result

Register where to store temperature measurement result

Destination register (for SUB_OPCODE_MACRO_LABELPC) >

uint32_t sreg

Register which contains address in RTC memory (expressed in words)

Register with operand A

uint32_t unused1: Unused

uint32_t offset

Offset to add to sreg

Absolute value of target PC offset w.r.t. current PC, expressed in words

uint32_t unused2: Unused

uint32_t sub_opcode

Sub opcode (SUB_OPCODE_ST)

Sub opcode (SUB_OPCODE_BX)

Sub opcode (SUB_OPCODE_B)

Sub opcode (SUB_OPCODE_BS)

Sub opcode (SUB_OPCODE_ALU_REG)

Sub opcode (SUB_OPCODE_ALU_CNT)

Sub opcode (SUB_OPCODE_ALU_IMM)

Sub opcode (SUB_OPCODE_WAKEUP)

Sub opcode (SUB_OPCODE_SLEEP)

SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH or SUB_OPCODE_MACRO_LABELPC

struct ulp_insn::[anonymous] st: Format of ST instruction

struct ulp_insn::[anonymous] ld: Format of LD instruction

struct ulp_insn::[anonymous] halt: Format of HALT instruction

uint32_t addr

Target PC, expressed in words (used if .reg == 0)

Address within either RTC_CNTL, RTC_IO, or SARADC

uint32_t reg: Target PC in register (1) or immediate (0)

uint32_t type: Jump condition (BX_JUMP_TYPE_xxx)

struct ulp_insn::[anonymous] bx: Format of BRANCH instruction (absolute address)

uint32_t imm

Immediate value to compare against

Immediate value of operand

Immediate value of operand B

uint32_t cmp

Comparison to perform: B_CMP_L or B_CMP_GE

Comparison to perform: JUMPS_LT, JUMPS_GE or JUMPS_LE

uint32_t sign: Sign of target PC offset: 0: positive, 1: negative

struct ulp_insn::[anonymous] b: Format of BRANCH instruction (relative address, conditional on R0)

struct ulp_insn::[anonymous] bs: Format of BRANCH instruction (relative address, conditional on the stage counter)

uint32_t treg: Register with operand B

uint32_t sel

Operation to perform, one of ALU_SEL_xxx

Operation to perform, one of ALU_SEL_Sxxx

struct ulp_insn::[anonymous] alu_reg: Format of ALU instruction (both sources are registers)

struct ulp_insn::[anonymous] alu_reg_s: Format of ALU instruction (stage counter and an immediate)

struct ulp_insn::[anonymous] alu_imm: Format of ALU instruction (one source is an immediate)

uint32_t periph_sel: Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)

uint32_t data

8 bits of data to write

8 bits of data for write operation

uint32_t low: Low bit

uint32_t high: High bit

struct ulp_insn::[anonymous] wr_reg: Format of WR_REG instruction

struct ulp_insn::[anonymous] rd_reg: Format of RD_REG instruction

uint32_t mux: Select SARADC pad (mux + 1)

uint32_t sar_sel: Select SARADC0 (0) or SARADC1 (1)

struct ulp_insn::[anonymous] adc: Format of ADC instruction

uint32_t wait_delay: Cycles to wait after measurement is done

uint32_t reserved: Reserved, set to 0

struct ulp_insn::[anonymous] tsens: Format of TSENS instruction

uint32_t i2c_addr: I2C slave address

uint32_t low_bits: low bit of range for write operation (lower bits are masked)

uint32_t high_bits: high bit of range for write operation (higher bits are masked)

uint32_t i2c_sel: index of slave address register [7:0]

uint32_t rw: Write (1) or read (0)

struct ulp_insn::[anonymous] i2c: Format of I2C instruction

uint32_t wakeup: Set to 1 to wake up chip

struct ulp_insn::[anonymous] end: Format of END instruction with wakeup

uint32_t cycle_sel: Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from

struct ulp_insn::[anonymous] sleep: Format of END instruction with sleep

uint32_t label: Label number

struct ulp_insn::[anonymous] macro: Format of tokens used by MACROs

uint32_t instruction: Encoded instruction for ULP coprocessor

Macros

R0: general purpose register 0

R1: general purpose register 1

R2: general purpose register 2

R3: general purpose register 3

OPCODE_WR_REG: Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC)

OPCODE_RD_REG: Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC)

RD_REG_PERIPH_RTC_CNTL: Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions

RD_REG_PERIPH_RTC_IO: Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions

RD_REG_PERIPH_SENS: Identifier of SARADC peripheral for RD_REG and WR_REG instructions

RD_REG_PERIPH_RTC_I2C: Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions

OPCODE_I2C: Instruction: read/write I2C

SUB_OPCODE_I2C_RD: I2C read

SUB_OPCODE_I2C_WR: I2C write

OPCODE_DELAY: Instruction: delay (nop) for a given number of cycles

OPCODE_ADC: Instruction: SAR ADC measurement

OPCODE_ST: Instruction: store indirect to RTC memory

SUB_OPCODE_ST: Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register

OPCODE_ALU: Arithmetic instructions

SUB_OPCODE_ALU_REG: Arithmetic instruction, both source values are in register

SUB_OPCODE_ALU_IMM: Arithmetic instruction, one source value is an immediate

SUB_OPCODE_ALU_CNT: Arithmetic instruction, stage counter and an immediate

ALU_SEL_ADD: Addition

ALU_SEL_SUB: Subtraction

ALU_SEL_AND: Logical AND

ALU_SEL_OR: Logical OR

ALU_SEL_MOV: Copy value (immediate to destination register or source register to destination register

ALU_SEL_LSH: Shift left by given number of bits

ALU_SEL_RSH: Shift right by given number of bits

ALU_SEL_SINC: Increment the stage counter

ALU_SEL_SDEC: Decrement the stage counter

ALU_SEL_SRST: Reset the stage counter

OPCODE_BRANCH: Branch instructions

SUB_OPCODE_BX: Branch to absolute PC (immediate or in register)

SUB_OPCODE_BR: Branch to relative PC, conditional on R0

SUB_OPCODE_BS: Branch to relative PC, conditional on the stage counter

BX_JUMP_TYPE_DIRECT: Unconditional jump

BX_JUMP_TYPE_ZERO: Branch if last ALU result is zero

BX_JUMP_TYPE_OVF: Branch if last ALU operation caused and overflow

SUB_OPCODE_B: Branch to a relative offset

B_CMP_L: Branch if R0 is less than an immediate

B_CMP_GE: Branch if R0 is greater than or equal to an immediate

JUMPS_LT: Branch if the stage counter <

JUMPS_GE: Branch if the stage counter >=

JUMPS_LE: Branch if the stage counter <=

OPCODE_END: Stop executing the program

SUB_OPCODE_END: Stop executing the program and optionally wake up the chip

SUB_OPCODE_SLEEP: Stop executing the program and run it again after selected interval

OPCODE_TSENS: Instruction: temperature sensor measurement. Poor accuracy, not recommended for most use-cases

OPCODE_HALT: Halt the coprocessor

OPCODE_LD: Indirect load lower 16 bits from RTC memory

OPCODE_MACRO: Not a real opcode. Used to identify labels and branches in the program

SUB_OPCODE_MACRO_LABEL: Label macro

SUB_OPCODE_MACRO_BRANCH: Branch macro

SUB_OPCODE_MACRO_LABELPC: Label pointer macro

I_DELAY(cycles_): Delay (nop) for a given number of cycles

I_HALT()

Halt the coprocessor.

This instruction halts the coprocessor, but keeps ULP timer active. As such, ULP program will be restarted again by timer. To stop the program and prevent the timer from restarting the program, use I_END(0) instruction.

I_WR_REG(reg, low_bit, high_bit, val)

Write literal value to a peripheral register

reg[high_bit : low_bit] = val This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.

I_RD_REG(reg, low_bit, high_bit)

Read from peripheral register into R0

R0 = reg[high_bit : low_bit] This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.

I_WR_REG_BIT(reg, shift, val)

Set or clear a bit in the peripheral register.

Sets bit (1 << shift) of register reg to value val. This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.

I_WAKE()

Wake the SoC from deep sleep.

This instruction initiates wake up from deep sleep. Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup triggered by the ULP before going into deep sleep. Note that ULP program will still keep running until the I_HALT instruction, and it will still be restarted by timer at regular intervals, even when the SoC is woken up.

To stop the ULP program, use I_HALT instruction.

To disable the timer which start ULP program, use I_END() instruction. I_END instruction clears the RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG register, which controls the ULP timer.

I_END()

Stop ULP program timer.

This is a convenience macro which disables the ULP program timer. Once this instruction is used, ULP program will not be restarted anymore until ulp_run function is called.

ULP program will continue running after this instruction. To stop the currently running program, use I_HALT().

I_SLEEP_CYCLE_SEL(timer_idx)

Select the time interval used to run ULP program.

This instructions selects which of the SENS_SLEEP_CYCLES_Sx registers' value is used by the ULP program timer. When the ULP program stops at I_HALT instruction, ULP program timer start counting. When the counter reaches the value of the selected SENS_SLEEP_CYCLES_Sx register, ULP program start running again from the start address (passed to the ulp_run function). There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.

By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP program timer.

I_TSENS(reg_dest, delay)

Perform temperature sensor measurement and store it into reg_dest.

Delay can be set between 1 and ((1 << 14) - 1). Higher values give higher measurement resolution.

I_ADC(reg_dest, adc_idx, pad_idx)

Perform ADC measurement and store result in reg_dest.

adc_idx selects ADC (0 or 1). pad_idx selects ADC pad (0 - 7).

I_ST(reg_val, reg_addr, offset_)

Store value from register reg_val into RTC memory.

The value is written to an offset calculated by adding value of reg_addr register and offset_ field (this offset is expressed in 32-bit words). 32 bits written to RTC memory are built as follows:

bits [31:21] hold the PC of current instruction, expressed in 32-bit words
bits [20:18] = 3'b0
bits [17:16] reg_addr (0..3)
bits [15:0] are assigned the contents of reg_val

RTC_SLOW_MEM[addr + offset_] = { insn_PC[10:0], 3'b0, reg_addr, reg_val[15:0] }

I_LD(reg_dest, reg_addr, offset_)

Load value from RTC memory into reg_dest register.

Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and value of offset_.

I_BL(pc_offset, imm_value)

Branch relative if R0 less than immediate value.

pc_offset is expressed in words, and can be from -127 to 127 imm_value is a 16-bit value to compare R0 against

I_BGE(pc_offset, imm_value)

Branch relative if R0 greater or equal than immediate value.

pc_offset is expressed in words, and can be from -127 to 127 imm_value is a 16-bit value to compare R0 against

I_BXR(reg_pc)

Unconditional branch to absolute PC, address in register.

reg_pc is the register which contains address to jump to. Address is expressed in 32-bit words.

I_BXI(imm_pc)

Unconditional branch to absolute PC, immediate address.

Address imm_pc is expressed in 32-bit words.

I_BXZR(reg_pc)

Branch to absolute PC if ALU result is zero, address in register.

reg_pc is the register which contains address to jump to. Address is expressed in 32-bit words.

I_BXZI(imm_pc)

Branch to absolute PC if ALU result is zero, immediate address.

Address imm_pc is expressed in 32-bit words.

I_BXFR(reg_pc)

Branch to absolute PC if ALU overflow, address in register

reg_pc is the register which contains address to jump to. Address is expressed in 32-bit words.

I_BXFI(imm_pc)

Branch to absolute PC if ALU overflow, immediate address

Address imm_pc is expressed in 32-bit words.

I_ADDR(reg_dest, reg_src1, reg_src2): Addition: dest = src1 + src2

I_SUBR(reg_dest, reg_src1, reg_src2): Subtraction: dest = src1 - src2

I_ANDR(reg_dest, reg_src1, reg_src2): Logical AND: dest = src1 & src2

I_ORR(reg_dest, reg_src1, reg_src2): Logical OR: dest = src1 | src2

I_MOVR(reg_dest, reg_src): Copy: dest = src

I_LSHR(reg_dest, reg_src, reg_shift): Logical shift left: dest = src << shift

I_RSHR(reg_dest, reg_src, reg_shift): Logical shift right: dest = src >> shift

I_ADDI(reg_dest, reg_src, imm_): Add register and an immediate value: dest = src1 + imm

I_SUBI(reg_dest, reg_src, imm_): Subtract register and an immediate value: dest = src - imm

I_ANDI(reg_dest, reg_src, imm_): Logical AND register and an immediate value: dest = src & imm

I_ORI(reg_dest, reg_src, imm_): Logical OR register and an immediate value: dest = src | imm

I_MOVI(reg_dest, imm_): Copy an immediate value into register: dest = imm

I_LSHI(reg_dest, reg_src, imm_): Logical shift left register value by an immediate: dest = src << imm

I_RSHI(reg_dest, reg_src, imm_): Logical shift right register value by an immediate: dest = val >> imm

M_LABEL(label_num)

Define a label with number label_num.

This is a macro which doesn't generate a real instruction. The token generated by this macro is removed by ulp_process_macros_and_load function. Label defined using this macro can be used in branch macros defined below.

M_BRANCH(label_num): Token macro used by M_B and M_BX macros. Not to be used directly.

M_LABELPC(label_num): Token macro used by M_MOVL macro. Not to be used directly.

M_MOVL(reg_dest, label_num)

Macro: Move the program counter at the given label into the register. This address can then be used with I_BXR, I_BXZR, I_BXFR, etc.