Chip Revision: v0.0

Known Errors

• [Clock] Audio PLL frequency range is limited
• [Clock] ESP32 cannot be used as the PHY clock source if Wi-Fi and Ethernet are used at the same time
• [CPU] The CPU crashes when the clock frequency switches
• [CPU] CPU has limitations when accessing peripherals in chips
• [CPU] There are limitations to the CPU access to 0x3FF0_0000 ~ 0x3FF1_EFFF and 0x3FF4_0000 ~ 0x3FF7_FFFF address spaces
• [CPU] When the CPU accesses external SRAM through cache, under certain conditions read and write errors occur
• [CPU] When each CPU reads certain different address spaces simultaneously, a read error may occur
• [CPU] When a CPU is interrupted while accessing five specific FIFO registers, subsequent CPU accesses will get halted
• [CPU] When the CPU accesses peripherals and writes a single address repeatedly, some writes may be lost
• [GPIO] For pads with both GPIO and RTC_GPIO functionality, the GPIO pull-up and pull-down configuration register fields are nonfunctional
• [GPIO] Within the same group of GPIO pins, edge interrupts cannot be used together with other interrupts
• [GPIO] When certain RTC peripherals are powered on, the inputs of GPIO36 and GPIO39 will be pulled down for approximately 80 ns
• [LEDC] When the LEDC is in decremental fade mode, a duty overflow error may occur
• [Reset] The Brown-out Reset (BOR) function does not work
• [Reset] A spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deep-sleep
• [Reset] Due to the flash start-up time, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deepsleep
• [TWAI] After losing arbitration, a dominant bit on the 3rd bit of intermission is not interpreted as an SOF
• [TWAI] Message transmitted after bus-off recovery is erroneous
• [TWAI] When the 8th bit of the error delimiter is dominant, the error passive state is not entered
• [TWAI] Error status bit is not frozen during bus-off recovery
• [TWAI] Receiving an erroneous data frame can cause the data bytes of the next received data frame to be invalid
• [TWAI] A negative phase error where |e| > SJW(N) will cause the remaining transmitted bits to be left shifted
• [TWAI] Receive Error Counter (REC) is allowed to change whilst in reset mode or bus-off recovery
• [TWAI] When the RX FIFO overruns with 64 or more messages, the RX FIFO becomes unrecoverable
• [TWAI] Suspend transmission is included even after losing arbitration
• [TWAI] When a stuff error occurs during arbitration whilst being transmitter, any errors in the subsequent error/overload frame will not increase the TEC
• [TWAI] Reading the interrupt register may lead to a transmit interrupt being lost
• [UART] UART fifo_cnt does not indicate the data length in FIFO correctly
• [ULP] ULP coprocessor and touch sensors can not be used in Deep-sleep mode if RTC_PERIPH power domain is powered up
• [RTC-126] RTC Register Read Error After Wake-up from Light-sleep Mode