Serial Peripheral Interface (SPI)

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Is ESP-WROOM-02D module able to connect SPI flash?

The ESP-WROOM-02D module is a Wi-Fi module based on the ESP8266 chip, which supports communication with external SPI flash devices using SPI interfaces. Specifically, the ESP-WROOM-02D module provides 4 SPI interface pins, GPIO12, GPIO13, GPIO14, and GPIO15. Among these pins, GPIO12~GPIO14 can be used as the MISO, MOSI, and SCLK pins for the SPI master interface, and GPIO15 can be used as the CS pin for the SPI slave interface.

To connect an external SPI flash device to the ESP-WROOM-02D module, the MOSI, MISO, SCK, and CS pins of the SPI flash device should be connected to the GPIO12~GPIO14 and GPIO15 pins of the ESP-WROOM-02D module. Additionally, the SPI interface needs to be properly configured and initialized in the firmware to ensure correct communication of ESP8266 with the external SPI flash device.

It should be noted that the model and capacity of the external SPI flash device should be selected based on the specific application requirements. In addition, timing characteristics and reliability of the SPI flash device should be considered to ensure data can be transmitted correctly and stably. Moreover, factors such as environment noise and physical distance between the SPI flash device and the ESP-WROOM-02D module should be considered to improve the reliability and performance of the system as much as possible.

Taking ESP-WROOM-S2 as the slave device and STM32 as MCU, is it possible to download through SPI interface?

No, we use UART0 to download by default. You can also design OTA support yourself in firmware.

What is the difference among SPI0, SPI1, HSPI and VSPI in ESP32?

  • ESP32 has 4 SPIs, SPI0 and SPI1 are two peripherals, also known as MSPI. SPI0 and SPI1 share the same SPI bus (same signals and IOs). The difference is, MSPI CS0 is connected to the main flash for firmware storage, and MSPI CS1 is connected to PSRAM. SPI2 and SPI3 are general-purpose SPIs that are available for customers to use.

  • HSPI represents the above-mentioned SPI2, and VSPI represents the SPI3. The two sets of SPIs are general-purpose SPIs and support QSPI.

The maximum data transmission of SPI DMA on ESP series chips is 4095 bytes. Is it because of hardware limitation?

  • Yes, this is a hardware limitation. A single node in the DMA table can only mount 4095 bytes of data.

  • However, a single SPI DMA transmission can mount more data through several nodes. At this time the maximum data transfer byte number is limited by the hardware register SPI_LL_DATA_MAX_BIT_LEN (whose value varies with different chip series and can be found in ESP-IDF), i.e., max_transfer_sz <= (SPI_LL_DATA_MAX_BIT_LEN / 8).

Does the SPI of the ESP series chip need to perform semaphore synchronization to access three SPI slave devices simultaneously?

  • The same SPI peripheral, as the master, can only communicate with one slave at a time, and CS decides which slave to communicate with. If you connect 3 slave devices to the SPI driver and communicate with them separately, it is okay and recommended.

  • It is recommended to operate devices sharing the same SPI in only one task. Otherwise, it is not thread-safe. Communication needs to be synchronized through semaphores. For specific issues, see SPI Master Driver > Driver Features.

When using an ESP32 board for development and testing based on ESP-IDF release/v4.3, I received the following error log during compilation. What is the reason?

spi_flash:Detected size(8192K) smaller than the size in the binary image header(16384K).Probe failed.

The reason is that the configured flash size is larger than the actual flash size. In order to avoid misuse of a larger address space, the actual flash size is checked.

What is the maximum transmission speed supported by SPI slave?

CHIP: ESP32

ESP32 can support up to 10 M of transmission speed when serves as an SPI slave.

How many bytes of data can be transferred at once using the ESP series chip as an SPI host device in non-DMA mode?

When using the ESP32-S3-WROOM-1 (ESP32-S3R2) module to enable its PSRAM configuration based on the “hello-world” example in ESP-IDF v4.4, the following error is printed. What is the reason?

E (232) spiram: Virtual address not enough for PSRAM!

ESP32-S3R2 chip integrates a 4-wire 2 MB PSRAM, please set PSRAM Mode to Quad mode in menuconfig before your action as follows:

menuconfig > Component config > ESP32S3 Specific > Support for external, SPI connected RAM > SPI RAM config > Mode (QUAD/OCT) of SPI RAM chip in use (Ouad Mode PSRAM)

When using the ESP32-S3-WROOM-2 (ESP32-S3R8V) module to enable the PSRAM configuration based on the “hello-world” example in ESP-IDF v4.4, the following error is printed. What is the reason?

E (453) psram: psram ID read error: 0x00ffff
E (454) cpu start: Failed to init external RAM!

ESP32-S3R8V chip integrates a 8-wire 8 MB PSRAM, please set PSRAM mode to Octal mode in menuconfig before your action as follows:

menuconfig > Component config > ESP32S3 Specific > Support for external, SPI connected RAM > SPI RAM config > Mode (QUAD/OCT) of SPI RAM chip in use (Octal Mode PSRAM)

Does ESP8266 RTOS SDK support full duplex for SPI?

CHIP: ESP8266

No, it doesn’t. Because ESP8266 doesn’t support DMA, in order to improve the transmission performance, the entire FIFO is used. So it can only be half duplex. Please refer to spi readme for more details.

Can the ESP series chips support the 9-bit clock mode of three-wire SPI (i.e., the mode where the first bit indicates whether the following 8 bits are command or data)?

  • Currently, the ESP32, ESP32-S, ESP32-C series chips do not support non-byte aligned data transmission, i.e., they only support 8-bit aligned data transmission. For a detailed explanation of this issue, see Github issue and documentation.

  • Subsequent new versions of the ESP chip may support non-byte aligned data transmission, but there is currently no specific timetable.

After setting a pin of the ESP series chip as the SDA data line, the expected result is that the SDA line should be low when idle, and high when writing data. But why is this pin high when idle upon power-up, and low when writing data? How can I achieve the expected result?

How many bytes can a single DMA Buffer support when the ESP32-C6 is in SPI DMA mode?

  • For ESP32-C6 in SPI DMA mode, a single DMA Buffer supports 4092 bytes at the maximum.

Does ESP32, as an SPI host, support a 30 MHz clock?

  • Not supported. When ESP32 acts as an SPI host, it can support up to 80 MHz CLK when using SPI IO_MUX pins, and supports integer division at 80 MHz.

  • When using GPIO matrix pins, it can support up to 40 MHz CLK. If using the full-duplex transmission mode of GPIO matrix pins, it only supports up to 26 MHz CLK. For detailed instructions, refer to the SPI Master Driver software usage instructions.

Why is there a difference in the MISO/MOSI status of the ESP32 and subsequent chips in SPI half-duplex mode?

In half-duplex TX mode, the ESP32 by default pulls the unused MISO line to a low level, while other chips except for the ESP32 default to a high level, which is a normal phenomenon. If you need to pull other chips except for the ESP32 to a low level, you can set SPI_Q_POL to 0.

Is the Handshake pin mandatory when using an ESP series product as an SPI slave device?

  • The Handshake pin is not mandatory; whether it is required depends on the specific application. In the following official solutions, the Handshake pin is part of the protocol design and is a required signal:

    • SPI AT Solution for ESP-AT (ESP32-C2/C3/C5/C6/C61, etc.): In order to allow Espressif devices, which act as SPI slaves, to actively report data, an additional Handshake line is used. The slave pulls this signal high to notify the master that data is available for reception or that data transmission is permitted. Therefore, the Handshake pin is required in the SPI AT protocol.

    • ESP-Hosted/ESP-Hosted-MCU SPI mode: The protocol explicitly requires additional GPIO connections such as Handshake, Data Ready, and Reset/EN, in addition to the standard Quad SPI. Among them, the Handshake pin is used to indicate that the Espressif peripheral is ready for an SPI transaction, and is a required signal. For more details, please refer to the ESP-Hosted SPI FD (Full Duplex) Operation and SPI Communication Protocol documentation.

  • Additionally, the official ESP-IDF spi_slave example also defaults to using a single Handshake line for synchronous control.

  • If you are implementing an SPI slave protocol using an ESP product, from a hardware and driver perspective, SPI itself only requires four signal lines: SCLK, MOSI, MISO, and CS. Whether to add a Handshake line depends on the design of the upper-layer protocol and synchronization requirements. For example, the official ESP-IDF spi_slave_hd example does not require a Handshake line.

When using the ESP32-C3 as an SPI slave with the receiver example, all data is incorrect when the master MCU clock is 20 MHz, and there is severe packet loss at 10 MHz. How to solve this problem?

The ESP32-C3 SPI slave receiver example requires handshake line control (the handshake line being pulled high indicates that the DMA is properly mounted). The handshake protocol must be correctly implemented for normal data transmission and reception. If you do not want to use a physical handshake line, you can switch to the spi_slave_hd half-duplex scheme, which has an internal mechanism for cyclically mounting DMA buffers, resulting in more stable transmission rates.


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