Parallel IO

[中文]

Introduction

[Parallel IO Peripheral] is a general parallel interface that can be used to connect external devices such as LED matrices, LCD displays, printers, and cameras. This peripheral has independent TX and RX units. Each unit can have up to 8 or 16 data signals and 1 or 2 clock signals.

The TX and RX drivers of the Parallel IO peripheral are independently designed and can be used by including the header files driver/parlio_tx.h or driver/parlio_rx.h.

API Reference

Header File

  • components/esp_driver_parlio/include/driver/parlio_types.h

  • This header file can be included with:

    #include "driver/parlio_types.h"

  • This header file is a part of the API provided by the esp_driver_parlio component. To declare that your component depends on esp_driver_parlio, add the following to your CMakeLists.txt:

    REQUIRES esp_driver_parlio

    or

    PRIV_REQUIRES esp_driver_parlio

Type Definitions

typedef struct parlio_tx_unit_t *parlio_tx_unit_handle_t

Type of Parallel IO TX unit handle.

typedef struct parlio_rx_unit_t *parlio_rx_unit_handle_t

Type of Parallel IO RX unit handle.

typedef struct parlio_rx_delimiter_t *parlio_rx_delimiter_handle_t

Type of Parallel IO RX frame delimiter handle.

Header File

Macros

PARLIO_TX_UNIT_MAX_DATA_WIDTH

Maximum data width of TX unit.

PARLIO_RX_UNIT_MAX_DATA_WIDTH

Maximum data width of RX unit.

Type Definitions

typedef soc_periph_parlio_clk_src_t parlio_clock_source_t

Parallel IO clock source.

Note

User should select the clock source based on the power and resolution requirement

Enumerations

enum parlio_sample_edge_t

Parallel IO sample edge.

Values:

enumerator PARLIO_SAMPLE_EDGE_NEG

Sample data on falling edge of clock

enumerator PARLIO_SAMPLE_EDGE_POS

Sample data on rising edge of clock

enum parlio_bit_pack_order_t

Parallel IO bit packing order.

Data in memory: Byte 0: MSB < B0.7 B0.6 B0.5 B0.4 B0.3 B0.2 B0.1 B0.0 > LSB Byte 1: MSB < B1.7 B1.6 B1.5 B1.4 B1.3 B1.2 B1.1 B1.0 > LSB

Output on line (PARLIO_BIT_PACK_ORDER_LSB): Cycle 0 Cycle 1 Cycle 2 &#8212;> time GPIO 0: B0.0 B0.4 B1.0 GPIO 1: B0.1 B0.5 B1.1 GPIO 2: B0.2 B0.6 B1.2 GPIO 3: B0.3 B0.7 B1.3

Output on line (PARLIO_BIT_PACK_ORDER_MSB): Cycle 0 Cycle 1 Cycle 2 &#8212;> time GPIO 0: B0.4 B0.0 B1.4 GPIO 1: B0.5 B0.1 B1.5 GPIO 2: B0.6 B0.2 B1.6 GPIO 3: B0.7 B0.3 B1.7

Values:

enumerator PARLIO_BIT_PACK_ORDER_LSB

Bit pack order: LSB

enumerator PARLIO_BIT_PACK_ORDER_MSB

Bit pack order: MSB

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